Unified Coverage Report :: Module

Line Coverage for Module : prim_intr_hw ( parameter Width=1,FlopOutput=1,IntrT="Status" )
Line Coverage for Module self-instances :

SCORE	LINE
86.94	90.00

tb.dut.intr_hw_pkt_received

SCORE	LINE
86.94	90.00

tb.dut.intr_hw_pkt_sent

SCORE	LINE
86.94	90.00

tb.dut.intr_av_out_empty

SCORE	LINE
86.94	90.00

tb.dut.intr_rx_full

SCORE	LINE
86.94	90.00

tb.dut.intr_av_setup_empty

	Line No.	Total	Covered	Percent
TOTAL		10	9	90.00
ALWAYS	75	4	3	75.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	83	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
ALWAYS	95	3	3	100.00



74                          always_ff @(posedge clk_i or negedge rst_ni) begin
75         2/2                if (!rst_ni) test_q <= '0;
           Tests:       T1 T2 T3  | T1 T2 T3 
76         1/2     ==>        else if (reg2hw_intr_test_qe_i) test_q <= reg2hw_intr_test_q_i;
           Tests:       T1 T2 T3 
                        MISSING_ELSE
77                          end
78                      
79                          // TODO: In Status type, INTR_STATE is better to be external type and RO.
80                          assign hw2reg_intr_state_de_o = 1'b 1; // always represent the status
81         1/1              assign hw2reg_intr_state_d_o  = event_intr_i | test_q;
           Tests:       T1 T2 T3 
82                      
83         1/1              assign status = event_intr_i | test_q;
           Tests:       T1 T2 T3 
84                      
85                          // To make the timing same to event type, status signal does not use CSR.q,
86                          // rather the input of the CSR.
87                          logic unused_reg2hw;
88         1/1              assign unused_reg2hw = ^reg2hw_intr_state_q_i;
           Tests:       T1 T2 T3 
89                        end : g_intr_status
90                      
91                      
92                        if (FlopOutput == 1) begin : gen_flop_intr_output
93                          // flop the interrupt output
94                          always_ff @(posedge clk_i or negedge rst_ni) begin
95         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
96         1/1                  intr_o <= '0;
           Tests:       T1 T2 T3 
97                            end else begin
98         1/1                  intr_o <= status & reg2hw_intr_enable_q_i;
           Tests:       T1 T2 T3

Line Coverage for Module : prim_intr_hw ( parameter Width=1,FlopOutput=1,IntrT="Event" )
Line Coverage for Module self-instances :

SCORE	LINE
93.75	100.00

tb.dut.intr_disconnected

SCORE	LINE
89.58	100.00

tb.dut.intr_powered

SCORE	LINE
93.75	100.00

tb.dut.intr_host_lost

SCORE	LINE
89.58	100.00

tb.dut.intr_link_reset

SCORE	LINE
89.58	100.00

tb.dut.intr_link_suspend

SCORE	LINE
93.75	100.00

tb.dut.intr_link_resume

SCORE	LINE
91.67	100.00

tb.dut.intr_av_overflow

SCORE	LINE
89.58	100.00

tb.dut.intr_link_in_err

SCORE	LINE
93.75	100.00

tb.dut.intr_link_out_err

SCORE	LINE
93.75	100.00

tb.dut.intr_rx_crc_err

SCORE	LINE
93.75	100.00

tb.dut.intr_rx_pid_err

SCORE	LINE
93.75	100.00

tb.dut.intr_rx_bitstuff_err

SCORE	LINE
89.58	100.00

tb.dut.intr_frame

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	62	1	1	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	67	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
ALWAYS	95	3	3	100.00



61                          logic  [Width-1:0]    new_event;
62         1/1              assign new_event =
           Tests:       T1 T2 T3 
63                                     (({Width{reg2hw_intr_test_qe_i}} & reg2hw_intr_test_q_i) | event_intr_i);
64         1/1              assign hw2reg_intr_state_de_o = |new_event;
           Tests:       T1 T2 T3 
65                          // for scalar interrupts, this resolves to '1' with new event
66                          // for vector interrupts, new events are OR'd in to existing interrupt state
67         1/1              assign hw2reg_intr_state_d_o  =  new_event | reg2hw_intr_state_q_i;
           Tests:       T1 T2 T3 
68                      
69         1/1              assign status = reg2hw_intr_state_q_i ;
           Tests:       T1 T2 T3 
70                        end : g_intr_event
71                        else if (IntrT == "Status") begin : g_intr_status
72                          logic [Width-1:0] test_q; // Storing test. Cleared by SW
73                      
74                          always_ff @(posedge clk_i or negedge rst_ni) begin
75                            if (!rst_ni) test_q <= '0;
76                            else if (reg2hw_intr_test_qe_i) test_q <= reg2hw_intr_test_q_i;
77                          end
78                      
79                          // TODO: In Status type, INTR_STATE is better to be external type and RO.
80                          assign hw2reg_intr_state_de_o = 1'b 1; // always represent the status
81                          assign hw2reg_intr_state_d_o  = event_intr_i | test_q;
82                      
83                          assign status = event_intr_i | test_q;
84                      
85                          // To make the timing same to event type, status signal does not use CSR.q,
86                          // rather the input of the CSR.
87                          logic unused_reg2hw;
88                          assign unused_reg2hw = ^reg2hw_intr_state_q_i;
89                        end : g_intr_status
90                      
91                      
92                        if (FlopOutput == 1) begin : gen_flop_intr_output
93                          // flop the interrupt output
94                          always_ff @(posedge clk_i or negedge rst_ni) begin
95         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
96         1/1                  intr_o <= '0;
           Tests:       T1 T2 T3 
97                            end else begin
98         1/1                  intr_o <= status & reg2hw_intr_enable_q_i;
           Tests:       T1 T2 T3

Cond Coverage for Module : prim_intr_hw ( parameter Width=1,FlopOutput=1,IntrT="Status" )
Cond Coverage for Module self-instances :

SCORE	COND
86.94	77.78

tb.dut.intr_hw_pkt_received

SCORE	COND
86.94	77.78

tb.dut.intr_hw_pkt_sent

SCORE	COND
86.94	77.78

tb.dut.intr_av_out_empty

SCORE	COND
86.94	77.78

tb.dut.intr_rx_full

SCORE	COND
86.94	77.78

tb.dut.intr_av_setup_empty

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (event_intr_i | g_intr_status.test_q)
             ------1-----   ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       83
 EXPRESSION (event_intr_i | g_intr_status.test_q)
             ------1-----   ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T30,T33,T34
1	0	Covered	T1,T2,T3
1	1	Covered	T30,T33,T34

Cond Coverage for Module : prim_intr_hw ( parameter Width=1,FlopOutput=1,IntrT="Event" )
Cond Coverage for Module self-instances :

SCORE	COND
93.75	75.00

tb.dut.intr_disconnected

SCORE	COND
89.58	58.33

tb.dut.intr_powered

SCORE	COND
93.75	75.00

tb.dut.intr_host_lost

SCORE	COND
89.58	58.33

tb.dut.intr_link_reset

SCORE	COND
89.58	58.33

tb.dut.intr_link_suspend

SCORE	COND
93.75	75.00

tb.dut.intr_link_resume

SCORE	COND
91.67	66.67

tb.dut.intr_av_overflow

SCORE	COND
89.58	58.33

tb.dut.intr_link_in_err

SCORE	COND
93.75	75.00

tb.dut.intr_link_out_err

SCORE	COND
93.75	75.00

tb.dut.intr_rx_crc_err

SCORE	COND
93.75	75.00

tb.dut.intr_rx_pid_err

SCORE	COND
93.75	75.00

tb.dut.intr_rx_bitstuff_err

SCORE	COND
89.58	58.33

tb.dut.intr_frame

	Total	Covered	Percent
Conditions	12	9	75.00
Logical	12	9	75.00
Non-Logical	0	0
Event	0	0

 LINE       62
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Not Covered

 LINE       62
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       67
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T41,T21,T56
1	0	Covered	T1,T2,T3
1	1	Covered	T41,T21,T56

Branch Coverage for Module : prim_intr_hw ( parameter Width=1,FlopOutput=1,IntrT="Status" )
Branch Coverage for Module self-instances :

SCORE	BRANCH
86.94	80.00

tb.dut.intr_hw_pkt_received

SCORE	BRANCH
86.94	80.00

tb.dut.intr_hw_pkt_sent

SCORE	BRANCH
86.94	80.00

tb.dut.intr_av_out_empty

SCORE	BRANCH
86.94	80.00

tb.dut.intr_rx_full

SCORE	BRANCH
86.94	80.00

tb.dut.intr_av_setup_empty

	Line No.	Total	Covered	Percent
Branches		5	4	80.00
IF	75	3	2	66.67
IF	95	2	2	100.00



75               if (!rst_ni) test_q <= '0;
                 -1-  
                 ==>
76               else if (reg2hw_intr_test_qe_i) test_q <= reg2hw_intr_test_q_i;
                      -2-  
                 ==>
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3



95               if (!rst_ni) begin
                 -1-  
96                 intr_o <= '0;
                   ==>
97               end else begin
98                 intr_o <= status & reg2hw_intr_enable_q_i;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Branch Coverage for Module : prim_intr_hw ( parameter Width=1,FlopOutput=1,IntrT="Event" )
Branch Coverage for Module self-instances :

SCORE	BRANCH
93.75	100.00

tb.dut.intr_disconnected

SCORE	BRANCH
89.58	100.00

tb.dut.intr_powered

SCORE	BRANCH
93.75	100.00

tb.dut.intr_host_lost

SCORE	BRANCH
89.58	100.00

tb.dut.intr_link_reset

SCORE	BRANCH
89.58	100.00

tb.dut.intr_link_suspend

SCORE	BRANCH
93.75	100.00

tb.dut.intr_link_resume

SCORE	BRANCH
91.67	100.00

tb.dut.intr_av_overflow

SCORE	BRANCH
89.58	100.00

tb.dut.intr_link_in_err

SCORE	BRANCH
93.75	100.00

tb.dut.intr_link_out_err

SCORE	BRANCH
93.75	100.00

tb.dut.intr_rx_crc_err

SCORE	BRANCH
93.75	100.00

tb.dut.intr_rx_pid_err

SCORE	BRANCH
93.75	100.00

tb.dut.intr_rx_bitstuff_err

SCORE	BRANCH
89.58	100.00

tb.dut.intr_frame

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	95	2	2	100.00



95               if (!rst_ni) begin
                 -1-  
96                 intr_o <= '0;
                   ==>
97               end else begin
98                 intr_o <= status & reg2hw_intr_enable_q_i;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Module : prim_intr_hw

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
IntrTKind_A	66438	66438	0	0

IntrTKind_A

Name	Attempts	Real Successes
Total	66438	66438
T1	18	18
T2	18	18
T3	18	18
T27	18	18
T28	18	18
T29	18	18
T40	18	18
T41	18	18
T42	18	18
T43	18	18

Line Coverage for Instance : tb.dut.intr_hw_pkt_received

	Line No.	Total	Covered	Percent
TOTAL		10	9	90.00
ALWAYS	75	4	3	75.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	83	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
ALWAYS	95	3	3	100.00



74                          always_ff @(posedge clk_i or negedge rst_ni) begin
75         2/2                if (!rst_ni) test_q <= '0;
           Tests:       T1 T2 T3  | T1 T2 T3 
76         1/2     ==>        else if (reg2hw_intr_test_qe_i) test_q <= reg2hw_intr_test_q_i;
           Tests:       T1 T2 T3 
                        MISSING_ELSE
77                          end
78                      
79                          // TODO: In Status type, INTR_STATE is better to be external type and RO.
80                          assign hw2reg_intr_state_de_o = 1'b 1; // always represent the status
81         1/1              assign hw2reg_intr_state_d_o  = event_intr_i | test_q;
           Tests:       T1 T2 T3 
82                      
83         1/1              assign status = event_intr_i | test_q;
           Tests:       T1 T2 T3 
84                      
85                          // To make the timing same to event type, status signal does not use CSR.q,
86                          // rather the input of the CSR.
87                          logic unused_reg2hw;
88         1/1              assign unused_reg2hw = ^reg2hw_intr_state_q_i;
           Tests:       T1 T2 T3 
89                        end : g_intr_status
90                      
91                      
92                        if (FlopOutput == 1) begin : gen_flop_intr_output
93                          // flop the interrupt output
94                          always_ff @(posedge clk_i or negedge rst_ni) begin
95         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
96         1/1                  intr_o <= '0;
           Tests:       T1 T2 T3 
97                            end else begin
98         1/1                  intr_o <= status & reg2hw_intr_enable_q_i;
           Tests:       T1 T2 T3

Cond Coverage for Instance : tb.dut.intr_hw_pkt_received

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (event_intr_i | g_intr_status.test_q)
             ------1-----   ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T2,T27,T29

 LINE       83
 EXPRESSION (event_intr_i | g_intr_status.test_q)
             ------1-----   ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T2,T27,T29

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T33,T57,T49
1	0	Covered	T2,T27,T29
1	1	Covered	T33,T57,T49

Branch Coverage for Instance : tb.dut.intr_hw_pkt_received

	Line No.	Total	Covered	Percent
Branches		5	4	80.00
IF	75	3	2	66.67
IF	95	2	2	100.00



75               if (!rst_ni) test_q <= '0;
                 -1-  
                 ==>
76               else if (reg2hw_intr_test_qe_i) test_q <= reg2hw_intr_test_q_i;
                      -2-  
                 ==>
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3



95               if (!rst_ni) begin
                 -1-  
96                 intr_o <= '0;
                   ==>
97               end else begin
98                 intr_o <= status & reg2hw_intr_enable_q_i;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.intr_hw_pkt_received

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
IntrTKind_A	3691	3691	0	0

IntrTKind_A

Name	Attempts	Real Successes
Total	3691	3691
T1	1	1
T2	1	1
T3	1	1
T27	1	1
T28	1	1
T29	1	1
T40	1	1
T41	1	1
T42	1	1
T43	1	1

Line Coverage for Instance : tb.dut.intr_hw_pkt_sent

	Line No.	Total	Covered	Percent
TOTAL		10	9	90.00
ALWAYS	75	4	3	75.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	83	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
ALWAYS	95	3	3	100.00



74                          always_ff @(posedge clk_i or negedge rst_ni) begin
75         2/2                if (!rst_ni) test_q <= '0;
           Tests:       T1 T2 T3  | T1 T2 T3 
76         1/2     ==>        else if (reg2hw_intr_test_qe_i) test_q <= reg2hw_intr_test_q_i;
           Tests:       T1 T2 T3 
                        MISSING_ELSE
77                          end
78                      
79                          // TODO: In Status type, INTR_STATE is better to be external type and RO.
80                          assign hw2reg_intr_state_de_o = 1'b 1; // always represent the status
81         1/1              assign hw2reg_intr_state_d_o  = event_intr_i | test_q;
           Tests:       T1 T2 T3 
82                      
83         1/1              assign status = event_intr_i | test_q;
           Tests:       T1 T2 T3 
84                      
85                          // To make the timing same to event type, status signal does not use CSR.q,
86                          // rather the input of the CSR.
87                          logic unused_reg2hw;
88         1/1              assign unused_reg2hw = ^reg2hw_intr_state_q_i;
           Tests:       T1 T2 T3 
89                        end : g_intr_status
90                      
91                      
92                        if (FlopOutput == 1) begin : gen_flop_intr_output
93                          // flop the interrupt output
94                          always_ff @(posedge clk_i or negedge rst_ni) begin
95         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
96         1/1                  intr_o <= '0;
           Tests:       T1 T2 T3 
97                            end else begin
98         1/1                  intr_o <= status & reg2hw_intr_enable_q_i;
           Tests:       T1 T2 T3

Cond Coverage for Instance : tb.dut.intr_hw_pkt_sent

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (event_intr_i | g_intr_status.test_q)
             ------1-----   ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T28,T29,T30

 LINE       83
 EXPRESSION (event_intr_i | g_intr_status.test_q)
             ------1-----   ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T28,T29,T30

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T30,T34,T36
1	0	Covered	T28,T29,T31
1	1	Covered	T30,T34,T36

Branch Coverage for Instance : tb.dut.intr_hw_pkt_sent

	Line No.	Total	Covered	Percent
Branches		5	4	80.00
IF	75	3	2	66.67
IF	95	2	2	100.00



75               if (!rst_ni) test_q <= '0;
                 -1-  
                 ==>
76               else if (reg2hw_intr_test_qe_i) test_q <= reg2hw_intr_test_q_i;
                      -2-  
                 ==>
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3



95               if (!rst_ni) begin
                 -1-  
96                 intr_o <= '0;
                   ==>
97               end else begin
98                 intr_o <= status & reg2hw_intr_enable_q_i;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.intr_hw_pkt_sent

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
IntrTKind_A	3691	3691	0	0

IntrTKind_A

Name	Attempts	Real Successes
Total	3691	3691
T1	1	1
T2	1	1
T3	1	1
T27	1	1
T28	1	1
T29	1	1
T40	1	1
T41	1	1
T42	1	1
T43	1	1

Line Coverage for Instance : tb.dut.intr_av_out_empty

	Line No.	Total	Covered	Percent
TOTAL		10	9	90.00
ALWAYS	75	4	3	75.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	83	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
ALWAYS	95	3	3	100.00



74                          always_ff @(posedge clk_i or negedge rst_ni) begin
75         2/2                if (!rst_ni) test_q <= '0;
           Tests:       T1 T2 T3  | T1 T2 T3 
76         1/2     ==>        else if (reg2hw_intr_test_qe_i) test_q <= reg2hw_intr_test_q_i;
           Tests:       T1 T2 T3 
                        MISSING_ELSE
77                          end
78                      
79                          // TODO: In Status type, INTR_STATE is better to be external type and RO.
80                          assign hw2reg_intr_state_de_o = 1'b 1; // always represent the status
81         1/1              assign hw2reg_intr_state_d_o  = event_intr_i | test_q;
           Tests:       T1 T2 T3 
82                      
83         1/1              assign status = event_intr_i | test_q;
           Tests:       T1 T2 T3 
84                      
85                          // To make the timing same to event type, status signal does not use CSR.q,
86                          // rather the input of the CSR.
87                          logic unused_reg2hw;
88         1/1              assign unused_reg2hw = ^reg2hw_intr_state_q_i;
           Tests:       T1 T2 T3 
89                        end : g_intr_status
90                      
91                      
92                        if (FlopOutput == 1) begin : gen_flop_intr_output
93                          // flop the interrupt output
94                          always_ff @(posedge clk_i or negedge rst_ni) begin
95         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
96         1/1                  intr_o <= '0;
           Tests:       T1 T2 T3 
97                            end else begin
98         1/1                  intr_o <= status & reg2hw_intr_enable_q_i;
           Tests:       T1 T2 T3

Cond Coverage for Instance : tb.dut.intr_av_out_empty

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (event_intr_i | g_intr_status.test_q)
             ------1-----   ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       83
 EXPRESSION (event_intr_i | g_intr_status.test_q)
             ------1-----   ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T58
1	0	Covered	T1,T2,T3
1	1	Covered	T58

Branch Coverage for Instance : tb.dut.intr_av_out_empty

	Line No.	Total	Covered	Percent
Branches		5	4	80.00
IF	75	3	2	66.67
IF	95	2	2	100.00



75               if (!rst_ni) test_q <= '0;
                 -1-  
                 ==>
76               else if (reg2hw_intr_test_qe_i) test_q <= reg2hw_intr_test_q_i;
                      -2-  
                 ==>
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3



95               if (!rst_ni) begin
                 -1-  
96                 intr_o <= '0;
                   ==>
97               end else begin
98                 intr_o <= status & reg2hw_intr_enable_q_i;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.intr_av_out_empty

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
IntrTKind_A	3691	3691	0	0

IntrTKind_A

Name	Attempts	Real Successes
Total	3691	3691
T1	1	1
T2	1	1
T3	1	1
T27	1	1
T28	1	1
T29	1	1
T40	1	1
T41	1	1
T42	1	1
T43	1	1

Line Coverage for Instance : tb.dut.intr_rx_full

	Line No.	Total	Covered	Percent
TOTAL		10	9	90.00
ALWAYS	75	4	3	75.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	83	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
ALWAYS	95	3	3	100.00



74                          always_ff @(posedge clk_i or negedge rst_ni) begin
75         2/2                if (!rst_ni) test_q <= '0;
           Tests:       T1 T2 T3  | T1 T2 T3 
76         1/2     ==>        else if (reg2hw_intr_test_qe_i) test_q <= reg2hw_intr_test_q_i;
           Tests:       T1 T2 T3 
                        MISSING_ELSE
77                          end
78                      
79                          // TODO: In Status type, INTR_STATE is better to be external type and RO.
80                          assign hw2reg_intr_state_de_o = 1'b 1; // always represent the status
81         1/1              assign hw2reg_intr_state_d_o  = event_intr_i | test_q;
           Tests:       T1 T2 T3 
82                      
83         1/1              assign status = event_intr_i | test_q;
           Tests:       T1 T2 T3 
84                      
85                          // To make the timing same to event type, status signal does not use CSR.q,
86                          // rather the input of the CSR.
87                          logic unused_reg2hw;
88         1/1              assign unused_reg2hw = ^reg2hw_intr_state_q_i;
           Tests:       T1 T2 T3 
89                        end : g_intr_status
90                      
91                      
92                        if (FlopOutput == 1) begin : gen_flop_intr_output
93                          // flop the interrupt output
94                          always_ff @(posedge clk_i or negedge rst_ni) begin
95         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
96         1/1                  intr_o <= '0;
           Tests:       T1 T2 T3 
97                            end else begin
98         1/1                  intr_o <= status & reg2hw_intr_enable_q_i;
           Tests:       T1 T2 T3

Cond Coverage for Instance : tb.dut.intr_rx_full

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (event_intr_i | g_intr_status.test_q)
             ------1-----   ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T20,T59,T60

 LINE       83
 EXPRESSION (event_intr_i | g_intr_status.test_q)
             ------1-----   ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T20,T59,T60

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T20,T61,T62
1	0	Covered	T59,T60,T63
1	1	Covered	T20,T64,T65

Branch Coverage for Instance : tb.dut.intr_rx_full

	Line No.	Total	Covered	Percent
Branches		5	4	80.00
IF	75	3	2	66.67
IF	95	2	2	100.00



75               if (!rst_ni) test_q <= '0;
                 -1-  
                 ==>
76               else if (reg2hw_intr_test_qe_i) test_q <= reg2hw_intr_test_q_i;
                      -2-  
                 ==>
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3



95               if (!rst_ni) begin
                 -1-  
96                 intr_o <= '0;
                   ==>
97               end else begin
98                 intr_o <= status & reg2hw_intr_enable_q_i;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.intr_rx_full

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
IntrTKind_A	3691	3691	0	0

IntrTKind_A

Name	Attempts	Real Successes
Total	3691	3691
T1	1	1
T2	1	1
T3	1	1
T27	1	1
T28	1	1
T29	1	1
T40	1	1
T41	1	1
T42	1	1
T43	1	1

Line Coverage for Instance : tb.dut.intr_av_setup_empty

	Line No.	Total	Covered	Percent
TOTAL		10	9	90.00
ALWAYS	75	4	3	75.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	83	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
ALWAYS	95	3	3	100.00



74                          always_ff @(posedge clk_i or negedge rst_ni) begin
75         2/2                if (!rst_ni) test_q <= '0;
           Tests:       T1 T2 T3  | T1 T2 T3 
76         1/2     ==>        else if (reg2hw_intr_test_qe_i) test_q <= reg2hw_intr_test_q_i;
           Tests:       T1 T2 T3 
                        MISSING_ELSE
77                          end
78                      
79                          // TODO: In Status type, INTR_STATE is better to be external type and RO.
80                          assign hw2reg_intr_state_de_o = 1'b 1; // always represent the status
81         1/1              assign hw2reg_intr_state_d_o  = event_intr_i | test_q;
           Tests:       T1 T2 T3 
82                      
83         1/1              assign status = event_intr_i | test_q;
           Tests:       T1 T2 T3 
84                      
85                          // To make the timing same to event type, status signal does not use CSR.q,
86                          // rather the input of the CSR.
87                          logic unused_reg2hw;
88         1/1              assign unused_reg2hw = ^reg2hw_intr_state_q_i;
           Tests:       T1 T2 T3 
89                        end : g_intr_status
90                      
91                      
92                        if (FlopOutput == 1) begin : gen_flop_intr_output
93                          // flop the interrupt output
94                          always_ff @(posedge clk_i or negedge rst_ni) begin
95         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
96         1/1                  intr_o <= '0;
           Tests:       T1 T2 T3 
97                            end else begin
98         1/1                  intr_o <= status & reg2hw_intr_enable_q_i;
           Tests:       T1 T2 T3

Cond Coverage for Instance : tb.dut.intr_av_setup_empty

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (event_intr_i | g_intr_status.test_q)
             ------1-----   ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       83
 EXPRESSION (event_intr_i | g_intr_status.test_q)
             ------1-----   ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T27,T66,T67
1	0	Covered	T1,T2,T3
1	1	Covered	T27,T66,T67

Branch Coverage for Instance : tb.dut.intr_av_setup_empty

	Line No.	Total	Covered	Percent
Branches		5	4	80.00
IF	75	3	2	66.67
IF	95	2	2	100.00



75               if (!rst_ni) test_q <= '0;
                 -1-  
                 ==>
76               else if (reg2hw_intr_test_qe_i) test_q <= reg2hw_intr_test_q_i;
                      -2-  
                 ==>
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3



95               if (!rst_ni) begin
                 -1-  
96                 intr_o <= '0;
                   ==>
97               end else begin
98                 intr_o <= status & reg2hw_intr_enable_q_i;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.intr_av_setup_empty

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
IntrTKind_A	3691	3691	0	0

IntrTKind_A

Name	Attempts	Real Successes
Total	3691	3691
T1	1	1
T2	1	1
T3	1	1
T27	1	1
T28	1	1
T29	1	1
T40	1	1
T41	1	1
T42	1	1
T43	1	1

Line Coverage for Instance : tb.dut.intr_powered

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	62	1	1	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	67	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
ALWAYS	95	3	3	100.00



61                          logic  [Width-1:0]    new_event;
62         1/1              assign new_event =
           Tests:       T1 T2 T3 
63                                     (({Width{reg2hw_intr_test_qe_i}} & reg2hw_intr_test_q_i) | event_intr_i);
64         1/1              assign hw2reg_intr_state_de_o = |new_event;
           Tests:       T1 T2 T3 
65                          // for scalar interrupts, this resolves to '1' with new event
66                          // for vector interrupts, new events are OR'd in to existing interrupt state
67         1/1              assign hw2reg_intr_state_d_o  =  new_event | reg2hw_intr_state_q_i;
           Tests:       T1 T2 T3 
68                      
69         1/1              assign status = reg2hw_intr_state_q_i ;
           Tests:       T1 T2 T3 
70                        end : g_intr_event
71                        else if (IntrT == "Status") begin : g_intr_status
72                          logic [Width-1:0] test_q; // Storing test. Cleared by SW
73                      
74                          always_ff @(posedge clk_i or negedge rst_ni) begin
75                            if (!rst_ni) test_q <= '0;
76                            else if (reg2hw_intr_test_qe_i) test_q <= reg2hw_intr_test_q_i;
77                          end
78                      
79                          // TODO: In Status type, INTR_STATE is better to be external type and RO.
80                          assign hw2reg_intr_state_de_o = 1'b 1; // always represent the status
81                          assign hw2reg_intr_state_d_o  = event_intr_i | test_q;
82                      
83                          assign status = event_intr_i | test_q;
84                      
85                          // To make the timing same to event type, status signal does not use CSR.q,
86                          // rather the input of the CSR.
87                          logic unused_reg2hw;
88                          assign unused_reg2hw = ^reg2hw_intr_state_q_i;
89                        end : g_intr_status
90                      
91                      
92                        if (FlopOutput == 1) begin : gen_flop_intr_output
93                          // flop the interrupt output
94                          always_ff @(posedge clk_i or negedge rst_ni) begin
95         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
96         1/1                  intr_o <= '0;
           Tests:       T1 T2 T3 
97                            end else begin
98         1/1                  intr_o <= status & reg2hw_intr_enable_q_i;
           Tests:       T1 T2 T3

Cond Coverage for Instance : tb.dut.intr_powered

	Total	Covered	Percent
Conditions	12	7	58.33
Logical	12	7	58.33
Non-Logical	0	0
Event	0	0

 LINE       62
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Not Covered

 LINE       62
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       67
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Not Covered

Branch Coverage for Instance : tb.dut.intr_powered

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	95	2	2	100.00



95               if (!rst_ni) begin
                 -1-  
96                 intr_o <= '0;
                   ==>
97               end else begin
98                 intr_o <= status & reg2hw_intr_enable_q_i;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.intr_powered

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
IntrTKind_A	3691	3691	0	0

IntrTKind_A

Name	Attempts	Real Successes
Total	3691	3691
T1	1	1
T2	1	1
T3	1	1
T27	1	1
T28	1	1
T29	1	1
T40	1	1
T41	1	1
T42	1	1
T43	1	1

Line Coverage for Instance : tb.dut.intr_link_reset

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	62	1	1	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	67	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
ALWAYS	95	3	3	100.00



61                          logic  [Width-1:0]    new_event;
62         1/1              assign new_event =
           Tests:       T1 T2 T3 
63                                     (({Width{reg2hw_intr_test_qe_i}} & reg2hw_intr_test_q_i) | event_intr_i);
64         1/1              assign hw2reg_intr_state_de_o = |new_event;
           Tests:       T1 T2 T3 
65                          // for scalar interrupts, this resolves to '1' with new event
66                          // for vector interrupts, new events are OR'd in to existing interrupt state
67         1/1              assign hw2reg_intr_state_d_o  =  new_event | reg2hw_intr_state_q_i;
           Tests:       T1 T2 T3 
68                      
69         1/1              assign status = reg2hw_intr_state_q_i ;
           Tests:       T1 T2 T3 
70                        end : g_intr_event
71                        else if (IntrT == "Status") begin : g_intr_status
72                          logic [Width-1:0] test_q; // Storing test. Cleared by SW
73                      
74                          always_ff @(posedge clk_i or negedge rst_ni) begin
75                            if (!rst_ni) test_q <= '0;
76                            else if (reg2hw_intr_test_qe_i) test_q <= reg2hw_intr_test_q_i;
77                          end
78                      
79                          // TODO: In Status type, INTR_STATE is better to be external type and RO.
80                          assign hw2reg_intr_state_de_o = 1'b 1; // always represent the status
81                          assign hw2reg_intr_state_d_o  = event_intr_i | test_q;
82                      
83                          assign status = event_intr_i | test_q;
84                      
85                          // To make the timing same to event type, status signal does not use CSR.q,
86                          // rather the input of the CSR.
87                          logic unused_reg2hw;
88                          assign unused_reg2hw = ^reg2hw_intr_state_q_i;
89                        end : g_intr_status
90                      
91                      
92                        if (FlopOutput == 1) begin : gen_flop_intr_output
93                          // flop the interrupt output
94                          always_ff @(posedge clk_i or negedge rst_ni) begin
95         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
96         1/1                  intr_o <= '0;
           Tests:       T1 T2 T3 
97                            end else begin
98         1/1                  intr_o <= status & reg2hw_intr_enable_q_i;
           Tests:       T1 T2 T3

Cond Coverage for Instance : tb.dut.intr_link_reset

	Total	Covered	Percent
Conditions	12	7	58.33
Logical	12	7	58.33
Non-Logical	0	0
Event	0	0

 LINE       62
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Not Covered

 LINE       62
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       67
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Not Covered

Branch Coverage for Instance : tb.dut.intr_link_reset

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	95	2	2	100.00



95               if (!rst_ni) begin
                 -1-  
96                 intr_o <= '0;
                   ==>
97               end else begin
98                 intr_o <= status & reg2hw_intr_enable_q_i;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.intr_link_reset

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
IntrTKind_A	3691	3691	0	0

IntrTKind_A

Name	Attempts	Real Successes
Total	3691	3691
T1	1	1
T2	1	1
T3	1	1
T27	1	1
T28	1	1
T29	1	1
T40	1	1
T41	1	1
T42	1	1
T43	1	1

Line Coverage for Instance : tb.dut.intr_link_suspend

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	62	1	1	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	67	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
ALWAYS	95	3	3	100.00



61                          logic  [Width-1:0]    new_event;
62         1/1              assign new_event =
           Tests:       T1 T2 T3 
63                                     (({Width{reg2hw_intr_test_qe_i}} & reg2hw_intr_test_q_i) | event_intr_i);
64         1/1              assign hw2reg_intr_state_de_o = |new_event;
           Tests:       T1 T2 T3 
65                          // for scalar interrupts, this resolves to '1' with new event
66                          // for vector interrupts, new events are OR'd in to existing interrupt state
67         1/1              assign hw2reg_intr_state_d_o  =  new_event | reg2hw_intr_state_q_i;
           Tests:       T1 T2 T3 
68                      
69         1/1              assign status = reg2hw_intr_state_q_i ;
           Tests:       T1 T2 T3 
70                        end : g_intr_event
71                        else if (IntrT == "Status") begin : g_intr_status
72                          logic [Width-1:0] test_q; // Storing test. Cleared by SW
73                      
74                          always_ff @(posedge clk_i or negedge rst_ni) begin
75                            if (!rst_ni) test_q <= '0;
76                            else if (reg2hw_intr_test_qe_i) test_q <= reg2hw_intr_test_q_i;
77                          end
78                      
79                          // TODO: In Status type, INTR_STATE is better to be external type and RO.
80                          assign hw2reg_intr_state_de_o = 1'b 1; // always represent the status
81                          assign hw2reg_intr_state_d_o  = event_intr_i | test_q;
82                      
83                          assign status = event_intr_i | test_q;
84                      
85                          // To make the timing same to event type, status signal does not use CSR.q,
86                          // rather the input of the CSR.
87                          logic unused_reg2hw;
88                          assign unused_reg2hw = ^reg2hw_intr_state_q_i;
89                        end : g_intr_status
90                      
91                      
92                        if (FlopOutput == 1) begin : gen_flop_intr_output
93                          // flop the interrupt output
94                          always_ff @(posedge clk_i or negedge rst_ni) begin
95         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
96         1/1                  intr_o <= '0;
           Tests:       T1 T2 T3 
97                            end else begin
98         1/1                  intr_o <= status & reg2hw_intr_enable_q_i;
           Tests:       T1 T2 T3

Cond Coverage for Instance : tb.dut.intr_link_suspend

	Total	Covered	Percent
Conditions	12	7	58.33
Logical	12	7	58.33
Non-Logical	0	0
Event	0	0

 LINE       62
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T4
1	0	Not Covered

 LINE       62
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       67
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T4
1	0	Covered	T7,T8,T4

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T8,T4
1	1	Not Covered

Branch Coverage for Instance : tb.dut.intr_link_suspend

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	95	2	2	100.00



95               if (!rst_ni) begin
                 -1-  
96                 intr_o <= '0;
                   ==>
97               end else begin
98                 intr_o <= status & reg2hw_intr_enable_q_i;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.intr_link_suspend

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
IntrTKind_A	3691	3691	0	0

IntrTKind_A

Name	Attempts	Real Successes
Total	3691	3691
T1	1	1
T2	1	1
T3	1	1
T27	1	1
T28	1	1
T29	1	1
T40	1	1
T41	1	1
T42	1	1
T43	1	1

Line Coverage for Instance : tb.dut.intr_link_in_err

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	62	1	1	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	67	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
ALWAYS	95	3	3	100.00



61                          logic  [Width-1:0]    new_event;
62         1/1              assign new_event =
           Tests:       T1 T2 T3 
63                                     (({Width{reg2hw_intr_test_qe_i}} & reg2hw_intr_test_q_i) | event_intr_i);
64         1/1              assign hw2reg_intr_state_de_o = |new_event;
           Tests:       T1 T2 T3 
65                          // for scalar interrupts, this resolves to '1' with new event
66                          // for vector interrupts, new events are OR'd in to existing interrupt state
67         1/1              assign hw2reg_intr_state_d_o  =  new_event | reg2hw_intr_state_q_i;
           Tests:       T1 T2 T3 
68                      
69         1/1              assign status = reg2hw_intr_state_q_i ;
           Tests:       T1 T2 T3 
70                        end : g_intr_event
71                        else if (IntrT == "Status") begin : g_intr_status
72                          logic [Width-1:0] test_q; // Storing test. Cleared by SW
73                      
74                          always_ff @(posedge clk_i or negedge rst_ni) begin
75                            if (!rst_ni) test_q <= '0;
76                            else if (reg2hw_intr_test_qe_i) test_q <= reg2hw_intr_test_q_i;
77                          end
78                      
79                          // TODO: In Status type, INTR_STATE is better to be external type and RO.
80                          assign hw2reg_intr_state_de_o = 1'b 1; // always represent the status
81                          assign hw2reg_intr_state_d_o  = event_intr_i | test_q;
82                      
83                          assign status = event_intr_i | test_q;
84                      
85                          // To make the timing same to event type, status signal does not use CSR.q,
86                          // rather the input of the CSR.
87                          logic unused_reg2hw;
88                          assign unused_reg2hw = ^reg2hw_intr_state_q_i;
89                        end : g_intr_status
90                      
91                      
92                        if (FlopOutput == 1) begin : gen_flop_intr_output
93                          // flop the interrupt output
94                          always_ff @(posedge clk_i or negedge rst_ni) begin
95         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
96         1/1                  intr_o <= '0;
           Tests:       T1 T2 T3 
97                            end else begin
98         1/1                  intr_o <= status & reg2hw_intr_enable_q_i;
           Tests:       T1 T2 T3

Cond Coverage for Instance : tb.dut.intr_link_in_err

	Total	Covered	Percent
Conditions	12	7	58.33
Logical	12	7	58.33
Non-Logical	0	0
Event	0	0

 LINE       62
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T31,T32,T68
1	0	Not Covered

 LINE       62
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       67
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T31,T32,T68
1	0	Covered	T31,T32,T68

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T31,T32,T68
1	1	Not Covered

Branch Coverage for Instance : tb.dut.intr_link_in_err

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	95	2	2	100.00



95               if (!rst_ni) begin
                 -1-  
96                 intr_o <= '0;
                   ==>
97               end else begin
98                 intr_o <= status & reg2hw_intr_enable_q_i;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.intr_link_in_err

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
IntrTKind_A	3691	3691	0	0

IntrTKind_A

Name	Attempts	Real Successes
Total	3691	3691
T1	1	1
T2	1	1
T3	1	1
T27	1	1
T28	1	1
T29	1	1
T40	1	1
T41	1	1
T42	1	1
T43	1	1

Line Coverage for Instance : tb.dut.intr_frame

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	62	1	1	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	67	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
ALWAYS	95	3	3	100.00



61                          logic  [Width-1:0]    new_event;
62         1/1              assign new_event =
           Tests:       T1 T2 T3 
63                                     (({Width{reg2hw_intr_test_qe_i}} & reg2hw_intr_test_q_i) | event_intr_i);
64         1/1              assign hw2reg_intr_state_de_o = |new_event;
           Tests:       T1 T2 T3 
65                          // for scalar interrupts, this resolves to '1' with new event
66                          // for vector interrupts, new events are OR'd in to existing interrupt state
67         1/1              assign hw2reg_intr_state_d_o  =  new_event | reg2hw_intr_state_q_i;
           Tests:       T1 T2 T3 
68                      
69         1/1              assign status = reg2hw_intr_state_q_i ;
           Tests:       T1 T2 T3 
70                        end : g_intr_event
71                        else if (IntrT == "Status") begin : g_intr_status
72                          logic [Width-1:0] test_q; // Storing test. Cleared by SW
73                      
74                          always_ff @(posedge clk_i or negedge rst_ni) begin
75                            if (!rst_ni) test_q <= '0;
76                            else if (reg2hw_intr_test_qe_i) test_q <= reg2hw_intr_test_q_i;
77                          end
78                      
79                          // TODO: In Status type, INTR_STATE is better to be external type and RO.
80                          assign hw2reg_intr_state_de_o = 1'b 1; // always represent the status
81                          assign hw2reg_intr_state_d_o  = event_intr_i | test_q;
82                      
83                          assign status = event_intr_i | test_q;
84                      
85                          // To make the timing same to event type, status signal does not use CSR.q,
86                          // rather the input of the CSR.
87                          logic unused_reg2hw;
88                          assign unused_reg2hw = ^reg2hw_intr_state_q_i;
89                        end : g_intr_status
90                      
91                      
92                        if (FlopOutput == 1) begin : gen_flop_intr_output
93                          // flop the interrupt output
94                          always_ff @(posedge clk_i or negedge rst_ni) begin
95         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
96         1/1                  intr_o <= '0;
           Tests:       T1 T2 T3 
97                            end else begin
98         1/1                  intr_o <= status & reg2hw_intr_enable_q_i;
           Tests:       T1 T2 T3

Cond Coverage for Instance : tb.dut.intr_frame

	Total	Covered	Percent
Conditions	12	7	58.33
Logical	12	7	58.33
Non-Logical	0	0
Event	0	0

 LINE       62
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T41,T7,T21
1	0	Not Covered

 LINE       62
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       67
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T41,T7,T21
1	0	Covered	T41,T7,T21

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T41,T7,T21
1	1	Not Covered

Branch Coverage for Instance : tb.dut.intr_frame

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	95	2	2	100.00



95               if (!rst_ni) begin
                 -1-  
96                 intr_o <= '0;
                   ==>
97               end else begin
98                 intr_o <= status & reg2hw_intr_enable_q_i;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.intr_frame

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
IntrTKind_A	3691	3691	0	0

IntrTKind_A

Name	Attempts	Real Successes
Total	3691	3691
T1	1	1
T2	1	1
T3	1	1
T27	1	1
T28	1	1
T29	1	1
T40	1	1
T41	1	1
T42	1	1
T43	1	1

Line Coverage for Instance : tb.dut.intr_av_overflow

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	62	1	1	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	67	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
ALWAYS	95	3	3	100.00



61                          logic  [Width-1:0]    new_event;
62         1/1              assign new_event =
           Tests:       T1 T2 T3 
63                                     (({Width{reg2hw_intr_test_qe_i}} & reg2hw_intr_test_q_i) | event_intr_i);
64         1/1              assign hw2reg_intr_state_de_o = |new_event;
           Tests:       T1 T38 T39 
65                          // for scalar interrupts, this resolves to '1' with new event
66                          // for vector interrupts, new events are OR'd in to existing interrupt state
67         1/1              assign hw2reg_intr_state_d_o  =  new_event | reg2hw_intr_state_q_i;
           Tests:       T1 T2 T3 
68                      
69         1/1              assign status = reg2hw_intr_state_q_i ;
           Tests:       T1 T2 T3 
70                        end : g_intr_event
71                        else if (IntrT == "Status") begin : g_intr_status
72                          logic [Width-1:0] test_q; // Storing test. Cleared by SW
73                      
74                          always_ff @(posedge clk_i or negedge rst_ni) begin
75                            if (!rst_ni) test_q <= '0;
76                            else if (reg2hw_intr_test_qe_i) test_q <= reg2hw_intr_test_q_i;
77                          end
78                      
79                          // TODO: In Status type, INTR_STATE is better to be external type and RO.
80                          assign hw2reg_intr_state_de_o = 1'b 1; // always represent the status
81                          assign hw2reg_intr_state_d_o  = event_intr_i | test_q;
82                      
83                          assign status = event_intr_i | test_q;
84                      
85                          // To make the timing same to event type, status signal does not use CSR.q,
86                          // rather the input of the CSR.
87                          logic unused_reg2hw;
88                          assign unused_reg2hw = ^reg2hw_intr_state_q_i;
89                        end : g_intr_status
90                      
91                      
92                        if (FlopOutput == 1) begin : gen_flop_intr_output
93                          // flop the interrupt output
94                          always_ff @(posedge clk_i or negedge rst_ni) begin
95         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
96         1/1                  intr_o <= '0;
           Tests:       T1 T2 T3 
97                            end else begin
98         1/1                  intr_o <= status & reg2hw_intr_enable_q_i;
           Tests:       T1 T2 T3

Cond Coverage for Instance : tb.dut.intr_av_overflow

	Total	Covered	Percent
Conditions	12	8	66.67
Logical	12	8	66.67
Non-Logical	0	0
Event	0	0

 LINE       62
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T69,T70
1	0	Not Covered

 LINE       62
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       67
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T69,T70
1	0	Covered	T1,T69,T70

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T69,T70
1	0	Not Covered
1	1	Covered	T1,T69,T70

Branch Coverage for Instance : tb.dut.intr_av_overflow

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	95	2	2	100.00



95               if (!rst_ni) begin
                 -1-  
96                 intr_o <= '0;
                   ==>
97               end else begin
98                 intr_o <= status & reg2hw_intr_enable_q_i;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.intr_av_overflow

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
IntrTKind_A	3691	3691	0	0

IntrTKind_A

Name	Attempts	Real Successes
Total	3691	3691
T1	1	1
T2	1	1
T3	1	1
T27	1	1
T28	1	1
T29	1	1
T40	1	1
T41	1	1
T42	1	1
T43	1	1

Line Coverage for Instance : tb.dut.intr_disconnected

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	62	1	1	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	67	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
ALWAYS	95	3	3	100.00



61                          logic  [Width-1:0]    new_event;
62         1/1              assign new_event =
           Tests:       T1 T2 T3 
63                                     (({Width{reg2hw_intr_test_qe_i}} & reg2hw_intr_test_q_i) | event_intr_i);
64         1/1              assign hw2reg_intr_state_de_o = |new_event;
           Tests:       T1 T2 T3 
65                          // for scalar interrupts, this resolves to '1' with new event
66                          // for vector interrupts, new events are OR'd in to existing interrupt state
67         1/1              assign hw2reg_intr_state_d_o  =  new_event | reg2hw_intr_state_q_i;
           Tests:       T1 T2 T3 
68                      
69         1/1              assign status = reg2hw_intr_state_q_i ;
           Tests:       T1 T2 T3 
70                        end : g_intr_event
71                        else if (IntrT == "Status") begin : g_intr_status
72                          logic [Width-1:0] test_q; // Storing test. Cleared by SW
73                      
74                          always_ff @(posedge clk_i or negedge rst_ni) begin
75                            if (!rst_ni) test_q <= '0;
76                            else if (reg2hw_intr_test_qe_i) test_q <= reg2hw_intr_test_q_i;
77                          end
78                      
79                          // TODO: In Status type, INTR_STATE is better to be external type and RO.
80                          assign hw2reg_intr_state_de_o = 1'b 1; // always represent the status
81                          assign hw2reg_intr_state_d_o  = event_intr_i | test_q;
82                      
83                          assign status = event_intr_i | test_q;
84                      
85                          // To make the timing same to event type, status signal does not use CSR.q,
86                          // rather the input of the CSR.
87                          logic unused_reg2hw;
88                          assign unused_reg2hw = ^reg2hw_intr_state_q_i;
89                        end : g_intr_status
90                      
91                      
92                        if (FlopOutput == 1) begin : gen_flop_intr_output
93                          // flop the interrupt output
94                          always_ff @(posedge clk_i or negedge rst_ni) begin
95         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
96         1/1                  intr_o <= '0;
           Tests:       T1 T2 T3 
97                            end else begin
98         1/1                  intr_o <= status & reg2hw_intr_enable_q_i;
           Tests:       T1 T2 T3

Cond Coverage for Instance : tb.dut.intr_disconnected

	Total	Covered	Percent
Conditions	12	9	75.00
Logical	12	9	75.00
Non-Logical	0	0
Event	0	0

 LINE       62
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Not Covered

 LINE       62
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       67
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T41,T56,T71
1	0	Covered	T1,T2,T3
1	1	Covered	T41,T56,T71

Branch Coverage for Instance : tb.dut.intr_disconnected

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	95	2	2	100.00



95               if (!rst_ni) begin
                 -1-  
96                 intr_o <= '0;
                   ==>
97               end else begin
98                 intr_o <= status & reg2hw_intr_enable_q_i;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.intr_disconnected

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
IntrTKind_A	3691	3691	0	0

IntrTKind_A

Name	Attempts	Real Successes
Total	3691	3691
T1	1	1
T2	1	1
T3	1	1
T27	1	1
T28	1	1
T29	1	1
T40	1	1
T41	1	1
T42	1	1
T43	1	1

Line Coverage for Instance : tb.dut.intr_host_lost

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	62	1	1	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	67	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
ALWAYS	95	3	3	100.00



61                          logic  [Width-1:0]    new_event;
62         1/1              assign new_event =
           Tests:       T1 T2 T3 
63                                     (({Width{reg2hw_intr_test_qe_i}} & reg2hw_intr_test_q_i) | event_intr_i);
64         1/1              assign hw2reg_intr_state_de_o = |new_event;
           Tests:       T1 T2 T3 
65                          // for scalar interrupts, this resolves to '1' with new event
66                          // for vector interrupts, new events are OR'd in to existing interrupt state
67         1/1              assign hw2reg_intr_state_d_o  =  new_event | reg2hw_intr_state_q_i;
           Tests:       T1 T2 T3 
68                      
69         1/1              assign status = reg2hw_intr_state_q_i ;
           Tests:       T1 T2 T3 
70                        end : g_intr_event
71                        else if (IntrT == "Status") begin : g_intr_status
72                          logic [Width-1:0] test_q; // Storing test. Cleared by SW
73                      
74                          always_ff @(posedge clk_i or negedge rst_ni) begin
75                            if (!rst_ni) test_q <= '0;
76                            else if (reg2hw_intr_test_qe_i) test_q <= reg2hw_intr_test_q_i;
77                          end
78                      
79                          // TODO: In Status type, INTR_STATE is better to be external type and RO.
80                          assign hw2reg_intr_state_de_o = 1'b 1; // always represent the status
81                          assign hw2reg_intr_state_d_o  = event_intr_i | test_q;
82                      
83                          assign status = event_intr_i | test_q;
84                      
85                          // To make the timing same to event type, status signal does not use CSR.q,
86                          // rather the input of the CSR.
87                          logic unused_reg2hw;
88                          assign unused_reg2hw = ^reg2hw_intr_state_q_i;
89                        end : g_intr_status
90                      
91                      
92                        if (FlopOutput == 1) begin : gen_flop_intr_output
93                          // flop the interrupt output
94                          always_ff @(posedge clk_i or negedge rst_ni) begin
95         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
96         1/1                  intr_o <= '0;
           Tests:       T1 T2 T3 
97                            end else begin
98         1/1                  intr_o <= status & reg2hw_intr_enable_q_i;
           Tests:       T1 T2 T3

Cond Coverage for Instance : tb.dut.intr_host_lost

	Total	Covered	Percent
Conditions	12	9	75.00
Logical	12	9	75.00
Non-Logical	0	0
Event	0	0

 LINE       62
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T21,T4,T6
1	0	Not Covered

 LINE       62
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       67
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T21,T4,T6
1	0	Covered	T21,T4,T6

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T21
1	0	Covered	T21,T4,T6
1	1	Covered	T21

Branch Coverage for Instance : tb.dut.intr_host_lost

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	95	2	2	100.00



95               if (!rst_ni) begin
                 -1-  
96                 intr_o <= '0;
                   ==>
97               end else begin
98                 intr_o <= status & reg2hw_intr_enable_q_i;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.intr_host_lost

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
IntrTKind_A	3691	3691	0	0

IntrTKind_A

Name	Attempts	Real Successes
Total	3691	3691
T1	1	1
T2	1	1
T3	1	1
T27	1	1
T28	1	1
T29	1	1
T40	1	1
T41	1	1
T42	1	1
T43	1	1

Line Coverage for Instance : tb.dut.intr_link_resume

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	62	1	1	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	67	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
ALWAYS	95	3	3	100.00



61                          logic  [Width-1:0]    new_event;
62         1/1              assign new_event =
           Tests:       T1 T2 T3 
63                                     (({Width{reg2hw_intr_test_qe_i}} & reg2hw_intr_test_q_i) | event_intr_i);
64         1/1              assign hw2reg_intr_state_de_o = |new_event;
           Tests:       T1 T2 T3 
65                          // for scalar interrupts, this resolves to '1' with new event
66                          // for vector interrupts, new events are OR'd in to existing interrupt state
67         1/1              assign hw2reg_intr_state_d_o  =  new_event | reg2hw_intr_state_q_i;
           Tests:       T1 T2 T3 
68                      
69         1/1              assign status = reg2hw_intr_state_q_i ;
           Tests:       T1 T2 T3 
70                        end : g_intr_event
71                        else if (IntrT == "Status") begin : g_intr_status
72                          logic [Width-1:0] test_q; // Storing test. Cleared by SW
73                      
74                          always_ff @(posedge clk_i or negedge rst_ni) begin
75                            if (!rst_ni) test_q <= '0;
76                            else if (reg2hw_intr_test_qe_i) test_q <= reg2hw_intr_test_q_i;
77                          end
78                      
79                          // TODO: In Status type, INTR_STATE is better to be external type and RO.
80                          assign hw2reg_intr_state_de_o = 1'b 1; // always represent the status
81                          assign hw2reg_intr_state_d_o  = event_intr_i | test_q;
82                      
83                          assign status = event_intr_i | test_q;
84                      
85                          // To make the timing same to event type, status signal does not use CSR.q,
86                          // rather the input of the CSR.
87                          logic unused_reg2hw;
88                          assign unused_reg2hw = ^reg2hw_intr_state_q_i;
89                        end : g_intr_status
90                      
91                      
92                        if (FlopOutput == 1) begin : gen_flop_intr_output
93                          // flop the interrupt output
94                          always_ff @(posedge clk_i or negedge rst_ni) begin
95         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
96         1/1                  intr_o <= '0;
           Tests:       T1 T2 T3 
97                            end else begin
98         1/1                  intr_o <= status & reg2hw_intr_enable_q_i;
           Tests:       T1 T2 T3

Cond Coverage for Instance : tb.dut.intr_link_resume

	Total	Covered	Percent
Conditions	12	9	75.00
Logical	12	9	75.00
Non-Logical	0	0
Event	0	0

 LINE       62
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T4,T72
1	0	Not Covered

 LINE       62
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       67
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T4,T72
1	0	Covered	T8,T4,T72

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T73,T74,T75
1	0	Covered	T8,T4,T72
1	1	Covered	T73,T74,T75

Branch Coverage for Instance : tb.dut.intr_link_resume

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	95	2	2	100.00



95               if (!rst_ni) begin
                 -1-  
96                 intr_o <= '0;
                   ==>
97               end else begin
98                 intr_o <= status & reg2hw_intr_enable_q_i;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.intr_link_resume

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
IntrTKind_A	3691	3691	0	0

IntrTKind_A

Name	Attempts	Real Successes
Total	3691	3691
T1	1	1
T2	1	1
T3	1	1
T27	1	1
T28	1	1
T29	1	1
T40	1	1
T41	1	1
T42	1	1
T43	1	1

Line Coverage for Instance : tb.dut.intr_link_out_err

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	62	1	1	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	67	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
ALWAYS	95	3	3	100.00



61                          logic  [Width-1:0]    new_event;
62         1/1              assign new_event =
           Tests:       T1 T2 T3 
63                                     (({Width{reg2hw_intr_test_qe_i}} & reg2hw_intr_test_q_i) | event_intr_i);
64         1/1              assign hw2reg_intr_state_de_o = |new_event;
           Tests:       T1 T2 T3 
65                          // for scalar interrupts, this resolves to '1' with new event
66                          // for vector interrupts, new events are OR'd in to existing interrupt state
67         1/1              assign hw2reg_intr_state_d_o  =  new_event | reg2hw_intr_state_q_i;
           Tests:       T1 T2 T3 
68                      
69         1/1              assign status = reg2hw_intr_state_q_i ;
           Tests:       T1 T2 T3 
70                        end : g_intr_event
71                        else if (IntrT == "Status") begin : g_intr_status
72                          logic [Width-1:0] test_q; // Storing test. Cleared by SW
73                      
74                          always_ff @(posedge clk_i or negedge rst_ni) begin
75                            if (!rst_ni) test_q <= '0;
76                            else if (reg2hw_intr_test_qe_i) test_q <= reg2hw_intr_test_q_i;
77                          end
78                      
79                          // TODO: In Status type, INTR_STATE is better to be external type and RO.
80                          assign hw2reg_intr_state_de_o = 1'b 1; // always represent the status
81                          assign hw2reg_intr_state_d_o  = event_intr_i | test_q;
82                      
83                          assign status = event_intr_i | test_q;
84                      
85                          // To make the timing same to event type, status signal does not use CSR.q,
86                          // rather the input of the CSR.
87                          logic unused_reg2hw;
88                          assign unused_reg2hw = ^reg2hw_intr_state_q_i;
89                        end : g_intr_status
90                      
91                      
92                        if (FlopOutput == 1) begin : gen_flop_intr_output
93                          // flop the interrupt output
94                          always_ff @(posedge clk_i or negedge rst_ni) begin
95         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
96         1/1                  intr_o <= '0;
           Tests:       T1 T2 T3 
97                            end else begin
98         1/1                  intr_o <= status & reg2hw_intr_enable_q_i;
           Tests:       T1 T2 T3

Cond Coverage for Instance : tb.dut.intr_link_out_err

	Total	Covered	Percent
Conditions	12	9	75.00
Logical	12	9	75.00
Non-Logical	0	0
Event	0	0

 LINE       62
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T31,T38,T17
1	0	Not Covered

 LINE       62
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T27
1	0	Not Covered
1	1	Not Covered

 LINE       67
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T31,T38,T17
1	0	Covered	T31,T38,T17

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T22,T76
1	0	Covered	T31,T38,T17
1	1	Covered	T22,T76

Branch Coverage for Instance : tb.dut.intr_link_out_err

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	95	2	2	100.00



95               if (!rst_ni) begin
                 -1-  
96                 intr_o <= '0;
                   ==>
97               end else begin
98                 intr_o <= status & reg2hw_intr_enable_q_i;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.intr_link_out_err

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
IntrTKind_A	3691	3691	0	0

IntrTKind_A

Name	Attempts	Real Successes
Total	3691	3691
T1	1	1
T2	1	1
T3	1	1
T27	1	1
T28	1	1
T29	1	1
T40	1	1
T41	1	1
T42	1	1
T43	1	1

Line Coverage for Instance : tb.dut.intr_rx_crc_err

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	62	1	1	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	67	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
ALWAYS	95	3	3	100.00



61                          logic  [Width-1:0]    new_event;
62         1/1              assign new_event =
           Tests:       T1 T2 T3 
63                                     (({Width{reg2hw_intr_test_qe_i}} & reg2hw_intr_test_q_i) | event_intr_i);
64         1/1              assign hw2reg_intr_state_de_o = |new_event;
           Tests:       T1 T2 T3 
65                          // for scalar interrupts, this resolves to '1' with new event
66                          // for vector interrupts, new events are OR'd in to existing interrupt state
67         1/1              assign hw2reg_intr_state_d_o  =  new_event | reg2hw_intr_state_q_i;
           Tests:       T1 T2 T3 
68                      
69         1/1              assign status = reg2hw_intr_state_q_i ;
           Tests:       T1 T2 T3 
70                        end : g_intr_event
71                        else if (IntrT == "Status") begin : g_intr_status
72                          logic [Width-1:0] test_q; // Storing test. Cleared by SW
73                      
74                          always_ff @(posedge clk_i or negedge rst_ni) begin
75                            if (!rst_ni) test_q <= '0;
76                            else if (reg2hw_intr_test_qe_i) test_q <= reg2hw_intr_test_q_i;
77                          end
78                      
79                          // TODO: In Status type, INTR_STATE is better to be external type and RO.
80                          assign hw2reg_intr_state_de_o = 1'b 1; // always represent the status
81                          assign hw2reg_intr_state_d_o  = event_intr_i | test_q;
82                      
83                          assign status = event_intr_i | test_q;
84                      
85                          // To make the timing same to event type, status signal does not use CSR.q,
86                          // rather the input of the CSR.
87                          logic unused_reg2hw;
88                          assign unused_reg2hw = ^reg2hw_intr_state_q_i;
89                        end : g_intr_status
90                      
91                      
92                        if (FlopOutput == 1) begin : gen_flop_intr_output
93                          // flop the interrupt output
94                          always_ff @(posedge clk_i or negedge rst_ni) begin
95         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
96         1/1                  intr_o <= '0;
           Tests:       T1 T2 T3 
97                            end else begin
98         1/1                  intr_o <= status & reg2hw_intr_enable_q_i;
           Tests:       T1 T2 T3

Cond Coverage for Instance : tb.dut.intr_rx_crc_err

	Total	Covered	Percent
Conditions	12	9	75.00
Logical	12	9	75.00
Non-Logical	0	0
Event	0	0

 LINE       62
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T17,T22
1	0	Not Covered

 LINE       62
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       67
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T17,T22
1	0	Covered	T3,T17,T22

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T17,T77,T78
1	0	Covered	T3,T22,T57
1	1	Covered	T17,T77,T78

Branch Coverage for Instance : tb.dut.intr_rx_crc_err

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	95	2	2	100.00



95               if (!rst_ni) begin
                 -1-  
96                 intr_o <= '0;
                   ==>
97               end else begin
98                 intr_o <= status & reg2hw_intr_enable_q_i;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.intr_rx_crc_err

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
IntrTKind_A	3691	3691	0	0

IntrTKind_A

Name	Attempts	Real Successes
Total	3691	3691
T1	1	1
T2	1	1
T3	1	1
T27	1	1
T28	1	1
T29	1	1
T40	1	1
T41	1	1
T42	1	1
T43	1	1

Line Coverage for Instance : tb.dut.intr_rx_pid_err

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	62	1	1	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	67	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
ALWAYS	95	3	3	100.00



61                          logic  [Width-1:0]    new_event;
62         1/1              assign new_event =
           Tests:       T1 T2 T3 
63                                     (({Width{reg2hw_intr_test_qe_i}} & reg2hw_intr_test_q_i) | event_intr_i);
64         1/1              assign hw2reg_intr_state_de_o = |new_event;
           Tests:       T1 T2 T3 
65                          // for scalar interrupts, this resolves to '1' with new event
66                          // for vector interrupts, new events are OR'd in to existing interrupt state
67         1/1              assign hw2reg_intr_state_d_o  =  new_event | reg2hw_intr_state_q_i;
           Tests:       T1 T2 T3 
68                      
69         1/1              assign status = reg2hw_intr_state_q_i ;
           Tests:       T1 T2 T3 
70                        end : g_intr_event
71                        else if (IntrT == "Status") begin : g_intr_status
72                          logic [Width-1:0] test_q; // Storing test. Cleared by SW
73                      
74                          always_ff @(posedge clk_i or negedge rst_ni) begin
75                            if (!rst_ni) test_q <= '0;
76                            else if (reg2hw_intr_test_qe_i) test_q <= reg2hw_intr_test_q_i;
77                          end
78                      
79                          // TODO: In Status type, INTR_STATE is better to be external type and RO.
80                          assign hw2reg_intr_state_de_o = 1'b 1; // always represent the status
81                          assign hw2reg_intr_state_d_o  = event_intr_i | test_q;
82                      
83                          assign status = event_intr_i | test_q;
84                      
85                          // To make the timing same to event type, status signal does not use CSR.q,
86                          // rather the input of the CSR.
87                          logic unused_reg2hw;
88                          assign unused_reg2hw = ^reg2hw_intr_state_q_i;
89                        end : g_intr_status
90                      
91                      
92                        if (FlopOutput == 1) begin : gen_flop_intr_output
93                          // flop the interrupt output
94                          always_ff @(posedge clk_i or negedge rst_ni) begin
95         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
96         1/1                  intr_o <= '0;
           Tests:       T1 T2 T3 
97                            end else begin
98         1/1                  intr_o <= status & reg2hw_intr_enable_q_i;
           Tests:       T1 T2 T3

Cond Coverage for Instance : tb.dut.intr_rx_pid_err

	Total	Covered	Percent
Conditions	12	9	75.00
Logical	12	9	75.00
Non-Logical	0	0
Event	0	0

 LINE       62
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T79,T80,T81
1	0	Not Covered

 LINE       62
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       67
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T79,T80,T81
1	0	Covered	T79,T80,T81

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T79,T80,T81
1	0	Covered	T82,T83,T84
1	1	Covered	T79,T80,T81

Branch Coverage for Instance : tb.dut.intr_rx_pid_err

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	95	2	2	100.00



95               if (!rst_ni) begin
                 -1-  
96                 intr_o <= '0;
                   ==>
97               end else begin
98                 intr_o <= status & reg2hw_intr_enable_q_i;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.intr_rx_pid_err

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
IntrTKind_A	3691	3691	0	0

IntrTKind_A

Name	Attempts	Real Successes
Total	3691	3691
T1	1	1
T2	1	1
T3	1	1
T27	1	1
T28	1	1
T29	1	1
T40	1	1
T41	1	1
T42	1	1
T43	1	1

Line Coverage for Instance : tb.dut.intr_rx_bitstuff_err

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	62	1	1	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	67	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
ALWAYS	95	3	3	100.00



61                          logic  [Width-1:0]    new_event;
62         1/1              assign new_event =
           Tests:       T1 T2 T3 
63                                     (({Width{reg2hw_intr_test_qe_i}} & reg2hw_intr_test_q_i) | event_intr_i);
64         1/1              assign hw2reg_intr_state_de_o = |new_event;
           Tests:       T1 T2 T3 
65                          // for scalar interrupts, this resolves to '1' with new event
66                          // for vector interrupts, new events are OR'd in to existing interrupt state
67         1/1              assign hw2reg_intr_state_d_o  =  new_event | reg2hw_intr_state_q_i;
           Tests:       T1 T2 T3 
68                      
69         1/1              assign status = reg2hw_intr_state_q_i ;
           Tests:       T1 T2 T3 
70                        end : g_intr_event
71                        else if (IntrT == "Status") begin : g_intr_status
72                          logic [Width-1:0] test_q; // Storing test. Cleared by SW
73                      
74                          always_ff @(posedge clk_i or negedge rst_ni) begin
75                            if (!rst_ni) test_q <= '0;
76                            else if (reg2hw_intr_test_qe_i) test_q <= reg2hw_intr_test_q_i;
77                          end
78                      
79                          // TODO: In Status type, INTR_STATE is better to be external type and RO.
80                          assign hw2reg_intr_state_de_o = 1'b 1; // always represent the status
81                          assign hw2reg_intr_state_d_o  = event_intr_i | test_q;
82                      
83                          assign status = event_intr_i | test_q;
84                      
85                          // To make the timing same to event type, status signal does not use CSR.q,
86                          // rather the input of the CSR.
87                          logic unused_reg2hw;
88                          assign unused_reg2hw = ^reg2hw_intr_state_q_i;
89                        end : g_intr_status
90                      
91                      
92                        if (FlopOutput == 1) begin : gen_flop_intr_output
93                          // flop the interrupt output
94                          always_ff @(posedge clk_i or negedge rst_ni) begin
95         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
96         1/1                  intr_o <= '0;
           Tests:       T1 T2 T3 
97                            end else begin
98         1/1                  intr_o <= status & reg2hw_intr_enable_q_i;
           Tests:       T1 T2 T3

Cond Coverage for Instance : tb.dut.intr_rx_bitstuff_err

	Total	Covered	Percent
Conditions	12	9	75.00
Logical	12	9	75.00
Non-Logical	0	0
Event	0	0

 LINE       62
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T85,T86
1	0	Not Covered

 LINE       62
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       67
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T85,T86
1	0	Covered	T3,T85,T86

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T85,T86
1	0	Covered	T82,T83,T84
1	1	Covered	T3,T85,T86

Branch Coverage for Instance : tb.dut.intr_rx_bitstuff_err

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	95	2	2	100.00



95               if (!rst_ni) begin
                 -1-  
96                 intr_o <= '0;
                   ==>
97               end else begin
98                 intr_o <= status & reg2hw_intr_enable_q_i;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.intr_rx_bitstuff_err

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
IntrTKind_A	3691	3691	0	0

IntrTKind_A

Name	Attempts	Real Successes
Total	3691	3691
T1	1	1
T2	1	1
T3	1	1
T27	1	1
T28	1	1
T29	1	1
T40	1	1
T41	1	1
T42	1	1
T43	1	1

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.99	97.53	92.86	94.55		100.00	100.00	dut

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.99	97.53	92.86	94.55		100.00	100.00	dut

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.99	97.53	92.86	94.55		100.00	100.00	dut