Unified Coverage Report :: Module Instance :: tb.dut.usbdev

Line Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00



68                          always_ff @(posedge clk_i or negedge rst_ni) begin
69         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
70         1/1                  under_rst <= 1'b1;
           Tests:       T1 T2 T3 
71         1/1                end else if (under_rst) begin
           Tests:       T1 T2 T3 
72         1/1                  under_rst <= ~under_rst;
           Tests:       T1 T2 T3 
73                            end
                        MISSING_ELSE
74                          end
75                      
76                          logic empty;
77                      
78                          // full and not ready for write are two different concepts.
79                          // The latter can be '0' when under reset, while the former is an indication that no more
80                          // entries can be written.
81         1/1              assign wready_o = ~full_o & ~under_rst;
           Tests:       T1 T2 T3 
82         1/1              assign rvalid_o = ~empty & ~under_rst;
           Tests:       T1 T2 T3 
83                      
84                          prim_fifo_sync_cnt #(
85                            .Depth(Depth),
86                            .Secure(Secure)
87                          ) u_fifo_cnt (
88                            .clk_i,
89                            .rst_ni,
90                            .clr_i,
91                            .incr_wptr_i(fifo_incr_wptr),
92                            .incr_rptr_i(fifo_incr_rptr),
93                            .wptr_o(fifo_wptr),
94                            .rptr_o(fifo_rptr),
95                            .full_o,
96                            .empty_o(fifo_empty),
97                            .depth_o,
98                            .err_o
99                          );
100        1/1              assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
           Tests:       T1 T2 T3 
101        1/1              assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
           Tests:       T1 T2 T3 
102                     
103                         // the generate blocks below are needed to avoid lint errors due to array indexing
104                         // in the where the fifo only has one storage element
105                         logic [Depth-1:0][Width-1:0] storage;
106                         logic [Width-1:0] storage_rdata;
107                         if (Depth == 1) begin : gen_depth_eq1
108                           assign storage_rdata = storage[0];
109                     
110                           always_ff @(posedge clk_i)
111                             if (fifo_incr_wptr) begin
112                               storage[0] <= wdata_i;
113                             end
114                     
115                           logic unused_ptrs;
116                           assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
117                     
118                         // fifo with more than one storage element
119                         end else begin : gen_depth_gt1
120        1/1                assign storage_rdata = storage[fifo_rptr];
           Tests:       T1 T2 T3 
121                     
122                           always_ff @(posedge clk_i)
123        1/1                  if (fifo_incr_wptr) begin
           Tests:       T1 T2 T3 
124        1/1                    storage[fifo_wptr] <= wdata_i;
           Tests:       T1 T2 T27 
125                             end
                        MISSING_ELSE
126                         end
127                     
128                         logic [Width-1:0] rdata_int;
129                         if (Pass == 1'b1) begin : gen_pass
130                           assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
131                           assign empty = fifo_empty & ~wvalid_i;
132                         end else begin : gen_nopass
133        1/1                assign rdata_int = storage_rdata;
           Tests:       T1 T2 T27 
134        1/1                assign empty = fifo_empty;
           Tests:       T1 T2 T3 
135                         end
136                     
137                         if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138                           assign rdata_o = empty ? Width'(0) : rdata_int;
139                         end else begin : gen_no_output_zero
140        1/1                assign rdata_o = rdata_int;
           Tests:       T1 T2 T27

Cond Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T20,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T27

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T89
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T2,T27

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Excluded		DUT shall not read from empty FIFO
1	0	1	Covered	T1,T2,T27
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T2,T27,T38

Branch Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00



69               if (!rst_ni) begin
                 -1-  
70                 under_rst <= 1'b1;
                   ==>
71               end else if (under_rst) begin
                          -2-  
72                 under_rst <= ~under_rst;
                   ==>
73               end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3



123                if (fifo_incr_wptr) begin
                   -1-     
124                  storage[fifo_wptr] <= wdata_i;
                     ==>
125                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T27
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	578611326	135432543	0	0
DataKnown_AKnownEnable	578611326	578320424	0	0
DepthKnown_A	578611326	578320424	0	0
RvalidKnown_A	578611326	578320424	0	0
WreadyKnown_A	578611326	578320424	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	578611326	135432543	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	578611326	135432543
T1	6612	931
T2	7617	554
T3	6918	0
T4	0	271054
T20	0	6619
T27	9068	1685
T28	8119	0
T29	23729	0
T38	0	3918
T39	0	5866
T40	4128	0
T41	6638	0
T42	23439	10721
T43	28526	19612
T57	0	1682

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	578611326	578320424
T1	6612	6551
T2	7617	7517
T3	6918	6849
T27	9068	8987
T28	8119	8036
T29	23729	23634
T40	4128	4054
T41	6638	6580
T42	23439	23369
T43	28526	28432

DepthKnown_A

Name	Attempts	Real Successes
Total	578611326	578320424
T1	6612	6551
T2	7617	7517
T3	6918	6849
T27	9068	8987
T28	8119	8036
T29	23729	23634
T40	4128	4054
T41	6638	6580
T42	23439	23369
T43	28526	28432

RvalidKnown_A

Name	Attempts	Real Successes
Total	578611326	578320424
T1	6612	6551
T2	7617	7517
T3	6918	6849
T27	9068	8987
T28	8119	8036
T29	23729	23634
T40	4128	4054
T41	6638	6580
T42	23439	23369
T43	28526	28432

WreadyKnown_A

Name	Attempts	Real Successes
Total	578611326	578320424
T1	6612	6551
T2	7617	7517
T3	6918	6849
T27	9068	8987
T28	8119	8036
T29	23729	23634
T40	4128	4054
T41	6638	6580
T42	23439	23369
T43	28526	28432

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes
Total	578611326	135432543
T1	6612	931
T2	7617	554
T3	6918	0
T4	0	271054
T20	0	6619
T27	9068	1685
T28	8119	0
T29	23729	0
T38	0	3918
T39	0	5866
T40	4128	0
T41	6638	0
T42	23439	10721
T43	28526	19612
T57	0	1682

Line Coverage for Instance : tb.dut.usbdev_avoutfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00



68                          always_ff @(posedge clk_i or negedge rst_ni) begin
69         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
70         1/1                  under_rst <= 1'b1;
           Tests:       T1 T2 T3 
71         1/1                end else if (under_rst) begin
           Tests:       T1 T2 T3 
72         1/1                  under_rst <= ~under_rst;
           Tests:       T1 T2 T3 
73                            end
                        MISSING_ELSE
74                          end
75                      
76                          logic empty;
77                      
78                          // full and not ready for write are two different concepts.
79                          // The latter can be '0' when under reset, while the former is an indication that no more
80                          // entries can be written.
81         1/1              assign wready_o = ~full_o & ~under_rst;
           Tests:       T1 T2 T3 
82         1/1              assign rvalid_o = ~empty & ~under_rst;
           Tests:       T1 T2 T3 
83                      
84                          prim_fifo_sync_cnt #(
85                            .Depth(Depth),
86                            .Secure(Secure)
87                          ) u_fifo_cnt (
88                            .clk_i,
89                            .rst_ni,
90                            .clr_i,
91                            .incr_wptr_i(fifo_incr_wptr),
92                            .incr_rptr_i(fifo_incr_rptr),
93                            .wptr_o(fifo_wptr),
94                            .rptr_o(fifo_rptr),
95                            .full_o,
96                            .empty_o(fifo_empty),
97                            .depth_o,
98                            .err_o
99                          );
100        1/1              assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
           Tests:       T1 T2 T3 
101        1/1              assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
           Tests:       T1 T2 T3 
102                     
103                         // the generate blocks below are needed to avoid lint errors due to array indexing
104                         // in the where the fifo only has one storage element
105                         logic [Depth-1:0][Width-1:0] storage;
106                         logic [Width-1:0] storage_rdata;
107                         if (Depth == 1) begin : gen_depth_eq1
108                           assign storage_rdata = storage[0];
109                     
110                           always_ff @(posedge clk_i)
111                             if (fifo_incr_wptr) begin
112                               storage[0] <= wdata_i;
113                             end
114                     
115                           logic unused_ptrs;
116                           assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
117                     
118                         // fifo with more than one storage element
119                         end else begin : gen_depth_gt1
120        1/1                assign storage_rdata = storage[fifo_rptr];
           Tests:       T1 T2 T3 
121                     
122                           always_ff @(posedge clk_i)
123        1/1                  if (fifo_incr_wptr) begin
           Tests:       T1 T2 T3 
124        1/1                    storage[fifo_wptr] <= wdata_i;
           Tests:       T3 T41 T42 
125                             end
                        MISSING_ELSE
126                         end
127                     
128                         logic [Width-1:0] rdata_int;
129                         if (Pass == 1'b1) begin : gen_pass
130                           assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
131                           assign empty = fifo_empty & ~wvalid_i;
132                         end else begin : gen_nopass
133        1/1                assign rdata_int = storage_rdata;
           Tests:       T3 T41 T42 
134        1/1                assign empty = fifo_empty;
           Tests:       T1 T2 T3 
135                         end
136                     
137                         if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138                           assign rdata_o = empty ? Width'(0) : rdata_int;
139                         end else begin : gen_no_output_zero
140        1/1                assign rdata_o = rdata_int;
           Tests:       T3 T41 T42

Cond Coverage for Instance : tb.dut.usbdev_avoutfifo

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T38,T39,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T3,T41,T42

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T69,T70,T90
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T3,T41,T42

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Excluded		DUT shall not read from empty FIFO
1	0	1	Covered	T3,T41,T42
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T29,T30,T31

Branch Coverage for Instance : tb.dut.usbdev_avoutfifo

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00



69               if (!rst_ni) begin
                 -1-  
70                 under_rst <= 1'b1;
                   ==>
71               end else if (under_rst) begin
                          -2-  
72                 under_rst <= ~under_rst;
                   ==>
73               end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3



123                if (fifo_incr_wptr) begin
                   -1-     
124                  storage[fifo_wptr] <= wdata_i;
                     ==>
125                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T3,T41,T42
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.usbdev_avoutfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	578611326	278982691	0	0
DataKnown_AKnownEnable	578611326	578320424	0	0
DepthKnown_A	578611326	578320424	0	0
RvalidKnown_A	578611326	578320424	0	0
WreadyKnown_A	578611326	578320424	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	578611326	278982691	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	578611326	278982691
T3	6918	1240
T27	9068	0
T28	8119	0
T29	23729	10098
T30	41711	15241
T31	57856	27457
T33	0	1559
T34	0	961
T35	0	648
T40	4128	0
T41	6638	1020
T42	23439	15827
T43	28526	20825

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	578611326	578320424
T1	6612	6551
T2	7617	7517
T3	6918	6849
T27	9068	8987
T28	8119	8036
T29	23729	23634
T40	4128	4054
T41	6638	6580
T42	23439	23369
T43	28526	28432

DepthKnown_A

Name	Attempts	Real Successes
Total	578611326	578320424
T1	6612	6551
T2	7617	7517
T3	6918	6849
T27	9068	8987
T28	8119	8036
T29	23729	23634
T40	4128	4054
T41	6638	6580
T42	23439	23369
T43	28526	28432

RvalidKnown_A

Name	Attempts	Real Successes
Total	578611326	578320424
T1	6612	6551
T2	7617	7517
T3	6918	6849
T27	9068	8987
T28	8119	8036
T29	23729	23634
T40	4128	4054
T41	6638	6580
T42	23439	23369
T43	28526	28432

WreadyKnown_A

Name	Attempts	Real Successes
Total	578611326	578320424
T1	6612	6551
T2	7617	7517
T3	6918	6849
T27	9068	8987
T28	8119	8036
T29	23729	23634
T40	4128	4054
T41	6638	6580
T42	23439	23369
T43	28526	28432

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes
Total	578611326	278982691
T3	6918	1240
T27	9068	0
T28	8119	0
T29	23729	10098
T30	41711	15241
T31	57856	27457
T33	0	1559
T34	0	961
T35	0	648
T40	4128	0
T41	6638	1020
T42	23439	15827
T43	28526	20825

Line Coverage for Instance : tb.dut.usbdev_rxfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00



68                          always_ff @(posedge clk_i or negedge rst_ni) begin
69         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
70         1/1                  under_rst <= 1'b1;
           Tests:       T1 T2 T3 
71         1/1                end else if (under_rst) begin
           Tests:       T1 T2 T3 
72         1/1                  under_rst <= ~under_rst;
           Tests:       T1 T2 T3 
73                            end
                        MISSING_ELSE
74                          end
75                      
76                          logic empty;
77                      
78                          // full and not ready for write are two different concepts.
79                          // The latter can be '0' when under reset, while the former is an indication that no more
80                          // entries can be written.
81         1/1              assign wready_o = ~full_o & ~under_rst;
           Tests:       T1 T2 T3 
82         1/1              assign rvalid_o = ~empty & ~under_rst;
           Tests:       T1 T2 T3 
83                      
84                          prim_fifo_sync_cnt #(
85                            .Depth(Depth),
86                            .Secure(Secure)
87                          ) u_fifo_cnt (
88                            .clk_i,
89                            .rst_ni,
90                            .clr_i,
91                            .incr_wptr_i(fifo_incr_wptr),
92                            .incr_rptr_i(fifo_incr_rptr),
93                            .wptr_o(fifo_wptr),
94                            .rptr_o(fifo_rptr),
95                            .full_o,
96                            .empty_o(fifo_empty),
97                            .depth_o,
98                            .err_o
99                          );
100        1/1              assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
           Tests:       T1 T2 T3 
101        1/1              assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
           Tests:       T1 T2 T3 
102                     
103                         // the generate blocks below are needed to avoid lint errors due to array indexing
104                         // in the where the fifo only has one storage element
105                         logic [Depth-1:0][Width-1:0] storage;
106                         logic [Width-1:0] storage_rdata;
107                         if (Depth == 1) begin : gen_depth_eq1
108                           assign storage_rdata = storage[0];
109                     
110                           always_ff @(posedge clk_i)
111                             if (fifo_incr_wptr) begin
112                               storage[0] <= wdata_i;
113                             end
114                     
115                           logic unused_ptrs;
116                           assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
117                     
118                         // fifo with more than one storage element
119                         end else begin : gen_depth_gt1
120        1/1                assign storage_rdata = storage[fifo_rptr];
           Tests:       T1 T2 T3 
121                     
122                           always_ff @(posedge clk_i)
123        1/1                  if (fifo_incr_wptr) begin
           Tests:       T1 T2 T3 
124        1/1                    storage[fifo_wptr] <= wdata_i;
           Tests:       T2 T27 T29 
125                             end
                        MISSING_ELSE
126                         end
127                     
128                         logic [Width-1:0] rdata_int;
129                         if (Pass == 1'b1) begin : gen_pass
130                           assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
131                           assign empty = fifo_empty & ~wvalid_i;
132                         end else begin : gen_nopass
133        1/1                assign rdata_int = storage_rdata;
           Tests:       T2 T27 T29 
134        1/1                assign empty = fifo_empty;
           Tests:       T1 T2 T3 
135                         end
136                     
137                         if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138        1/1                assign rdata_o = empty ? Width'(0) : rdata_int;
           Tests:       T1 T2 T3

Cond Coverage for Instance : tb.dut.usbdev_rxfifo

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T20,T59,T60
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T2,T27,T29

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T2,T27,T29

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Not Covered
1	0	1	Covered	T2,T27,T29
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T2,T29,T30

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T2,T27,T29
1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.usbdev_rxfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00



138              assign rdata_o = empty ? Width'(0) : rdata_int;
                                        -1-  
                                        ==>  
                                        ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T27,T29



69               if (!rst_ni) begin
                 -1-  
70                 under_rst <= 1'b1;
                   ==>
71               end else if (under_rst) begin
                          -2-  
72                 under_rst <= ~under_rst;
                   ==>
73               end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3



123                if (fifo_incr_wptr) begin
                   -1-     
124                  storage[fifo_wptr] <= wdata_i;
                     ==>
125                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T2,T27,T29
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.usbdev_rxfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	578611326	45799241	0	0
DataKnown_AKnownEnable	578611326	578320424	0	0
DepthKnown_A	578611326	578320424	0	0
RvalidKnown_A	578611326	578320424	0	0
WreadyKnown_A	578611326	578320424	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	578611326	45799241	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	578611326	45799241
T2	7617	91
T3	6918	0
T27	9068	1197
T28	8119	0
T29	23729	762
T30	41711	1140
T31	0	1094
T33	0	100
T34	0	108
T35	0	101
T36	0	1138
T37	0	2850
T40	4128	0
T41	6638	0
T42	23439	0
T43	28526	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	578611326	578320424
T1	6612	6551
T2	7617	7517
T3	6918	6849
T27	9068	8987
T28	8119	8036
T29	23729	23634
T40	4128	4054
T41	6638	6580
T42	23439	23369
T43	28526	28432

DepthKnown_A

Name	Attempts	Real Successes
Total	578611326	578320424
T1	6612	6551
T2	7617	7517
T3	6918	6849
T27	9068	8987
T28	8119	8036
T29	23729	23634
T40	4128	4054
T41	6638	6580
T42	23439	23369
T43	28526	28432

RvalidKnown_A

Name	Attempts	Real Successes
Total	578611326	578320424
T1	6612	6551
T2	7617	7517
T3	6918	6849
T27	9068	8987
T28	8119	8036
T29	23729	23634
T40	4128	4054
T41	6638	6580
T42	23439	23369
T43	28526	28432

WreadyKnown_A

Name	Attempts	Real Successes
Total	578611326	578320424
T1	6612	6551
T2	7617	7517
T3	6918	6849
T27	9068	8987
T28	8119	8036
T29	23729	23634
T40	4128	4054
T41	6638	6580
T42	23439	23369
T43	28526	28432

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes
Total	578611326	45799241
T2	7617	91
T3	6918	0
T27	9068	1197
T28	8119	0
T29	23729	762
T30	41711	1140
T31	0	1094
T33	0	100
T34	0	108
T35	0	101
T36	0	1138
T37	0	2850
T40	4128	0
T41	6638	0
T42	23439	0
T43	28526	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	580407123	20340085	0	0
DataKnown_AKnownEnable	580407123	580074828	0	0
DepthKnown_A	580407123	580074828	0	0
RvalidKnown_A	580407123	580074828	0	0
WreadyKnown_A	580407123	580074828	0	0
gen_passthru_fifo.paramCheckPass	3866	3866	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	580407123	20340085
T1	6612	18
T2	7617	14
T3	6918	12
T27	9068	20
T28	8119	15
T29	23729	163
T40	4128	7
T41	6638	11
T42	23439	42
T43	28526	58

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	580407123	580074828
T1	6612	6551
T2	7617	7517
T3	6918	6849
T27	9068	8987
T28	8119	8036
T29	23729	23634
T40	4128	4054
T41	6638	6580
T42	23439	23369
T43	28526	28432

DepthKnown_A

Name	Attempts	Real Successes
Total	580407123	580074828
T1	6612	6551
T2	7617	7517
T3	6918	6849
T27	9068	8987
T28	8119	8036
T29	23729	23634
T40	4128	4054
T41	6638	6580
T42	23439	23369
T43	28526	28432

RvalidKnown_A

Name	Attempts	Real Successes
Total	580407123	580074828
T1	6612	6551
T2	7617	7517
T3	6918	6849
T27	9068	8987
T28	8119	8036
T29	23729	23634
T40	4128	4054
T41	6638	6580
T42	23439	23369
T43	28526	28432

WreadyKnown_A

Name	Attempts	Real Successes
Total	580407123	580074828
T1	6612	6551
T2	7617	7517
T3	6918	6849
T27	9068	8987
T28	8119	8036
T29	23729	23634
T40	4128	4054
T41	6638	6580
T42	23439	23369
T43	28526	28432

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	3866	3866
T1	1	1
T2	1	1
T3	1	1
T27	1	1
T28	1	1
T29	1	1
T40	1	1
T41	1	1
T42	1	1
T43	1	1

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	580407123	28077160	0	0
DataKnown_AKnownEnable	580407123	580074828	0	0
DepthKnown_A	580407123	580074828	0	0
RvalidKnown_A	580407123	580074828	0	0
WreadyKnown_A	580407123	580074828	0	0
gen_passthru_fifo.paramCheckPass	3866	3866	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	580407123	28077160
T1	6612	18
T2	7617	14
T3	6918	12
T27	9068	83
T28	8119	66
T29	23729	163
T40	4128	32
T41	6638	31
T42	23439	169
T43	28526	58

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	580407123	580074828
T1	6612	6551
T2	7617	7517
T3	6918	6849
T27	9068	8987
T28	8119	8036
T29	23729	23634
T40	4128	4054
T41	6638	6580
T42	23439	23369
T43	28526	28432

DepthKnown_A

Name	Attempts	Real Successes
Total	580407123	580074828
T1	6612	6551
T2	7617	7517
T3	6918	6849
T27	9068	8987
T28	8119	8036
T29	23729	23634
T40	4128	4054
T41	6638	6580
T42	23439	23369
T43	28526	28432

RvalidKnown_A

Name	Attempts	Real Successes
Total	580407123	580074828
T1	6612	6551
T2	7617	7517
T3	6918	6849
T27	9068	8987
T28	8119	8036
T29	23729	23634
T40	4128	4054
T41	6638	6580
T42	23439	23369
T43	28526	28432

WreadyKnown_A

Name	Attempts	Real Successes
Total	580407123	580074828
T1	6612	6551
T2	7617	7517
T3	6918	6849
T27	9068	8987
T28	8119	8036
T29	23729	23634
T40	4128	4054
T41	6638	6580
T42	23439	23369
T43	28526	28432

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	3866	3866
T1	1	1
T2	1	1
T3	1	1
T27	1	1
T28	1	1
T29	1	1
T40	1	1
T41	1	1
T42	1	1
T43	1	1

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	580407123	935518	0	0
DataKnown_AKnownEnable	580407123	580074828	0	0
DepthKnown_A	580407123	580074828	0	0
RvalidKnown_A	580407123	580074828	0	0
WreadyKnown_A	580407123	580074828	0	0
gen_passthru_fifo.paramCheckPass	3866	3866	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	580407123	935518
T2	7617	2
T3	6918	0
T18	0	16
T27	9068	0
T28	8119	0
T29	23729	63
T30	41711	92
T31	0	75
T33	0	10
T35	0	3
T36	0	91
T40	4128	0
T41	6638	0
T42	23439	6
T43	28526	4

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	580407123	580074828
T1	6612	6551
T2	7617	7517
T3	6918	6849
T27	9068	8987
T28	8119	8036
T29	23729	23634
T40	4128	4054
T41	6638	6580
T42	23439	23369
T43	28526	28432

DepthKnown_A

Name	Attempts	Real Successes
Total	580407123	580074828
T1	6612	6551
T2	7617	7517
T3	6918	6849
T27	9068	8987
T28	8119	8036
T29	23729	23634
T40	4128	4054
T41	6638	6580
T42	23439	23369
T43	28526	28432

RvalidKnown_A

Name	Attempts	Real Successes
Total	580407123	580074828
T1	6612	6551
T2	7617	7517
T3	6918	6849
T27	9068	8987
T28	8119	8036
T29	23729	23634
T40	4128	4054
T41	6638	6580
T42	23439	23369
T43	28526	28432

WreadyKnown_A

Name	Attempts	Real Successes
Total	580407123	580074828
T1	6612	6551
T2	7617	7517
T3	6918	6849
T27	9068	8987
T28	8119	8036
T29	23729	23634
T40	4128	4054
T41	6638	6580
T42	23439	23369
T43	28526	28432

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	3866	3866
T1	1	1
T2	1	1
T3	1	1
T27	1	1
T28	1	1
T29	1	1
T40	1	1
T41	1	1
T42	1	1
T43	1	1

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	580407123	1707763	0	0
DataKnown_AKnownEnable	580407123	580074828	0	0
DepthKnown_A	580407123	580074828	0	0
RvalidKnown_A	580407123	580074828	0	0
WreadyKnown_A	580407123	580074828	0	0
gen_passthru_fifo.paramCheckPass	3866	3866	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	580407123	1707763
T2	7617	2
T3	6918	0
T18	0	16
T27	9068	0
T28	8119	0
T29	23729	63
T30	41711	370
T31	0	75
T33	0	10
T35	0	3
T36	0	408
T40	4128	0
T41	6638	0
T42	23439	27
T43	28526	4

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	580407123	580074828
T1	6612	6551
T2	7617	7517
T3	6918	6849
T27	9068	8987
T28	8119	8036
T29	23729	23634
T40	4128	4054
T41	6638	6580
T42	23439	23369
T43	28526	28432

DepthKnown_A

Name	Attempts	Real Successes
Total	580407123	580074828
T1	6612	6551
T2	7617	7517
T3	6918	6849
T27	9068	8987
T28	8119	8036
T29	23729	23634
T40	4128	4054
T41	6638	6580
T42	23439	23369
T43	28526	28432

RvalidKnown_A

Name	Attempts	Real Successes
Total	580407123	580074828
T1	6612	6551
T2	7617	7517
T3	6918	6849
T27	9068	8987
T28	8119	8036
T29	23729	23634
T40	4128	4054
T41	6638	6580
T42	23439	23369
T43	28526	28432

WreadyKnown_A

Name	Attempts	Real Successes
Total	580407123	580074828
T1	6612	6551
T2	7617	7517
T3	6918	6849
T27	9068	8987
T28	8119	8036
T29	23729	23634
T40	4128	4054
T41	6638	6580
T42	23439	23369
T43	28526	28432

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	3866	3866
T1	1	1
T2	1	1
T3	1	1
T27	1	1
T28	1	1
T29	1	1
T40	1	1
T41	1	1
T42	1	1
T43	1	1

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	580407123	19346038	0	0
DataKnown_AKnownEnable	580407123	580074828	0	0
DepthKnown_A	580407123	580074828	0	0
RvalidKnown_A	580407123	580074828	0	0
WreadyKnown_A	580407123	580074828	0	0
gen_passthru_fifo.paramCheckPass	3866	3866	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	580407123	19346038
T1	6612	18
T2	7617	12
T3	6918	12
T27	9068	20
T28	8119	15
T29	23729	100
T40	4128	7
T41	6638	11
T42	23439	36
T43	28526	54

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	580407123	580074828
T1	6612	6551
T2	7617	7517
T3	6918	6849
T27	9068	8987
T28	8119	8036
T29	23729	23634
T40	4128	4054
T41	6638	6580
T42	23439	23369
T43	28526	28432

DepthKnown_A

Name	Attempts	Real Successes
Total	580407123	580074828
T1	6612	6551
T2	7617	7517
T3	6918	6849
T27	9068	8987
T28	8119	8036
T29	23729	23634
T40	4128	4054
T41	6638	6580
T42	23439	23369
T43	28526	28432

RvalidKnown_A

Name	Attempts	Real Successes
Total	580407123	580074828
T1	6612	6551
T2	7617	7517
T3	6918	6849
T27	9068	8987
T28	8119	8036
T29	23729	23634
T40	4128	4054
T41	6638	6580
T42	23439	23369
T43	28526	28432

WreadyKnown_A

Name	Attempts	Real Successes
Total	580407123	580074828
T1	6612	6551
T2	7617	7517
T3	6918	6849
T27	9068	8987
T28	8119	8036
T29	23729	23634
T40	4128	4054
T41	6638	6580
T42	23439	23369
T43	28526	28432

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	3866	3866
T1	1	1
T2	1	1
T3	1	1
T27	1	1
T28	1	1
T29	1	1
T40	1	1
T41	1	1
T42	1	1
T43	1	1

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	580407123	26369397	0	0
DataKnown_AKnownEnable	580407123	580074828	0	0
DepthKnown_A	580407123	580074828	0	0
RvalidKnown_A	580407123	580074828	0	0
WreadyKnown_A	580407123	580074828	0	0
gen_passthru_fifo.paramCheckPass	3866	3866	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	580407123	26369397
T1	6612	18
T2	7617	12
T3	6918	12
T27	9068	83
T28	8119	66
T29	23729	100
T40	4128	32
T41	6638	31
T42	23439	142
T43	28526	54

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	580407123	580074828
T1	6612	6551
T2	7617	7517
T3	6918	6849
T27	9068	8987
T28	8119	8036
T29	23729	23634
T40	4128	4054
T41	6638	6580
T42	23439	23369
T43	28526	28432

DepthKnown_A

Name	Attempts	Real Successes
Total	580407123	580074828
T1	6612	6551
T2	7617	7517
T3	6918	6849
T27	9068	8987
T28	8119	8036
T29	23729	23634
T40	4128	4054
T41	6638	6580
T42	23439	23369
T43	28526	28432

RvalidKnown_A

Name	Attempts	Real Successes
Total	580407123	580074828
T1	6612	6551
T2	7617	7517
T3	6918	6849
T27	9068	8987
T28	8119	8036
T29	23729	23634
T40	4128	4054
T41	6638	6580
T42	23439	23369
T43	28526	28432

WreadyKnown_A

Name	Attempts	Real Successes
Total	580407123	580074828
T1	6612	6551
T2	7617	7517
T3	6918	6849
T27	9068	8987
T28	8119	8036
T29	23729	23634
T40	4128	4054
T41	6638	6580
T42	23439	23369
T43	28526	28432

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	3866	3866
T1	1	1
T2	1	1
T3	1	1
T27	1	1
T28	1	1
T29	1	1
T40	1	1
T41	1	1
T42	1	1
T43	1	1

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00



68                          always_ff @(posedge clk_i or negedge rst_ni) begin
69         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
70         1/1                  under_rst <= 1'b1;
           Tests:       T1 T2 T3 
71         1/1                end else if (under_rst) begin
           Tests:       T1 T2 T3 
72         1/1                  under_rst <= ~under_rst;
           Tests:       T1 T2 T3 
73                            end
                        MISSING_ELSE
74                          end
75                      
76                          logic empty;
77                      
78                          // full and not ready for write are two different concepts.
79                          // The latter can be '0' when under reset, while the former is an indication that no more
80                          // entries can be written.
81         1/1              assign wready_o = ~full_o & ~under_rst;
           Tests:       T1 T2 T3 
82         1/1              assign rvalid_o = ~empty & ~under_rst;
           Tests:       T1 T2 T3 
83                      
84                          prim_fifo_sync_cnt #(
85                            .Depth(Depth),
86                            .Secure(Secure)
87                          ) u_fifo_cnt (
88                            .clk_i,
89                            .rst_ni,
90                            .clr_i,
91                            .incr_wptr_i(fifo_incr_wptr),
92                            .incr_rptr_i(fifo_incr_rptr),
93                            .wptr_o(fifo_wptr),
94                            .rptr_o(fifo_rptr),
95                            .full_o,
96                            .empty_o(fifo_empty),
97                            .depth_o,
98                            .err_o
99                          );
100        1/1              assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
           Tests:       T1 T2 T3 
101        1/1              assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
           Tests:       T1 T2 T3 
102                     
103                         // the generate blocks below are needed to avoid lint errors due to array indexing
104                         // in the where the fifo only has one storage element
105                         logic [Depth-1:0][Width-1:0] storage;
106                         logic [Width-1:0] storage_rdata;
107                         if (Depth == 1) begin : gen_depth_eq1
108        1/1                assign storage_rdata = storage[0];
           Tests:       T2 T42 T29 
109                     
110                           always_ff @(posedge clk_i)
111        1/1                  if (fifo_incr_wptr) begin
           Tests:       T1 T2 T3 
112        1/1                    storage[0] <= wdata_i;
           Tests:       T2 T42 T29 
113                             end
                        MISSING_ELSE
114                     
115                           logic unused_ptrs;
116        1/1                assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
           Tests:       T1 T2 T3 
117                     
118                         // fifo with more than one storage element
119                         end else begin : gen_depth_gt1
120                           assign storage_rdata = storage[fifo_rptr];
121                     
122                           always_ff @(posedge clk_i)
123                             if (fifo_incr_wptr) begin
124                               storage[fifo_wptr] <= wdata_i;
125                             end
126                         end
127                     
128                         logic [Width-1:0] rdata_int;
129                         if (Pass == 1'b1) begin : gen_pass
130                           assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
131                           assign empty = fifo_empty & ~wvalid_i;
132                         end else begin : gen_nopass
133        1/1                assign rdata_int = storage_rdata;
           Tests:       T2 T42 T29 
134        1/1                assign empty = fifo_empty;
           Tests:       T1 T2 T3 
135                         end
136                     
137                         if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138        1/1                assign rdata_o = empty ? Width'(0) : rdata_int;
           Tests:       T1 T2 T3

Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Total	Covered	Percent
Conditions	11	11	100.00
Logical	11	11	100.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T42,T29
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T2,T42,T29

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T2,T42,T29

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Excluded		VC_COV_UNR
1	0	1	Covered	T42,T29,T43
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T2,T42,T29

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T2,T42,T29
1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00



138              assign rdata_o = empty ? Width'(0) : rdata_int;
                                        -1-  
                                        ==>  
                                        ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T42,T29



69               if (!rst_ni) begin
                 -1-  
70                 under_rst <= 1'b1;
                   ==>
71               end else if (under_rst) begin
                          -2-  
72                 under_rst <= ~under_rst;
                   ==>
73               end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3



123                if (fifo_incr_wptr) begin
                   -1-     
124                  storage[fifo_wptr] <= wdata_i;
                     ==>
125                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T2,T42,T29
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	578611326	1661631	0	0
DataKnown_AKnownEnable	578611326	578320424	0	0
DepthKnown_A	578611326	578320424	0	0
RvalidKnown_A	578611326	578320424	0	0
WreadyKnown_A	578611326	578320424	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	578611326	1661631	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	578611326	1661631
T2	7617	2
T3	6918	0
T18	0	16
T27	9068	0
T28	8119	0
T29	23729	63
T30	41711	370
T31	0	75
T33	0	10
T35	0	3
T36	0	408
T40	4128	0
T41	6638	0
T42	23439	27
T43	28526	4

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	578611326	578320424
T1	6612	6551
T2	7617	7517
T3	6918	6849
T27	9068	8987
T28	8119	8036
T29	23729	23634
T40	4128	4054
T41	6638	6580
T42	23439	23369
T43	28526	28432

DepthKnown_A

Name	Attempts	Real Successes
Total	578611326	578320424
T1	6612	6551
T2	7617	7517
T3	6918	6849
T27	9068	8987
T28	8119	8036
T29	23729	23634
T40	4128	4054
T41	6638	6580
T42	23439	23369
T43	28526	28432

RvalidKnown_A

Name	Attempts	Real Successes
Total	578611326	578320424
T1	6612	6551
T2	7617	7517
T3	6918	6849
T27	9068	8987
T28	8119	8036
T29	23729	23634
T40	4128	4054
T41	6638	6580
T42	23439	23369
T43	28526	28432

WreadyKnown_A

Name	Attempts	Real Successes
Total	578611326	578320424
T1	6612	6551
T2	7617	7517
T3	6918	6849
T27	9068	8987
T28	8119	8036
T29	23729	23634
T40	4128	4054
T41	6638	6580
T42	23439	23369
T43	28526	28432

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes
Total	578611326	1661631
T2	7617	2
T3	6918	0
T18	0	16
T27	9068	0
T28	8119	0
T29	23729	63
T30	41711	370
T31	0	75
T33	0	10
T35	0	3
T36	0	408
T40	4128	0
T41	6638	0
T42	23439	27
T43	28526	4

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00



68                          always_ff @(posedge clk_i or negedge rst_ni) begin
69         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
70         1/1                  under_rst <= 1'b1;
           Tests:       T1 T2 T3 
71         1/1                end else if (under_rst) begin
           Tests:       T1 T2 T3 
72         1/1                  under_rst <= ~under_rst;
           Tests:       T1 T2 T3 
73                            end
                        MISSING_ELSE
74                          end
75                      
76                          logic empty;
77                      
78                          // full and not ready for write are two different concepts.
79                          // The latter can be '0' when under reset, while the former is an indication that no more
80                          // entries can be written.
81         1/1              assign wready_o = ~full_o & ~under_rst;
           Tests:       T1 T2 T3 
82         1/1              assign rvalid_o = ~empty & ~under_rst;
           Tests:       T1 T2 T3 
83                      
84                          prim_fifo_sync_cnt #(
85                            .Depth(Depth),
86                            .Secure(Secure)
87                          ) u_fifo_cnt (
88                            .clk_i,
89                            .rst_ni,
90                            .clr_i,
91                            .incr_wptr_i(fifo_incr_wptr),
92                            .incr_rptr_i(fifo_incr_rptr),
93                            .wptr_o(fifo_wptr),
94                            .rptr_o(fifo_rptr),
95                            .full_o,
96                            .empty_o(fifo_empty),
97                            .depth_o,
98                            .err_o
99                          );
100        1/1              assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
           Tests:       T1 T2 T3 
101        1/1              assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
           Tests:       T1 T2 T3 
102                     
103                         // the generate blocks below are needed to avoid lint errors due to array indexing
104                         // in the where the fifo only has one storage element
105                         logic [Depth-1:0][Width-1:0] storage;
106                         logic [Width-1:0] storage_rdata;
107                         if (Depth == 1) begin : gen_depth_eq1
108        1/1                assign storage_rdata = storage[0];
           Tests:       T2 T29 T30 
109                     
110                           always_ff @(posedge clk_i)
111        1/1                  if (fifo_incr_wptr) begin
           Tests:       T1 T2 T3 
112        1/1                    storage[0] <= wdata_i;
           Tests:       T2 T29 T30 
113                             end
                        MISSING_ELSE
114                     
115                           logic unused_ptrs;
116        1/1                assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
           Tests:       T1 T2 T3 
117                     
118                         // fifo with more than one storage element
119                         end else begin : gen_depth_gt1
120                           assign storage_rdata = storage[fifo_rptr];
121                     
122                           always_ff @(posedge clk_i)
123                             if (fifo_incr_wptr) begin
124                               storage[fifo_wptr] <= wdata_i;
125                             end
126                         end
127                     
128                         logic [Width-1:0] rdata_int;
129                         if (Pass == 1'b1) begin : gen_pass
130                           assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
131                           assign empty = fifo_empty & ~wvalid_i;
132                         end else begin : gen_nopass
133        1/1                assign rdata_int = storage_rdata;
           Tests:       T2 T29 T30 
134        1/1                assign empty = fifo_empty;
           Tests:       T1 T2 T3 
135                         end
136                     
137                         if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138        1/1                assign rdata_o = empty ? Width'(0) : rdata_int;
           Tests:       T1 T2 T3

Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T29,T30
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T2,T29,T30

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T2,T29,T30

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Excluded		VC_COV_UNR
1	0	1	Excluded		VC_COV_UNR
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T2,T29,T30

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (5'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T2,T29,T30
1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00



138              assign rdata_o = empty ? Width'(0) : rdata_int;
                                        -1-  
                                        ==>  
                                        ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T29,T30



69               if (!rst_ni) begin
                 -1-  
70                 under_rst <= 1'b1;
                   ==>
71               end else if (under_rst) begin
                          -2-  
72                 under_rst <= ~under_rst;
                   ==>
73               end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3



123                if (fifo_incr_wptr) begin
                   -1-     
124                  storage[fifo_wptr] <= wdata_i;
                     ==>
125                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T2,T29,T30
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	578611326	601958	0	0
DataKnown_AKnownEnable	578611326	578320424	0	0
DepthKnown_A	578611326	578320424	0	0
RvalidKnown_A	578611326	578320424	0	0
WreadyKnown_A	578611326	578320424	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	578611326	601958	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	578611326	601958
T2	7617	2
T3	6918	0
T18	0	16
T27	9068	0
T28	8119	0
T29	23729	63
T30	41711	92
T31	0	75
T33	0	10
T35	0	3
T36	0	91
T40	4128	0
T41	6638	0
T42	23439	0
T43	28526	0
T57	0	52
T88	0	304

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	578611326	578320424
T1	6612	6551
T2	7617	7517
T3	6918	6849
T27	9068	8987
T28	8119	8036
T29	23729	23634
T40	4128	4054
T41	6638	6580
T42	23439	23369
T43	28526	28432

DepthKnown_A

Name	Attempts	Real Successes
Total	578611326	578320424
T1	6612	6551
T2	7617	7517
T3	6918	6849
T27	9068	8987
T28	8119	8036
T29	23729	23634
T40	4128	4054
T41	6638	6580
T42	23439	23369
T43	28526	28432

RvalidKnown_A

Name	Attempts	Real Successes
Total	578611326	578320424
T1	6612	6551
T2	7617	7517
T3	6918	6849
T27	9068	8987
T28	8119	8036
T29	23729	23634
T40	4128	4054
T41	6638	6580
T42	23439	23369
T43	28526	28432

WreadyKnown_A

Name	Attempts	Real Successes
Total	578611326	578320424
T1	6612	6551
T2	7617	7517
T3	6918	6849
T27	9068	8987
T28	8119	8036
T29	23729	23634
T40	4128	4054
T41	6638	6580
T42	23439	23369
T43	28526	28432

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes
Total	578611326	601958
T2	7617	2
T3	6918	0
T18	0	16
T27	9068	0
T28	8119	0
T29	23729	63
T30	41711	92
T31	0	75
T33	0	10
T35	0	3
T36	0	91
T40	4128	0
T41	6638	0
T42	23439	0
T43	28526	0
T57	0	52
T88	0	304

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00



68                          always_ff @(posedge clk_i or negedge rst_ni) begin
69         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
70         1/1                  under_rst <= 1'b1;
           Tests:       T1 T2 T3 
71         1/1                end else if (under_rst) begin
           Tests:       T1 T2 T3 
72         1/1                  under_rst <= ~under_rst;
           Tests:       T1 T2 T3 
73                            end
                        MISSING_ELSE
74                          end
75                      
76                          logic empty;
77                      
78                          // full and not ready for write are two different concepts.
79                          // The latter can be '0' when under reset, while the former is an indication that no more
80                          // entries can be written.
81         1/1              assign wready_o = ~full_o & ~under_rst;
           Tests:       T1 T2 T3 
82         1/1              assign rvalid_o = ~empty & ~under_rst;
           Tests:       T1 T2 T3 
83                      
84                          prim_fifo_sync_cnt #(
85                            .Depth(Depth),
86                            .Secure(Secure)
87                          ) u_fifo_cnt (
88                            .clk_i,
89                            .rst_ni,
90                            .clr_i,
91                            .incr_wptr_i(fifo_incr_wptr),
92                            .incr_rptr_i(fifo_incr_rptr),
93                            .wptr_o(fifo_wptr),
94                            .rptr_o(fifo_rptr),
95                            .full_o,
96                            .empty_o(fifo_empty),
97                            .depth_o,
98                            .err_o
99                          );
100        1/1              assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
           Tests:       T1 T2 T3 
101        1/1              assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
           Tests:       T1 T2 T3 
102                     
103                         // the generate blocks below are needed to avoid lint errors due to array indexing
104                         // in the where the fifo only has one storage element
105                         logic [Depth-1:0][Width-1:0] storage;
106                         logic [Width-1:0] storage_rdata;
107                         if (Depth == 1) begin : gen_depth_eq1
108        1/1                assign storage_rdata = storage[0];
           Tests:       T2 T29 T30 
109                     
110                           always_ff @(posedge clk_i)
111        1/1                  if (fifo_incr_wptr) begin
           Tests:       T1 T2 T3 
112        1/1                    storage[0] <= wdata_i;
           Tests:       T2 T29 T30 
113                             end
                        MISSING_ELSE
114                     
115                           logic unused_ptrs;
116        1/1                assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
           Tests:       T1 T2 T3 
117                     
118                         // fifo with more than one storage element
119                         end else begin : gen_depth_gt1
120                           assign storage_rdata = storage[fifo_rptr];
121                     
122                           always_ff @(posedge clk_i)
123                             if (fifo_incr_wptr) begin
124                               storage[fifo_wptr] <= wdata_i;
125                             end
126                         end
127                     
128                         logic [Width-1:0] rdata_int;
129                         if (Pass == 1'b1) begin : gen_pass
130        1/1                assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
           Tests:       T1 T2 T3 
131        1/1                assign empty = fifo_empty & ~wvalid_i;
           Tests:       T1 T2 T3 
132                         end else begin : gen_nopass
133                           assign rdata_int = storage_rdata;
134                           assign empty = fifo_empty;
135                         end
136                     
137                         if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138        1/1                assign rdata_o = empty ? Width'(0) : rdata_int;
           Tests:       T1 T2 T3

Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Total	Covered	Percent
Conditions	18	18	100.00
Logical	18	18	100.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T30,T36,T87
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T2,T29,T30

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T2,T29,T30

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Excluded		VC_COV_UNR
1	0	1	Covered	T29,T30,T31
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T2,T29,T30

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T29,T30

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T29,T30

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T30,T36,T87
1	0	Covered	T2,T29,T30
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (40'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T2,T29,T30
1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00



130              assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
                                                             -1-  
                                                             ==>  
                                                             ==>

Branches:

-1-	Status	Tests
1	Covered	T2,T29,T30
0	Covered	T1,T2,T3



138              assign rdata_o = empty ? Width'(0) : rdata_int;
                                        -1-  
                                        ==>  
                                        ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T29,T30



69               if (!rst_ni) begin
                 -1-  
70                 under_rst <= 1'b1;
                   ==>
71               end else if (under_rst) begin
                          -2-  
72                 under_rst <= ~under_rst;
                   ==>
73               end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3



111                if (fifo_incr_wptr) begin
                   -1-     
112                  storage[0] <= wdata_i;
                     ==>
113                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T2,T29,T30
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	578611326	1138683	0	0
DataKnown_AKnownEnable	578611326	578320424	0	0
DepthKnown_A	578611326	578320424	0	0
RvalidKnown_A	578611326	578320424	0	0
WreadyKnown_A	578611326	578320424	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	578611326	1138683	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	578611326	1138683
T2	7617	2
T3	6918	0
T18	0	16
T27	9068	0
T28	8119	0
T29	23729	63
T30	41711	370
T31	0	75
T33	0	10
T35	0	3
T36	0	408
T40	4128	0
T41	6638	0
T42	23439	0
T43	28526	0
T57	0	52
T88	0	304

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	578611326	578320424
T1	6612	6551
T2	7617	7517
T3	6918	6849
T27	9068	8987
T28	8119	8036
T29	23729	23634
T40	4128	4054
T41	6638	6580
T42	23439	23369
T43	28526	28432

DepthKnown_A

Name	Attempts	Real Successes
Total	578611326	578320424
T1	6612	6551
T2	7617	7517
T3	6918	6849
T27	9068	8987
T28	8119	8036
T29	23729	23634
T40	4128	4054
T41	6638	6580
T42	23439	23369
T43	28526	28432

RvalidKnown_A

Name	Attempts	Real Successes
Total	578611326	578320424
T1	6612	6551
T2	7617	7517
T3	6918	6849
T27	9068	8987
T28	8119	8036
T29	23729	23634
T40	4128	4054
T41	6638	6580
T42	23439	23369
T43	28526	28432

WreadyKnown_A

Name	Attempts	Real Successes
Total	578611326	578320424
T1	6612	6551
T2	7617	7517
T3	6918	6849
T27	9068	8987
T28	8119	8036
T29	23729	23634
T40	4128	4054
T41	6638	6580
T42	23439	23369
T43	28526	28432

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes
Total	578611326	1138683
T2	7617	2
T3	6918	0
T18	0	16
T27	9068	0
T28	8119	0
T29	23729	63
T30	41711	370
T31	0	75
T33	0	10
T35	0	3
T36	0	408
T40	4128	0
T41	6638	0
T42	23439	0
T43	28526	0
T57	0	52
T88	0	304

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.99	97.53	92.86	94.55		100.00	100.00	dut

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.99	97.53	92.86	94.55		100.00	100.00	dut

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00