Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	10117335	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

10713414

1

T1

13

T2

23

T3

9

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	20173577	1			T1	52		T2	20		T3	10
values[0x0]	328075	1			T1	7		T2	4		T3	6
values[0x1]	329097	1			T1	6		T2	3		T3	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8043330	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

12787419

1

T1

28

T2

23

T3

9

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	96818	1			T7	3		T28	4		T8	4
valid_sources[0x01]	79524	1			T7	2		T19	6		T28	1
valid_sources[0x02]	62687	1			T7	2		T16	2		T21	1
valid_sources[0x03]	120906	1			T7	1		T16	1		T28	1
valid_sources[0x04]	65691	1			T7	5		T28	7		T29	153
valid_sources[0x05]	62505	1			T7	4		T16	1		T28	7
valid_sources[0x06]	109657	1			T7	3		T19	1		T28	6
valid_sources[0x07]	62470	1			T7	3		T26	16		T28	4
valid_sources[0x08]	72152	1			T7	5		T17	1		T19	2
valid_sources[0x09]	182665	1			T7	7		T16	1		T28	5
valid_sources[0x0a]	62899	1			T7	1		T28	8		T8	1
valid_sources[0x0b]	62104	1			T7	3		T20	1		T21	2
valid_sources[0x0c]	61786	1			T7	5		T28	3		T8	3
valid_sources[0x0d]	84004	1			T2	1		T7	3		T19	1
valid_sources[0x0e]	149926	1			T7	6		T17	1		T28	6
valid_sources[0x0f]	80312	1			T7	3		T28	3		T29	150
valid_sources[0x10]	63177	1			T3	2		T7	5		T21	3
valid_sources[0x11]	77678	1			T7	3		T28	4		T29	153
valid_sources[0x12]	63488	1			T1	3		T7	2		T28	7
valid_sources[0x13]	63233	1			T28	11		T29	135		T40	18
valid_sources[0x14]	137875	1			T7	8		T28	4		T8	1
valid_sources[0x15]	63986	1			T7	5		T21	1		T28	3
valid_sources[0x16]	95157	1			T7	3		T18	5		T28	2
valid_sources[0x17]	82597	1			T7	5		T21	1		T28	2
valid_sources[0x18]	122257	1			T7	3		T28	6		T29	155
valid_sources[0x19]	62551	1			T2	1		T7	4		T19	2
valid_sources[0x1a]	62322	1			T1	3		T7	3		T28	5
valid_sources[0x1b]	121500	1			T7	5		T28	2		T29	129
valid_sources[0x1c]	87896	1			T2	1		T7	3		T21	1
valid_sources[0x1d]	90622	1			T7	2		T28	3		T8	1
valid_sources[0x1e]	63212	1			T7	5		T17	1		T28	5
valid_sources[0x1f]	64158	1			T7	2		T16	1		T28	4
valid_sources[0x20]	91935	1			T7	4		T27	1		T28	8
valid_sources[0x21]	63539	1			T1	1		T7	3		T28	4
valid_sources[0x22]	62533	1			T7	5		T28	5		T8	2
valid_sources[0x23]	64114	1			T7	4		T19	1		T28	4
valid_sources[0x24]	63990	1			T1	7		T7	8		T80	1
valid_sources[0x25]	72965	1			T7	4		T28	5		T29	155
valid_sources[0x26]	62459	1			T7	4		T19	8		T28	3
valid_sources[0x27]	88989	1			T7	4		T19	11		T80	1
valid_sources[0x28]	65677	1			T7	1		T28	5		T29	133
valid_sources[0x29]	64386	1			T7	4		T28	3		T29	134
valid_sources[0x2a]	63336	1			T7	4		T21	1		T28	5
valid_sources[0x2b]	76008	1			T7	1		T17	1		T19	4
valid_sources[0x2c]	63142	1			T7	2		T28	6		T29	152
valid_sources[0x2d]	63646	1			T2	1		T7	6		T16	1
valid_sources[0x2e]	63101	1			T7	5		T28	3		T8	1
valid_sources[0x2f]	62437	1			T7	7		T28	1		T29	138
valid_sources[0x30]	92004	1			T7	3		T21	1		T28	3
valid_sources[0x31]	62282	1			T7	6		T18	5		T28	4
valid_sources[0x32]	86572	1			T7	4		T19	1		T28	3
valid_sources[0x33]	62416	1			T7	6		T20	2		T21	1
valid_sources[0x34]	63926	1			T7	2		T19	11		T28	5
valid_sources[0x35]	70413	1			T7	4		T28	3		T8	1
valid_sources[0x36]	66113	1			T7	5		T16	1		T28	4
valid_sources[0x37]	62397	1			T7	5		T28	6		T29	159
valid_sources[0x38]	73550	1			T7	3		T28	3		T29	141
valid_sources[0x39]	116375	1			T1	3		T7	3		T19	3
valid_sources[0x3a]	137953	1			T7	3		T28	2		T8	3
valid_sources[0x3b]	170307	1			T7	3		T28	2		T8	1
valid_sources[0x3c]	71195	1			T7	12		T21	2		T28	3
valid_sources[0x3d]	84573	1			T7	5		T21	1		T28	5
valid_sources[0x3e]	64664	1			T7	2		T28	3		T29	140
valid_sources[0x3f]	63162	1			T7	1		T18	4		T26	8
valid_sources[0x40]	63657	1			T2	1		T7	4		T19	12
valid_sources[0x41]	63562	1			T2	1		T7	2		T16	2
valid_sources[0x42]	64211	1			T7	6		T17	1		T19	4
valid_sources[0x43]	151435	1			T7	5		T28	6		T29	156
valid_sources[0x44]	70506	1			T7	2		T28	6		T29	131
valid_sources[0x45]	64575	1			T7	2		T19	6		T21	1
valid_sources[0x46]	63494	1			T7	1		T19	4		T21	1
valid_sources[0x47]	62699	1			T7	4		T28	8		T29	136
valid_sources[0x48]	63245	1			T7	5		T21	1		T28	5
valid_sources[0x49]	98942	1			T1	5		T7	3		T28	4
valid_sources[0x4a]	62998	1			T7	6		T29	160		T4	26
valid_sources[0x4b]	63660	1			T7	2		T28	5		T29	140
valid_sources[0x4c]	63644	1			T7	3		T28	3		T29	152
valid_sources[0x4d]	64180	1			T7	3		T28	3		T29	144
valid_sources[0x4e]	86418	1			T7	6		T21	2		T28	3
valid_sources[0x4f]	62111	1			T7	7		T28	6		T29	133
valid_sources[0x50]	105040	1			T7	3		T26	27		T28	3
valid_sources[0x51]	63363	1			T7	4		T18	2		T28	8
valid_sources[0x52]	122456	1			T7	3		T19	1		T80	2
valid_sources[0x53]	76487	1			T7	5		T28	7		T29	132
valid_sources[0x54]	62772	1			T7	1		T28	2		T29	130
valid_sources[0x55]	62694	1			T7	5		T28	3		T29	125
valid_sources[0x56]	96147	1			T1	1		T28	7		T29	149
valid_sources[0x57]	137792	1			T7	8		T28	1		T29	149
valid_sources[0x58]	191687	1			T7	3		T28	6		T29	161
valid_sources[0x59]	63109	1			T7	3		T28	3		T29	141
valid_sources[0x5a]	63026	1			T7	3		T19	7		T21	1
valid_sources[0x5b]	108533	1			T7	3		T21	2		T28	3
valid_sources[0x5c]	62690	1			T7	4		T17	1		T21	1
valid_sources[0x5d]	90213	1			T7	4		T28	5		T8	1
valid_sources[0x5e]	61812	1			T7	1		T34	1		T28	5
valid_sources[0x5f]	77278	1			T1	6		T7	7		T21	1
valid_sources[0x60]	66403	1			T1	1		T3	1		T7	1
valid_sources[0x61]	62600	1			T7	4		T21	1		T28	4
valid_sources[0x62]	148049	1			T7	1		T26	5		T28	2
valid_sources[0x63]	62547	1			T7	3		T28	4		T8	2
valid_sources[0x64]	124887	1			T7	4		T28	5		T8	1
valid_sources[0x65]	114976	1			T7	3		T18	4		T19	2
valid_sources[0x66]	85315	1			T18	1		T28	6		T29	135
valid_sources[0x67]	66704	1			T7	3		T28	6		T8	3
valid_sources[0x68]	101460	1			T7	1		T19	12		T28	4
valid_sources[0x69]	61769	1			T1	2		T2	1		T7	4
valid_sources[0x6a]	64048	1			T7	6		T19	4		T28	8
valid_sources[0x6b]	84104	1			T7	6		T29	132		T95	3
valid_sources[0x6c]	125725	1			T7	5		T27	1		T28	5
valid_sources[0x6d]	79345	1			T7	4		T19	2		T28	4
valid_sources[0x6e]	81907	1			T7	3		T28	7		T8	1
valid_sources[0x6f]	65379	1			T7	3		T34	1		T28	4
valid_sources[0x70]	63636	1			T7	2		T28	8		T8	2
valid_sources[0x71]	64743	1			T7	4		T26	17		T28	2
valid_sources[0x72]	64375	1			T2	1		T7	1		T17	1
valid_sources[0x73]	75175	1			T28	2		T8	1		T29	162
valid_sources[0x74]	77883	1			T7	1		T26	11		T28	5
valid_sources[0x75]	62578	1			T1	1		T2	1		T7	8
valid_sources[0x76]	62994	1			T7	3		T28	5		T29	150
valid_sources[0x77]	65354	1			T7	2		T19	2		T28	8
valid_sources[0x78]	63641	1			T1	2		T3	1		T7	6
valid_sources[0x79]	89395	1			T7	1		T28	7		T29	158
valid_sources[0x7a]	64524	1			T7	2		T20	2		T34	1
valid_sources[0x7b]	62910	1			T7	4		T28	4		T29	126
valid_sources[0x7c]	62970	1			T3	2		T7	2		T21	1
valid_sources[0x7d]	63440	1			T7	6		T28	9		T8	2
valid_sources[0x7e]	62513	1			T2	1		T7	3		T28	4
valid_sources[0x7f]	64602	1			T21	1		T28	7		T8	1
valid_sources[0x80]	62771	1			T2	1		T7	2		T28	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

10183706

1

T1

2

T2

18

T3

2

values[0x0]

all_enables

biggest_size

273722

1

T1

7

T2

4

T3

4

values[0x1]

all_enables

biggest_size

255986

1

T1

4

T2

1

T3

3