Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

10129247

1

T1

52

T2

4

T3

11

full_word

10714211

1

T1

13

T2

23

T3

9

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	20843148	1			T1	65		T2	27		T3	20
auto[TlIntgErrCmd]	101	1			T188	4		T232	7		T233	10
auto[TlIntgErrData]	114	1			T188	5		T232	8		T233	3
auto[TlIntgErrBoth]	95	1			T188	1		T232	5		T233	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20175110

1

T1

52

T2

20

T3

10

auto[1]

668348

1

T1

13

T2

7

T3

10

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	9991133	1			T1	50		T2	2		T3	8
auto[TlIntgErrNone]	partial	auto[1]	137837	1			T1	2		T2	2		T3	3
auto[TlIntgErrNone]	full_word	auto[0]	10183834	1			T1	2		T2	18		T3	2
auto[TlIntgErrNone]	full_word	auto[1]	530344	1			T1	11		T2	5		T3	7
auto[TlIntgErrCmd]	partial	auto[0]	39	1			T188	2		T232	3		T233	6
auto[TlIntgErrCmd]	partial	auto[1]	55	1			T188	2		T232	4		T233	3
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T578	1		T245	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T233	1		T575	1		T579	1
auto[TlIntgErrData]	partial	auto[0]	58	1			T188	2		T232	5		T233	3
auto[TlIntgErrData]	partial	auto[1]	39	1			T188	3		T232	2		T570	2
auto[TlIntgErrData]	full_word	auto[0]	8	1			T232	1		T572	1		T580	1
auto[TlIntgErrData]	full_word	auto[1]	9	1			T571	1		T575	2		T579	1
auto[TlIntgErrBoth]	partial	auto[0]	33	1			T232	2		T233	5		T571	2
auto[TlIntgErrBoth]	partial	auto[1]	53	1			T188	1		T232	3		T233	1
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T574	1		T576	1		T577	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T233	1		T574	1		T572	1