Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.99	97.53	92.86	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	586564010	10082	0	0
ep_in_enable_rd_A	586564010	3323	0	0
ep_out_enable_rd_A	586564010	3488	0	0
in_iso_rd_A	586564010	3327	0	0
intr_enable_rd_A	586564010	4852	0	0
out_iso_rd_A	586564010	3461	0	0
phy_config_rd_A	586564010	1942	0	0
phy_pins_drive_rd_A	586564010	2754	0	0
rxenable_setup_rd_A	586564010	3593	0	0
set_nak_out_rd_A	586564010	3687	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	586564010	10082	0	0
T187	3244	317	0	0
T188	27995	4	0	0
T189	4710	8	0	0
T226	10636	763	0	0
T230	7019	307	0	0
T231	3697	576	0	0
T232	76616	6	0	0
T236	8477	576	0	0
T249	2735	7	0	0
T250	5316	4	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	586564010	3323	0	0
T189	4710	70	0	0
T227	5858	34	0	0
T232	76616	519	0	0
T233	37995	467	0	0
T234	4054	80	0	0
T244	10755	21	0	0
T275	9439	54	0	0
T278	5774	43	0	0
T288	11718	38	0	0
T289	9404	42	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	586564010	3488	0	0
T189	4710	58	0	0
T227	5858	10	0	0
T232	76616	481	0	0
T233	37995	475	0	0
T234	4054	98	0	0
T236	8477	8	0	0
T244	10755	71	0	0
T278	5774	5	0	0
T288	11718	53	0	0
T289	9404	12	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	586564010	3327	0	0
T189	4710	30	0	0
T227	5858	25	0	0
T232	76616	496	0	0
T233	37995	413	0	0
T234	4054	53	0	0
T244	10755	59	0	0
T275	9439	76	0	0
T278	5774	7	0	0
T288	11718	50	0	0
T289	9404	37	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	586564010	4852	0	0
T189	4710	59	0	0
T227	5858	60	0	0
T232	76616	873	0	0
T233	37995	671	0	0
T234	4054	5	0	0
T244	10755	19	0	0
T275	9439	65	0	0
T278	5774	22	0	0
T288	11718	45	0	0
T289	9404	19	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	586564010	3461	0	0
T189	4710	25	0	0
T227	5858	57	0	0
T232	76616	472	0	0
T233	37995	502	0	0
T234	4054	26	0	0
T244	10755	12	0	0
T275	9439	95	0	0
T288	11718	57	0	0
T289	9404	63	0	0
T290	4940	30	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	586564010	1942	0	0
T189	4710	2	0	0
T227	5858	18	0	0
T232	76616	238	0	0
T233	37995	224	0	0
T234	4054	31	0	0
T244	10755	65	0	0
T275	9439	73	0	0
T278	5774	30	0	0
T288	11718	37	0	0
T289	9404	40	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	586564010	2754	0	0
T189	4710	61	0	0
T227	5858	15	0	0
T232	76616	519	0	0
T233	37995	364	0	0
T234	4054	51	0	0
T244	10755	15	0	0
T275	9439	72	0	0
T278	5774	24	0	0
T288	11718	74	0	0
T289	9404	24	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	586564010	3593	0	0
T189	4710	44	0	0
T227	5858	10	0	0
T232	76616	398	0	0
T233	37995	546	0	0
T234	4054	107	0	0
T244	10755	71	0	0
T275	9439	101	0	0
T278	5774	17	0	0
T288	11718	59	0	0
T289	9404	13	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	586564010	3687	0	0
T189	4710	9	0	0
T227	5858	32	0	0
T232	76616	728	0	0
T233	37995	561	0	0
T234	4054	48	0	0
T244	10755	20	0	0
T275	9439	63	0	0
T278	5774	2	0	0
T288	11718	54	0	0
T289	9404	59	0	0