Line Coverage for Module :
usb_fs_nb_in_pe
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 120 | 117 | 97.50 |
| CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 132 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 141 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 149 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 154 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 169 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 172 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 178 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 186 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 188 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 189 | 1 | 1 | 100.00 |
| ALWAYS | 199 | 49 | 46 | 93.88 |
| ALWAYS | 303 | 3 | 3 | 100.00 |
| ALWAYS | 311 | 3 | 3 | 100.00 |
| ALWAYS | 319 | 8 | 8 | 100.00 |
| ALWAYS | 332 | 6 | 6 | 100.00 |
| ALWAYS | 344 | 9 | 9 | 100.00 |
| ALWAYS | 361 | 7 | 7 | 100.00 |
| CONT_ASSIGN | 375 | 1 | 1 | 100.00 |
| ALWAYS | 378 | 5 | 5 | 100.00 |
| ALWAYS | 388 | 5 | 5 | 100.00 |
| CONT_ASSIGN | 405 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 412 | 1 | 1 | 100.00 |
| ALWAYS | 422 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 425 | 1 | 1 | 100.00 |
117
118 1/1 assign in_ep_xact_end_o = in_xact_end;
Tests: T1 T2 T3
119
120 // data toggle state
121 logic [NumInEps-1:0] data_toggle_q, data_toggle_d;
122
123 // endpoint data buffer
124 logic token_received, setup_token_received, in_token_received, ack_received, nak_received;
125 logic more_data_to_send;
126 logic ep_in_hw, ep_active;
127 logic [3:0] in_ep_current_d;
128
129 // More syntax so can compare with enum
130 usb_pid_type_e rx_pid_type;
131 usb_pid_e rx_pid;
132 1/1 assign rx_pid_type = usb_pid_type_e'(rx_pid_i[1:0]);
Tests: T1 T2 T3
133 1/1 assign rx_pid = usb_pid_e'(rx_pid_i);
Tests: T1 T2 T3
134
135 1/1 assign token_received =
Tests: T1 T2 T3
136 rx_pkt_end_i &&
137 rx_pkt_valid_i &&
138 rx_pid_type == UsbPidTypeToken &&
139 rx_addr_i == dev_addr_i;
140
141 1/1 assign setup_token_received =
Tests: T1 T2 T3
142 token_received &&
143 rx_pid == UsbPidSetup;
144
145 1/1 assign in_token_received =
Tests: T1 T2 T3
146 token_received &&
147 rx_pid == UsbPidIn;
148
149 1/1 assign ack_received =
Tests: T1 T2 T3
150 rx_pkt_end_i &&
151 rx_pkt_valid_i &&
152 rx_pid == UsbPidAck;
153
154 1/1 assign nak_received =
Tests: T1 T2 T3
155 rx_pkt_end_i &&
156 rx_pkt_valid_i &&
157 rx_pid == UsbPidNak;
158
159 // Is the specified endpoint actually implemented in hardware?
160 1/1 assign ep_in_hw = {1'b0, rx_endp_i} < NumInEps;
Tests: T1 T2 T3
161 1/1 assign in_ep_current_d = ep_in_hw ? rx_endp_i : '0;
Tests: T1 T2 T3
162
163 // Make widths work - in_ep_current_d/in_ep_current_o only hold implemented endpoint IDs.
164 // These signals can be used to index signals of NumInEps width.
165 // They are only valid if ep_active is set, i.e., if the specified endpoint is implemented.
166 logic [InEpW-1:0] in_ep_index;
167 logic [InEpW-1:0] in_ep_index_d;
168 1/1 assign in_ep_index = in_ep_current_o[0 +: InEpW];
Tests: T1 T2 T3
169 1/1 assign in_ep_index_d = in_ep_current_d[0 +: InEpW];
Tests: T1 T2 T3
170
171 // Is the endpoint active?
172 1/1 assign ep_active = in_ep_enabled_i[in_ep_index_d] & ep_in_hw;
Tests: T1 T2 T3
173
174 // Retain whether the current IN transmission has associated data; an Isochronous transaction
175 // for which there was no packet data available must not raise a 'pkt_sent' interrupt.
176 logic has_data_q;
177
178 1/1 assign more_data_to_send = has_data_q & ~in_ep_data_done_i[in_ep_index];
Tests: T1 T2 T3
179
180 1/1 assign tx_data_avail_o = logic'(in_xact_state == StSendData) & more_data_to_send;
Tests: T1 T2 T3
181
182 ////////////////////////////////////////////////////////////////////////////////
183 // Transaction is starting on this IN endpoint; capture the packet details.
184 ////////////////////////////////////////////////////////////////////////////////
185 logic in_starting;
186 1/1 assign in_starting = (in_xact_state == StIdle || in_xact_state == StWaitAck) && in_token_received;
Tests: T1 T2 T3
187
188 1/1 assign in_xact_starting_o = in_starting & ep_active;
Tests: T1 T2 T3
189 1/1 assign in_xact_start_ep_o = in_ep_current_d;
Tests: T1 T2 T3
190
191 ////////////////////////////////////////////////////////////////////////////////
192 // in transaction state machine
193 ////////////////////////////////////////////////////////////////////////////////
194
195 logic [AckTimeoutCntW-1:0] timeout_cntdown_d, timeout_cntdown_q;
196 logic rollback_in_xact;
197
198 always_comb begin
199 1/1 in_xact_state_next = in_xact_state;
Tests: T1 T2 T3
200 1/1 in_xact_end = 1'b0;
Tests: T1 T2 T3
201 1/1 tx_pkt_start_o = 1'b0;
Tests: T1 T2 T3
202 1/1 tx_pid_o = 4'b0000;
Tests: T1 T2 T3
203 1/1 rollback_in_xact = 1'b0;
Tests: T1 T2 T3
204 1/1 timeout_cntdown_d = AckTimeoutCnt[AckTimeoutCntW-1:0];
Tests: T1 T2 T3
205 1/1 unique case (in_xact_state)
Tests: T1 T2 T3
206 StIdle: begin
207 1/1 if (ep_active && in_token_received) begin
Tests: T1 T2 T3
208 1/1 in_xact_state_next = StRcvdIn;
Tests: T18 T19 T26
209 end else begin
210 // Ignore tokens to inactive endpoints. Send no response.
211 1/1 in_xact_state_next = StIdle;
Tests: T1 T2 T3
212 end
213 end
214
215 StRcvdIn: begin
216 1/1 tx_pkt_start_o = 1'b1; // Need to transmit NAK/STALL or DATA
Tests: T18 T19 T26
217
218 1/1 if (in_ep_iso_i[in_ep_index]) begin
Tests: T18 T19 T26
219 // ISO endpoint
220 // We always need to transmit. When no data is available, we send
221 // a zero-length packet.
222 // DATA0 always for full-speed isochronous endpoints
223 1/1 in_xact_state_next = StSendData;
Tests: T32 T99 T86
224 1/1 tx_pid_o = {UsbPidData0};
Tests: T32 T99 T86
225 1/1 end else if (in_ep_stall_i[in_ep_index]) begin
Tests: T18 T19 T26
226 1/1 in_xact_state_next = StIdle;
Tests: T100 T60 T101
227 1/1 tx_pid_o = {UsbPidStall}; // STALL
Tests: T100 T60 T101
228 1/1 end else if (has_data_q) begin
Tests: T18 T19 T26
229 1/1 in_xact_state_next = StSendData;
Tests: T18 T19 T26
230 1/1 tx_pid_o = {data_toggle_q[in_ep_index], 1'b0, {UsbPidTypeData}}; // DATA0/1
Tests: T18 T19 T26
231 end else begin
232 1/1 in_xact_state_next = StIdle;
Tests: T4 T5 T6
233 1/1 tx_pid_o = {UsbPidNak}; // NAK
Tests: T4 T5 T6
234 end
235 end
236
237 StSendData: begin
238 // Use &in_ep_get_addr so width can vary, looking for all ones
239 1/1 if ((!more_data_to_send) || ((&in_ep_get_addr_o) && tx_data_get_i)) begin
Tests: T18 T19 T26
240 1/1 if (in_ep_iso_i[in_ep_index]) begin
Tests: T18 T19 T26
241 1/1 in_xact_state_next = StIdle; // no ACK for ISO EPs
Tests: T32 T99 T86
242 1/1 in_xact_end = has_data_q;
Tests: T32 T99 T86
243 end else begin
244 1/1 if (tx_pkt_end_i) begin
Tests: T18 T19 T26
245 0/1 ==> in_xact_state_next = StWaitAckStart;
246 end else begin
247 1/1 in_xact_state_next = StWaitTxEnd;
Tests: T18 T19 T26
248 end
249 end
250 end else begin
251 1/1 in_xact_state_next = StSendData;
Tests: T19 T26 T8
252 end
253 end
254
255 StWaitTxEnd: begin
256 1/1 if (tx_pkt_end_i) begin
Tests: T18 T19 T26
257 1/1 in_xact_state_next = StWaitAckStart;
Tests: T18 T19 T26
258 end
MISSING_ELSE
259 end
260
261 StWaitAckStart: begin
262 // The spec says we have up to 18 bit times to wait for the host
263 // response. If it doesn't arrive in time, we must invalidate the
264 // transaction.
265 1/1 timeout_cntdown_d = timeout_cntdown_q - 1'b1;
Tests: T18 T19 T26
266
267 1/1 if (rx_pkt_start_i) begin
Tests: T18 T19 T26
268 1/1 in_xact_state_next = StWaitAck;
Tests: T18 T19 T26
269 1/1 end else if (timeout_cntdown_q == '0) begin
Tests: T18 T19 T26
270 1/1 in_xact_state_next = StIdle;
Tests: T19 T29 T30
271 1/1 rollback_in_xact = 1'b1;
Tests: T19 T29 T30
272 end else begin
273 1/1 in_xact_state_next = StWaitAckStart;
Tests: T18 T19 T26
274 end
275 end
276
277 StWaitAck: begin
278 1/1 if (ack_received) begin
Tests: T18 T19 T26
279 1/1 in_xact_state_next = StIdle;
Tests: T18 T19 T26
280 1/1 in_xact_end = 1'b1;
Tests: T18 T19 T26
281 1/1 end else if (in_token_received) begin
Tests: T18 T19 T26
282 // Handshake response is missing.
283 0/1 ==> in_xact_state_next = ep_active ? StRcvdIn : StIdle;
284 0/1 ==> rollback_in_xact = 1'b1;
285 1/1 end else if (rx_pkt_end_i) begin
Tests: T18 T19 T26
286 // Includes NAK
287 1/1 in_xact_state_next = StIdle;
Tests: T19 T102 T103
288 1/1 rollback_in_xact = 1'b1;
Tests: T19 T102 T103
289 end else begin
290 1/1 in_xact_state_next = StWaitAck;
Tests: T18 T19 T26
291 end
292 end
293
294 default: in_xact_state_next = StIdle;
295 endcase
296 end
297
298 `ASSERT(InXactStateValid_A,
299 in_xact_state inside {StIdle, StRcvdIn, StSendData, StWaitTxEnd, StWaitAckStart, StWaitAck},
300 clk_48mhz_i)
301
302 always_ff @(posedge clk_48mhz_i or negedge rst_ni) begin
303 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
304 1/1 timeout_cntdown_q <= AckTimeoutCnt[AckTimeoutCntW-1:0];
Tests: T1 T2 T3
305 end else begin
306 1/1 timeout_cntdown_q <= timeout_cntdown_d;
Tests: T1 T2 T3
307 end
308 end
309
310 always_ff @(posedge clk_48mhz_i or negedge rst_ni) begin
311 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
312 1/1 tx_data_o <= '0;
Tests: T1 T2 T3
313 end else begin
314 1/1 tx_data_o <= in_ep_data_i;
Tests: T1 T2 T3
315 end
316 end
317
318 always_ff @(posedge clk_48mhz_i or negedge rst_ni) begin
319 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
320 1/1 in_xact_state <= StIdle;
Tests: T1 T2 T3
321 1/1 in_ep_rollback_o <= 1'b0;
Tests: T1 T2 T3
322 1/1 end else if (link_reset_i || !link_active_i) begin
Tests: T1 T2 T3
323 1/1 in_xact_state <= StIdle;
Tests: T1 T2 T3
324 1/1 in_ep_rollback_o <= 1'b0;
Tests: T1 T2 T3
325 end else begin
326 1/1 in_xact_state <= in_xact_state_next;
Tests: T1 T2 T3
327 1/1 in_ep_rollback_o <= rollback_in_xact;
Tests: T1 T2 T3
328 end
329 end
330
331 always_ff @(posedge clk_48mhz_i or negedge rst_ni) begin
332 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
333 1/1 in_ep_get_addr_o <= '0;
Tests: T1 T2 T3
334 end else begin
335 1/1 if (in_xact_state == StIdle) begin
Tests: T1 T2 T3
336 1/1 in_ep_get_addr_o <= '0;
Tests: T1 T2 T3
337 1/1 end else if ((in_xact_state == StSendData) && tx_data_get_i) begin
Tests: T18 T19 T26
338 1/1 in_ep_get_addr_o <= in_ep_get_addr_o + 1'b1;
Tests: T19 T26 T8
339 end
MISSING_ELSE
340 end
341 end
342
343 always_ff @(posedge clk_48mhz_i or negedge rst_ni) begin
344 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
345 1/1 in_ep_newpkt_o <= 1'b0;
Tests: T1 T2 T3
346 1/1 in_ep_current_o <= '0;
Tests: T1 T2 T3
347 1/1 has_data_q <= 1'b0;
Tests: T1 T2 T3
348 end else begin
349 1/1 if (in_token_received) begin
Tests: T1 T2 T3
350 1/1 in_ep_current_o <= in_ep_current_d;
Tests: T18 T19 T26
351 1/1 in_ep_newpkt_o <= 1'b1;
Tests: T18 T19 T26
352 1/1 has_data_q <= in_ep_has_data_i[in_ep_index_d];
Tests: T18 T19 T26
353 end else begin
354 1/1 in_ep_newpkt_o <= 1'b0;
Tests: T1 T2 T3
355 end
356 end
357 end
358
359 // Updating of data toggles
360 always_comb begin : proc_data_toggle_d
361 1/1 data_toggle_d = data_toggle_q;
Tests: T1 T2 T3
362
363 1/1 if (setup_token_received && ep_active) begin
Tests: T1 T2 T3
364 1/1 data_toggle_d[in_ep_index_d] = 1'b1;
Tests: T5 T60 T83
365 1/1 end else if ((in_xact_state == StWaitAck) && ack_received) begin
Tests: T1 T2 T3
366 1/1 data_toggle_d[in_ep_index] = ~data_toggle_q[in_ep_index];
Tests: T18 T19 T26
367 end
MISSING_ELSE
368 // Selective modification by software
369 1/1 if (in_datatog_we_i) begin
Tests: T1 T2 T3
370 1/1 data_toggle_d = (data_toggle_d & ~in_datatog_mask_i) |
Tests: T18 T19 T104
371 (in_datatog_status_i & in_datatog_mask_i);
372 end
MISSING_ELSE
373 end
374 // Supply current data toggles to register interface
375 1/1 assign in_data_toggle_o = data_toggle_q;
Tests: T1 T2 T3
376
377 always_ff @(posedge clk_48mhz_i or negedge rst_ni) begin
378 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
379 1/1 data_toggle_q <= '0; // Clear for all endpoints
Tests: T1 T2 T3
380 1/1 end else if (link_reset_i) begin
Tests: T1 T2 T3
381 1/1 data_toggle_q <= '0; // Clear for all endpoints
Tests: T1 T2 T3
382 end else begin
383 1/1 data_toggle_q <= data_toggle_d;
Tests: T1 T2 T3
384 end
385 end
386
387 always_ff @(posedge clk_48mhz_i or negedge rst_ni) begin
388 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
389 1/1 in_ep_data_get_o <= 1'b0;
Tests: T1 T2 T3
390 end else begin
391 1/1 if ((in_xact_state == StSendData) && tx_data_get_i) begin
Tests: T1 T2 T3
392 1/1 in_ep_data_get_o <= 1'b1;
Tests: T19 T26 T8
393 end else begin
394 1/1 in_ep_data_get_o <= 1'b0;
Tests: T1 T2 T3
395 end
396 end
397 end
398
399 ////////////////////////////////////////////////////////////////////////////////
400 // Count non-Isochronous IN transactions not receiving a handshake response.
401 //
402 // - no handshake response within the timeout period
403 // - packet reception started within the timeout period but it was not ACK/NAK.
404 ////////////////////////////////////////////////////////////////////////////////
405 1/1 assign event_timeout_in_o = (in_xact_state == StWaitAckStart ||
Tests: T1 T2 T3
406 (in_xact_state == StWaitAck && rx_pkt_end_i && !nak_received))
407 & rollback_in_xact;
408
409 ////////////////////////////////////////////////////////////////////////////////
410 // Count IN transactions that are actively NAKed by the host.
411 ////////////////////////////////////////////////////////////////////////////////
412 1/1 assign event_nak_in_o = (in_xact_state == StWaitAck) && nak_received;
Tests: T1 T2 T3
413
414 ////////////////////////////////////////////////////////////////////////////////
415 // Count the number of IN requests for which data is not available, including
416 // endpoints which are supported but not presently enabled/configured.
417 // (These may be ignored using the event counter configuration if required.)
418 ////////////////////////////////////////////////////////////////////////////////
419 logic event_nodata_in_q;
420 // This event signal must be delayed by a single cycle so that 'in_ep_current_o' becomes valid.
421 always_ff @(posedge clk_48mhz_i or negedge rst_ni) begin
422 2/2 if (!rst_ni) event_nodata_in_q <= 1'b0;
Tests: T1 T2 T3 | T1 T2 T3
423 1/1 else event_nodata_in_q <= in_starting & (ep_in_hw ? !in_ep_has_data_i[in_ep_index_d] : 1'b0);
Tests: T1 T2 T3
424 end
425 1/1 assign event_nodata_in_o = event_nodata_in_q;
Tests: T1 T2 T3
Cond Coverage for Module :
usb_fs_nb_in_pe
| Total | Covered | Percent |
|---|
| Conditions | 115 | 109 | 94.78 |
| Logical | 115 | 109 | 94.78 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 135
EXPRESSION (rx_pkt_end_i && rx_pkt_valid_i && (rx_pid_type == UsbPidTypeToken) && (rx_addr_i == dev_addr_i))
------1----- -------2------ ----------------3--------------- ------------4------------
| -1- | -2- | -3- | -4- | Status | Tests |
|---|
| 0 | 1 | 1 | 1 | Covered | T2,T3,T18 |
| 1 | 0 | 1 | 1 | Covered | T71,T72,T69 |
| 1 | 1 | 0 | 1 | Covered | T2,T3,T18 |
| 1 | 1 | 1 | 0 | Covered | T17,T20,T21 |
| 1 | 1 | 1 | 1 | Covered | T2,T3,T18 |
LINE 135
SUB-EXPRESSION (rx_pid_type == UsbPidTypeToken)
----------------1---------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T17 |
LINE 135
SUB-EXPRESSION (rx_addr_i == dev_addr_i)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 141
EXPRESSION (token_received && (rx_pid == UsbPidSetup))
-------1------ -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T21,T80,T27 |
| 1 | 0 | Covered | T2,T3,T18 |
| 1 | 1 | Covered | T27,T28,T5 |
LINE 141
SUB-EXPRESSION (rx_pid == UsbPidSetup)
-----------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T21,T80,T27 |
LINE 145
EXPRESSION (token_received && (rx_pid == UsbPidIn))
-------1------ ----------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T18,T19,T21 |
| 1 | 0 | Covered | T2,T3,T18 |
| 1 | 1 | Covered | T18,T19,T26 |
LINE 145
SUB-EXPRESSION (rx_pid == UsbPidIn)
----------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T18,T19,T21 |
LINE 149
EXPRESSION (rx_pkt_end_i && rx_pkt_valid_i && (rx_pid == UsbPidAck))
------1----- -------2------ ----------3----------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T18,T19,T26 |
| 1 | 0 | 1 | Covered | T72,T76,T105 |
| 1 | 1 | 0 | Covered | T2,T3,T17 |
| 1 | 1 | 1 | Covered | T18,T19,T26 |
LINE 149
SUB-EXPRESSION (rx_pid == UsbPidAck)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T18,T19,T21 |
LINE 154
EXPRESSION (rx_pkt_end_i && rx_pkt_valid_i && (rx_pid == UsbPidNak))
------1----- -------2------ ----------3----------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T19,T102,T103 |
| 1 | 0 | 1 | Covered | T72,T106,T107 |
| 1 | 1 | 0 | Covered | T2,T3,T17 |
| 1 | 1 | 1 | Covered | T19,T103,T108 |
LINE 154
SUB-EXPRESSION (rx_pid == UsbPidNak)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T18,T19,T26 |
LINE 161
EXPRESSION (ep_in_hw ? rx_endp_i : '0)
----1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T80,T8,T4 |
| 1 | Covered | T1,T2,T3 |
LINE 172
EXPRESSION (in_ep_enabled_i[in_ep_index_d] & ep_in_hw)
---------------1-------------- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T4,T60,T109 |
| 1 | 1 | Covered | T18,T19,T21 |
LINE 178
EXPRESSION (has_data_q & ((~in_ep_data_done_i[in_ep_index])))
-----1---- -----------------2-----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T60,T86,T110 |
| 1 | 0 | Covered | T18,T19,T26 |
| 1 | 1 | Covered | T19,T26,T8 |
LINE 180
EXPRESSION ((logic'((in_xact_state == StSendData))) & more_data_to_send)
-------------------1------------------- --------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T19,T26,T8 |
| 1 | 0 | Covered | T18,T19,T26 |
| 1 | 1 | Covered | T19,T26,T8 |
LINE 186
EXPRESSION (((in_xact_state == StIdle) || (in_xact_state == StWaitAck)) && in_token_received)
-----------------------------1----------------------------- --------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T18,T19,T26 |
LINE 186
SUB-EXPRESSION ((in_xact_state == StIdle) || (in_xact_state == StWaitAck))
------------1------------ --------------2-------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T18,T19,T26 |
| 0 | 1 | Covered | T18,T19,T26 |
| 1 | 0 | Covered | T1,T2,T3 |
LINE 186
SUB-EXPRESSION (in_xact_state == StIdle)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 186
SUB-EXPRESSION (in_xact_state == StWaitAck)
--------------1-------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T18,T19,T26 |
LINE 188
EXPRESSION (in_starting & ep_active)
-----1----- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T18,T19,T21 |
| 1 | 0 | Covered | T60,T110,T111 |
| 1 | 1 | Covered | T18,T19,T26 |
LINE 207
EXPRESSION (ep_active && in_token_received)
----1---- --------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T60,T110,T111 |
| 1 | 0 | Covered | T18,T19,T21 |
| 1 | 1 | Covered | T18,T19,T26 |
LINE 239
EXPRESSION (((!more_data_to_send)) || (((&in_ep_get_addr_o)) && tx_data_get_i))
-----------1---------- --------------------2-------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T19,T26,T8 |
| 0 | 1 | Covered | T112,T5,T113 |
| 1 | 0 | Covered | T18,T19,T26 |
LINE 239
SUB-EXPRESSION (((&in_ep_get_addr_o)) && tx_data_get_i)
----------1---------- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T19,T26,T8 |
| 1 | 0 | Covered | T112,T5,T113 |
| 1 | 1 | Covered | T112,T5,T113 |
LINE 269
EXPRESSION (timeout_cntdown_q == '0)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T18,T19,T26 |
| 1 | Covered | T19,T29,T30 |
LINE 283
EXPRESSION (ep_active ? StRcvdIn : StIdle)
----1----
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Not Covered | |
LINE 322
EXPRESSION (link_reset_i || ((!link_active_i)))
------1----- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
LINE 335
EXPRESSION (in_xact_state == StIdle)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T18,T19,T26 |
| 1 | Covered | T1,T2,T3 |
LINE 337
EXPRESSION ((in_xact_state == StSendData) && tx_data_get_i)
--------------1-------------- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T18,T19,T26 |
| 1 | 1 | Covered | T19,T26,T8 |
LINE 337
SUB-EXPRESSION (in_xact_state == StSendData)
--------------1--------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T18,T19,T26 |
| 1 | Covered | T18,T19,T26 |
LINE 363
EXPRESSION (setup_token_received && ep_active)
----------1--------- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T18,T19,T21 |
| 1 | 0 | Covered | T27,T28,T60 |
| 1 | 1 | Covered | T5,T60,T83 |
LINE 365
EXPRESSION ((in_xact_state == StWaitAck) && ack_received)
--------------1------------- ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T18,T19,T26 |
| 1 | 1 | Covered | T18,T19,T26 |
LINE 365
SUB-EXPRESSION (in_xact_state == StWaitAck)
--------------1-------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T18,T19,T26 |
LINE 391
EXPRESSION ((in_xact_state == StSendData) && tx_data_get_i)
--------------1-------------- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T114 |
| 1 | 0 | Covered | T18,T19,T26 |
| 1 | 1 | Covered | T19,T26,T8 |
LINE 391
SUB-EXPRESSION (in_xact_state == StSendData)
--------------1--------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T18,T19,T26 |
LINE 405
EXPRESSION (((in_xact_state == StWaitAckStart) || ((in_xact_state == StWaitAck) && rx_pkt_end_i && ((!nak_received)))) & rollback_in_xact)
-----------------------------------------------------1---------------------------------------------------- --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T19,T103,T108 |
| 1 | 0 | Covered | T18,T19,T26 |
| 1 | 1 | Covered | T19,T29,T30 |
LINE 405
SUB-EXPRESSION ((in_xact_state == StWaitAckStart) || ((in_xact_state == StWaitAck) && rx_pkt_end_i && ((!nak_received))))
----------------1---------------- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T18,T19,T26 |
| 1 | 0 | Covered | T18,T19,T26 |
LINE 405
SUB-EXPRESSION (in_xact_state == StWaitAckStart)
----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T18,T19,T26 |
LINE 405
SUB-EXPRESSION ((in_xact_state == StWaitAck) && rx_pkt_end_i && ((!nak_received)))
--------------1------------- ------2----- --------3--------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T2,T3,T17 |
| 1 | 0 | 1 | Covered | T18,T19,T26 |
| 1 | 1 | 0 | Covered | T19,T103,T108 |
| 1 | 1 | 1 | Covered | T18,T19,T26 |
LINE 405
SUB-EXPRESSION (in_xact_state == StWaitAck)
--------------1-------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T18,T19,T26 |
LINE 412
EXPRESSION ((in_xact_state == StWaitAck) && nak_received)
--------------1------------- ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T18,T19,T26 |
| 1 | 1 | Covered | T19,T103,T108 |
LINE 412
SUB-EXPRESSION (in_xact_state == StWaitAck)
--------------1-------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T18,T19,T26 |
LINE 423
EXPRESSION (in_starting & (ep_in_hw ? ((!in_ep_has_data_i[in_ep_index_d])) : 1'b0))
-----1----- ----------------------------2---------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T18,T19,T26 |
| 1 | 1 | Covered | T4,T5,T6 |
LINE 423
SUB-EXPRESSION (ep_in_hw ? ((!in_ep_has_data_i[in_ep_index_d])) : 1'b0)
----1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T80,T8,T4 |
| 1 | Covered | T1,T2,T3 |
FSM Coverage for Module :
usb_fs_nb_in_pe
Summary for FSM :: in_xact_state
| Total | Covered | Percent | |
| States |
6 |
6 |
100.00 |
(Not included in score) |
| Transitions |
12 |
10 |
83.33 |
|
| Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: in_xact_state
| states | Line No. | Covered | Tests |
| StIdle |
323 |
Covered |
T1,T2,T3 |
| StRcvdIn |
208 |
Covered |
T18,T19,T26 |
| StSendData |
223 |
Covered |
T18,T19,T26 |
| StWaitAck |
268 |
Covered |
T18,T19,T26 |
| StWaitAckStart |
245 |
Covered |
T18,T19,T26 |
| StWaitTxEnd |
247 |
Covered |
T18,T19,T26 |
| transitions | Line No. | Covered | Tests |
| StIdle->StRcvdIn |
208 |
Covered |
T18,T19,T26 |
| StRcvdIn->StIdle |
323 |
Covered |
T100,T4,T5 |
| StRcvdIn->StSendData |
223 |
Covered |
T18,T19,T26 |
| StSendData->StIdle |
323 |
Covered |
T32,T99,T86 |
| StSendData->StWaitAckStart |
245 |
Not Covered |
|
| StSendData->StWaitTxEnd |
247 |
Covered |
T18,T19,T26 |
| StWaitAck->StIdle |
323 |
Covered |
T18,T19,T26 |
| StWaitAck->StRcvdIn |
283 |
Not Covered |
|
| StWaitAckStart->StIdle |
323 |
Covered |
T19,T29,T30 |
| StWaitAckStart->StWaitAck |
268 |
Covered |
T18,T19,T26 |
| StWaitTxEnd->StIdle |
323 |
Covered |
T115,T116,T117 |
| StWaitTxEnd->StWaitAckStart |
257 |
Covered |
T18,T19,T26 |
Branch Coverage for Module :
usb_fs_nb_in_pe
| Line No. | Total | Covered | Percent |
| Branches |
|
50 |
46 |
92.00 |
| TERNARY |
161 |
2 |
2 |
100.00 |
| CASE |
205 |
21 |
17 |
80.95 |
| IF |
303 |
2 |
2 |
100.00 |
| IF |
311 |
2 |
2 |
100.00 |
| IF |
319 |
3 |
3 |
100.00 |
| IF |
332 |
4 |
4 |
100.00 |
| IF |
344 |
3 |
3 |
100.00 |
| IF |
363 |
3 |
3 |
100.00 |
| IF |
369 |
2 |
2 |
100.00 |
| IF |
378 |
3 |
3 |
100.00 |
| IF |
388 |
3 |
3 |
100.00 |
| IF |
422 |
2 |
2 |
100.00 |
161 assign in_ep_current_d = ep_in_hw ? rx_endp_i : '0;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T80,T8,T4 |
205 unique case (in_xact_state)
-1-
206 StIdle: begin
207 if (ep_active && in_token_received) begin
-2-
208 in_xact_state_next = StRcvdIn;
==>
209 end else begin
210 // Ignore tokens to inactive endpoints. Send no response.
211 in_xact_state_next = StIdle;
==>
212 end
213 end
214
215 StRcvdIn: begin
216 tx_pkt_start_o = 1'b1; // Need to transmit NAK/STALL or DATA
217
218 if (in_ep_iso_i[in_ep_index]) begin
-3-
219 // ISO endpoint
220 // We always need to transmit. When no data is available, we send
221 // a zero-length packet.
222 // DATA0 always for full-speed isochronous endpoints
223 in_xact_state_next = StSendData;
==>
224 tx_pid_o = {UsbPidData0};
225 end else if (in_ep_stall_i[in_ep_index]) begin
-4-
226 in_xact_state_next = StIdle;
==>
227 tx_pid_o = {UsbPidStall}; // STALL
228 end else if (has_data_q) begin
-5-
229 in_xact_state_next = StSendData;
==>
230 tx_pid_o = {data_toggle_q[in_ep_index], 1'b0, {UsbPidTypeData}}; // DATA0/1
231 end else begin
232 in_xact_state_next = StIdle;
==>
233 tx_pid_o = {UsbPidNak}; // NAK
234 end
235 end
236
237 StSendData: begin
238 // Use &in_ep_get_addr so width can vary, looking for all ones
239 if ((!more_data_to_send) || ((&in_ep_get_addr_o) && tx_data_get_i)) begin
-6-
240 if (in_ep_iso_i[in_ep_index]) begin
-7-
241 in_xact_state_next = StIdle; // no ACK for ISO EPs
==>
242 in_xact_end = has_data_q;
243 end else begin
244 if (tx_pkt_end_i) begin
-8-
245 in_xact_state_next = StWaitAckStart;
==>
246 end else begin
247 in_xact_state_next = StWaitTxEnd;
==>
248 end
249 end
250 end else begin
251 in_xact_state_next = StSendData;
==>
252 end
253 end
254
255 StWaitTxEnd: begin
256 if (tx_pkt_end_i) begin
-9-
257 in_xact_state_next = StWaitAckStart;
==>
258 end
MISSING_ELSE
==>
259 end
260
261 StWaitAckStart: begin
262 // The spec says we have up to 18 bit times to wait for the host
263 // response. If it doesn't arrive in time, we must invalidate the
264 // transaction.
265 timeout_cntdown_d = timeout_cntdown_q - 1'b1;
266
267 if (rx_pkt_start_i) begin
-10-
268 in_xact_state_next = StWaitAck;
==>
269 end else if (timeout_cntdown_q == '0) begin
-11-
270 in_xact_state_next = StIdle;
==>
271 rollback_in_xact = 1'b1;
272 end else begin
273 in_xact_state_next = StWaitAckStart;
==>
274 end
275 end
276
277 StWaitAck: begin
278 if (ack_received) begin
-12-
279 in_xact_state_next = StIdle;
==>
280 in_xact_end = 1'b1;
281 end else if (in_token_received) begin
-13-
282 // Handshake response is missing.
283 in_xact_state_next = ep_active ? StRcvdIn : StIdle;
-14-
==>
==>
284 rollback_in_xact = 1'b1;
285 end else if (rx_pkt_end_i) begin
-15-
286 // Includes NAK
287 in_xact_state_next = StIdle;
==>
288 rollback_in_xact = 1'b1;
289 end else begin
290 in_xact_state_next = StWaitAck;
==>
291 end
292 end
293
294 default: in_xact_state_next = StIdle;
==>
Branches:
| -1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | -9- | -10- | -11- | -12- | -13- | -14- | -15- | Status | Tests |
| StIdle |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T18,T19,T26 |
| StIdle |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| StRcvdIn |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T32,T99,T86 |
| StRcvdIn |
- |
0 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T100,T60,T101 |
| StRcvdIn |
- |
0 |
0 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T18,T19,T26 |
| StRcvdIn |
- |
0 |
0 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T4,T5,T6 |
| StSendData |
- |
- |
- |
- |
1 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T32,T99,T86 |
| StSendData |
- |
- |
- |
- |
1 |
0 |
1 |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
| StSendData |
- |
- |
- |
- |
1 |
0 |
0 |
- |
- |
- |
- |
- |
- |
- |
Covered |
T18,T19,T26 |
| StSendData |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T19,T26,T8 |
| StWaitTxEnd |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T18,T19,T26 |
| StWaitTxEnd |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
Covered |
T18,T19,T26 |
| StWaitAckStart |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
Covered |
T18,T19,T26 |
| StWaitAckStart |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
1 |
- |
- |
- |
- |
Covered |
T19,T29,T30 |
| StWaitAckStart |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
- |
- |
- |
- |
Covered |
T18,T19,T26 |
| StWaitAck |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
Covered |
T18,T19,T26 |
| StWaitAck |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
1 |
1 |
- |
Not Covered |
|
| StWaitAck |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
1 |
0 |
- |
Not Covered |
|
| StWaitAck |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
- |
1 |
Covered |
T19,T102,T103 |
| StWaitAck |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
- |
0 |
Covered |
T18,T19,T26 |
| default |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
303 if (!rst_ni) begin
-1-
304 timeout_cntdown_q <= AckTimeoutCnt[AckTimeoutCntW-1:0];
==>
305 end else begin
306 timeout_cntdown_q <= timeout_cntdown_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
311 if (!rst_ni) begin
-1-
312 tx_data_o <= '0;
==>
313 end else begin
314 tx_data_o <= in_ep_data_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
319 if (!rst_ni) begin
-1-
320 in_xact_state <= StIdle;
==>
321 in_ep_rollback_o <= 1'b0;
322 end else if (link_reset_i || !link_active_i) begin
-2-
323 in_xact_state <= StIdle;
==>
324 in_ep_rollback_o <= 1'b0;
325 end else begin
326 in_xact_state <= in_xact_state_next;
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
332 if (!rst_ni) begin
-1-
333 in_ep_get_addr_o <= '0;
==>
334 end else begin
335 if (in_xact_state == StIdle) begin
-2-
336 in_ep_get_addr_o <= '0;
==>
337 end else if ((in_xact_state == StSendData) && tx_data_get_i) begin
-3-
338 in_ep_get_addr_o <= in_ep_get_addr_o + 1'b1;
==>
339 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T1,T2,T3 |
| 0 |
0 |
1 |
Covered |
T19,T26,T8 |
| 0 |
0 |
0 |
Covered |
T18,T19,T26 |
344 if (!rst_ni) begin
-1-
345 in_ep_newpkt_o <= 1'b0;
==>
346 in_ep_current_o <= '0;
347 has_data_q <= 1'b0;
348 end else begin
349 if (in_token_received) begin
-2-
350 in_ep_current_o <= in_ep_current_d;
==>
351 in_ep_newpkt_o <= 1'b1;
352 has_data_q <= in_ep_has_data_i[in_ep_index_d];
353 end else begin
354 in_ep_newpkt_o <= 1'b0;
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T18,T19,T26 |
| 0 |
0 |
Covered |
T1,T2,T3 |
363 if (setup_token_received && ep_active) begin
-1-
364 data_toggle_d[in_ep_index_d] = 1'b1;
==>
365 end else if ((in_xact_state == StWaitAck) && ack_received) begin
-2-
366 data_toggle_d[in_ep_index] = ~data_toggle_q[in_ep_index];
==>
367 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T5,T60,T83 |
| 0 |
1 |
Covered |
T18,T19,T26 |
| 0 |
0 |
Covered |
T1,T2,T3 |
369 if (in_datatog_we_i) begin
-1-
370 data_toggle_d = (data_toggle_d & ~in_datatog_mask_i) |
==>
371 (in_datatog_status_i & in_datatog_mask_i);
372 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T18,T19,T104 |
| 0 |
Covered |
T1,T2,T3 |
378 if (!rst_ni) begin
-1-
379 data_toggle_q <= '0; // Clear for all endpoints
==>
380 end else if (link_reset_i) begin
-2-
381 data_toggle_q <= '0; // Clear for all endpoints
==>
382 end else begin
383 data_toggle_q <= data_toggle_d;
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
388 if (!rst_ni) begin
-1-
389 in_ep_data_get_o <= 1'b0;
==>
390 end else begin
391 if ((in_xact_state == StSendData) && tx_data_get_i) begin
-2-
392 in_ep_data_get_o <= 1'b1;
==>
393 end else begin
394 in_ep_data_get_o <= 1'b0;
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T19,T26,T8 |
| 0 |
0 |
Covered |
T1,T2,T3 |
422 if (!rst_ni) event_nodata_in_q <= 1'b0;
-1-
==>
423 else event_nodata_in_q <= in_starting & (ep_in_hw ? !in_ep_has_data_i[in_ep_index_d] : 1'b0);
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
usb_fs_nb_in_pe
Assertion Details
InXactStateValid_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
584743025 |
584444689 |
0 |
0 |
| T1 |
200035 |
199940 |
0 |
0 |
| T2 |
8838 |
8758 |
0 |
0 |
| T3 |
9382 |
9283 |
0 |
0 |
| T7 |
701361 |
701279 |
0 |
0 |
| T16 |
8019 |
7966 |
0 |
0 |
| T17 |
7604 |
7521 |
0 |
0 |
| T18 |
9070 |
9002 |
0 |
0 |
| T19 |
34405 |
34355 |
0 |
0 |
| T20 |
8875 |
8787 |
0 |
0 |
| T21 |
17497 |
17427 |
0 |
0 |
Line Coverage for Instance : tb.dut.usbdev_impl.u_usb_fs_nb_pe.u_usb_fs_nb_in_pe
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 119 | 117 | 98.32 |
| CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 132 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 141 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 149 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 154 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 169 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 172 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 178 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 186 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 188 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 189 | 1 | 1 | 100.00 |
| ALWAYS | 199 | 48 | 46 | 95.83 |
| ALWAYS | 303 | 3 | 3 | 100.00 |
| ALWAYS | 311 | 3 | 3 | 100.00 |
| ALWAYS | 319 | 8 | 8 | 100.00 |
| ALWAYS | 332 | 6 | 6 | 100.00 |
| ALWAYS | 344 | 9 | 9 | 100.00 |
| ALWAYS | 361 | 7 | 7 | 100.00 |
| CONT_ASSIGN | 375 | 1 | 1 | 100.00 |
| ALWAYS | 378 | 5 | 5 | 100.00 |
| ALWAYS | 388 | 5 | 5 | 100.00 |
| CONT_ASSIGN | 405 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 412 | 1 | 1 | 100.00 |
| ALWAYS | 422 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 425 | 1 | 1 | 100.00 |
117
118 1/1 assign in_ep_xact_end_o = in_xact_end;
Tests: T1 T2 T3
119
120 // data toggle state
121 logic [NumInEps-1:0] data_toggle_q, data_toggle_d;
122
123 // endpoint data buffer
124 logic token_received, setup_token_received, in_token_received, ack_received, nak_received;
125 logic more_data_to_send;
126 logic ep_in_hw, ep_active;
127 logic [3:0] in_ep_current_d;
128
129 // More syntax so can compare with enum
130 usb_pid_type_e rx_pid_type;
131 usb_pid_e rx_pid;
132 1/1 assign rx_pid_type = usb_pid_type_e'(rx_pid_i[1:0]);
Tests: T1 T2 T3
133 1/1 assign rx_pid = usb_pid_e'(rx_pid_i);
Tests: T1 T2 T3
134
135 1/1 assign token_received =
Tests: T1 T2 T3
136 rx_pkt_end_i &&
137 rx_pkt_valid_i &&
138 rx_pid_type == UsbPidTypeToken &&
139 rx_addr_i == dev_addr_i;
140
141 1/1 assign setup_token_received =
Tests: T1 T2 T3
142 token_received &&
143 rx_pid == UsbPidSetup;
144
145 1/1 assign in_token_received =
Tests: T1 T2 T3
146 token_received &&
147 rx_pid == UsbPidIn;
148
149 1/1 assign ack_received =
Tests: T1 T2 T3
150 rx_pkt_end_i &&
151 rx_pkt_valid_i &&
152 rx_pid == UsbPidAck;
153
154 1/1 assign nak_received =
Tests: T1 T2 T3
155 rx_pkt_end_i &&
156 rx_pkt_valid_i &&
157 rx_pid == UsbPidNak;
158
159 // Is the specified endpoint actually implemented in hardware?
160 1/1 assign ep_in_hw = {1'b0, rx_endp_i} < NumInEps;
Tests: T1 T2 T3
161 1/1 assign in_ep_current_d = ep_in_hw ? rx_endp_i : '0;
Tests: T1 T2 T3
162
163 // Make widths work - in_ep_current_d/in_ep_current_o only hold implemented endpoint IDs.
164 // These signals can be used to index signals of NumInEps width.
165 // They are only valid if ep_active is set, i.e., if the specified endpoint is implemented.
166 logic [InEpW-1:0] in_ep_index;
167 logic [InEpW-1:0] in_ep_index_d;
168 1/1 assign in_ep_index = in_ep_current_o[0 +: InEpW];
Tests: T1 T2 T3
169 1/1 assign in_ep_index_d = in_ep_current_d[0 +: InEpW];
Tests: T1 T2 T3
170
171 // Is the endpoint active?
172 1/1 assign ep_active = in_ep_enabled_i[in_ep_index_d] & ep_in_hw;
Tests: T1 T2 T3
173
174 // Retain whether the current IN transmission has associated data; an Isochronous transaction
175 // for which there was no packet data available must not raise a 'pkt_sent' interrupt.
176 logic has_data_q;
177
178 1/1 assign more_data_to_send = has_data_q & ~in_ep_data_done_i[in_ep_index];
Tests: T1 T2 T3
179
180 1/1 assign tx_data_avail_o = logic'(in_xact_state == StSendData) & more_data_to_send;
Tests: T1 T2 T3
181
182 ////////////////////////////////////////////////////////////////////////////////
183 // Transaction is starting on this IN endpoint; capture the packet details.
184 ////////////////////////////////////////////////////////////////////////////////
185 logic in_starting;
186 1/1 assign in_starting = (in_xact_state == StIdle || in_xact_state == StWaitAck) && in_token_received;
Tests: T1 T2 T3
187
188 1/1 assign in_xact_starting_o = in_starting & ep_active;
Tests: T1 T2 T3
189 1/1 assign in_xact_start_ep_o = in_ep_current_d;
Tests: T1 T2 T3
190
191 ////////////////////////////////////////////////////////////////////////////////
192 // in transaction state machine
193 ////////////////////////////////////////////////////////////////////////////////
194
195 logic [AckTimeoutCntW-1:0] timeout_cntdown_d, timeout_cntdown_q;
196 logic rollback_in_xact;
197
198 always_comb begin
199 1/1 in_xact_state_next = in_xact_state;
Tests: T1 T2 T3
200 1/1 in_xact_end = 1'b0;
Tests: T1 T2 T3
201 1/1 tx_pkt_start_o = 1'b0;
Tests: T1 T2 T3
202 1/1 tx_pid_o = 4'b0000;
Tests: T1 T2 T3
203 1/1 rollback_in_xact = 1'b0;
Tests: T1 T2 T3
204 1/1 timeout_cntdown_d = AckTimeoutCnt[AckTimeoutCntW-1:0];
Tests: T1 T2 T3
205 1/1 unique case (in_xact_state)
Tests: T1 T2 T3
206 StIdle: begin
207 1/1 if (ep_active && in_token_received) begin
Tests: T1 T2 T3
208 1/1 in_xact_state_next = StRcvdIn;
Tests: T18 T19 T26
209 end else begin
210 // Ignore tokens to inactive endpoints. Send no response.
211 1/1 in_xact_state_next = StIdle;
Tests: T1 T2 T3
212 end
213 end
214
215 StRcvdIn: begin
216 1/1 tx_pkt_start_o = 1'b1; // Need to transmit NAK/STALL or DATA
Tests: T18 T19 T26
217
218 1/1 if (in_ep_iso_i[in_ep_index]) begin
Tests: T18 T19 T26
219 // ISO endpoint
220 // We always need to transmit. When no data is available, we send
221 // a zero-length packet.
222 // DATA0 always for full-speed isochronous endpoints
223 1/1 in_xact_state_next = StSendData;
Tests: T32 T99 T86
224 1/1 tx_pid_o = {UsbPidData0};
Tests: T32 T99 T86
225 1/1 end else if (in_ep_stall_i[in_ep_index]) begin
Tests: T18 T19 T26
226 1/1 in_xact_state_next = StIdle;
Tests: T100 T60 T101
227 1/1 tx_pid_o = {UsbPidStall}; // STALL
Tests: T100 T60 T101
228 1/1 end else if (has_data_q) begin
Tests: T18 T19 T26
229 1/1 in_xact_state_next = StSendData;
Tests: T18 T19 T26
230 1/1 tx_pid_o = {data_toggle_q[in_ep_index], 1'b0, {UsbPidTypeData}}; // DATA0/1
Tests: T18 T19 T26
231 end else begin
232 1/1 in_xact_state_next = StIdle;
Tests: T4 T5 T6
233 1/1 tx_pid_o = {UsbPidNak}; // NAK
Tests: T4 T5 T6
234 end
235 end
236
237 StSendData: begin
238 // Use &in_ep_get_addr so width can vary, looking for all ones
239 1/1 if ((!more_data_to_send) || ((&in_ep_get_addr_o) && tx_data_get_i)) begin
Tests: T18 T19 T26
240 1/1 if (in_ep_iso_i[in_ep_index]) begin
Tests: T18 T19 T26
241 1/1 in_xact_state_next = StIdle; // no ACK for ISO EPs
Tests: T32 T99 T86
242 1/1 in_xact_end = has_data_q;
Tests: T32 T99 T86
243 end else begin
244 1/1 if (tx_pkt_end_i) begin
Tests: T18 T19 T26
245 excluded in_xact_state_next = StWaitAckStart;
Exclude Annotation: VC_COV_UNR
246 end else begin
247 1/1 in_xact_state_next = StWaitTxEnd;
Tests: T18 T19 T26
248 end
249 end
250 end else begin
251 1/1 in_xact_state_next = StSendData;
Tests: T19 T26 T8
252 end
253 end
254
255 StWaitTxEnd: begin
256 1/1 if (tx_pkt_end_i) begin
Tests: T18 T19 T26
257 1/1 in_xact_state_next = StWaitAckStart;
Tests: T18 T19 T26
258 end
MISSING_ELSE
259 end
260
261 StWaitAckStart: begin
262 // The spec says we have up to 18 bit times to wait for the host
263 // response. If it doesn't arrive in time, we must invalidate the
264 // transaction.
265 1/1 timeout_cntdown_d = timeout_cntdown_q - 1'b1;
Tests: T18 T19 T26
266
267 1/1 if (rx_pkt_start_i) begin
Tests: T18 T19 T26
268 1/1 in_xact_state_next = StWaitAck;
Tests: T18 T19 T26
269 1/1 end else if (timeout_cntdown_q == '0) begin
Tests: T18 T19 T26
270 1/1 in_xact_state_next = StIdle;
Tests: T19 T29 T30
271 1/1 rollback_in_xact = 1'b1;
Tests: T19 T29 T30
272 end else begin
273 1/1 in_xact_state_next = StWaitAckStart;
Tests: T18 T19 T26
274 end
275 end
276
277 StWaitAck: begin
278 1/1 if (ack_received) begin
Tests: T18 T19 T26
279 1/1 in_xact_state_next = StIdle;
Tests: T18 T19 T26
280 1/1 in_xact_end = 1'b1;
Tests: T18 T19 T26
281 1/1 end else if (in_token_received) begin
Tests: T18 T19 T26
282 // Handshake response is missing.
283 0/1 ==> in_xact_state_next = ep_active ? StRcvdIn : StIdle;
284 0/1 ==> rollback_in_xact = 1'b1;
285 1/1 end else if (rx_pkt_end_i) begin
Tests: T18 T19 T26
286 // Includes NAK
287 1/1 in_xact_state_next = StIdle;
Tests: T19 T102 T103
288 1/1 rollback_in_xact = 1'b1;
Tests: T19 T102 T103
289 end else begin
290 1/1 in_xact_state_next = StWaitAck;
Tests: T18 T19 T26
291 end
292 end
293
294 default: in_xact_state_next = StIdle;
Exclude Annotation: VC_COV_UNR
295 endcase
296 end
297
298 `ASSERT(InXactStateValid_A,
299 in_xact_state inside {StIdle, StRcvdIn, StSendData, StWaitTxEnd, StWaitAckStart, StWaitAck},
300 clk_48mhz_i)
301
302 always_ff @(posedge clk_48mhz_i or negedge rst_ni) begin
303 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
304 1/1 timeout_cntdown_q <= AckTimeoutCnt[AckTimeoutCntW-1:0];
Tests: T1 T2 T3
305 end else begin
306 1/1 timeout_cntdown_q <= timeout_cntdown_d;
Tests: T1 T2 T3
307 end
308 end
309
310 always_ff @(posedge clk_48mhz_i or negedge rst_ni) begin
311 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
312 1/1 tx_data_o <= '0;
Tests: T1 T2 T3
313 end else begin
314 1/1 tx_data_o <= in_ep_data_i;
Tests: T1 T2 T3
315 end
316 end
317
318 always_ff @(posedge clk_48mhz_i or negedge rst_ni) begin
319 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
320 1/1 in_xact_state <= StIdle;
Tests: T1 T2 T3
321 1/1 in_ep_rollback_o <= 1'b0;
Tests: T1 T2 T3
322 1/1 end else if (link_reset_i || !link_active_i) begin
Tests: T1 T2 T3
323 1/1 in_xact_state <= StIdle;
Tests: T1 T2 T3
324 1/1 in_ep_rollback_o <= 1'b0;
Tests: T1 T2 T3
325 end else begin
326 1/1 in_xact_state <= in_xact_state_next;
Tests: T1 T2 T3
327 1/1 in_ep_rollback_o <= rollback_in_xact;
Tests: T1 T2 T3
328 end
329 end
330
331 always_ff @(posedge clk_48mhz_i or negedge rst_ni) begin
332 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
333 1/1 in_ep_get_addr_o <= '0;
Tests: T1 T2 T3
334 end else begin
335 1/1 if (in_xact_state == StIdle) begin
Tests: T1 T2 T3
336 1/1 in_ep_get_addr_o <= '0;
Tests: T1 T2 T3
337 1/1 end else if ((in_xact_state == StSendData) && tx_data_get_i) begin
Tests: T18 T19 T26
338 1/1 in_ep_get_addr_o <= in_ep_get_addr_o + 1'b1;
Tests: T19 T26 T8
339 end
MISSING_ELSE
340 end
341 end
342
343 always_ff @(posedge clk_48mhz_i or negedge rst_ni) begin
344 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
345 1/1 in_ep_newpkt_o <= 1'b0;
Tests: T1 T2 T3
346 1/1 in_ep_current_o <= '0;
Tests: T1 T2 T3
347 1/1 has_data_q <= 1'b0;
Tests: T1 T2 T3
348 end else begin
349 1/1 if (in_token_received) begin
Tests: T1 T2 T3
350 1/1 in_ep_current_o <= in_ep_current_d;
Tests: T18 T19 T26
351 1/1 in_ep_newpkt_o <= 1'b1;
Tests: T18 T19 T26
352 1/1 has_data_q <= in_ep_has_data_i[in_ep_index_d];
Tests: T18 T19 T26
353 end else begin
354 1/1 in_ep_newpkt_o <= 1'b0;
Tests: T1 T2 T3
355 end
356 end
357 end
358
359 // Updating of data toggles
360 always_comb begin : proc_data_toggle_d
361 1/1 data_toggle_d = data_toggle_q;
Tests: T1 T2 T3
362
363 1/1 if (setup_token_received && ep_active) begin
Tests: T1 T2 T3
364 1/1 data_toggle_d[in_ep_index_d] = 1'b1;
Tests: T5 T60 T83
365 1/1 end else if ((in_xact_state == StWaitAck) && ack_received) begin
Tests: T1 T2 T3
366 1/1 data_toggle_d[in_ep_index] = ~data_toggle_q[in_ep_index];
Tests: T18 T19 T26
367 end
MISSING_ELSE
368 // Selective modification by software
369 1/1 if (in_datatog_we_i) begin
Tests: T1 T2 T3
370 1/1 data_toggle_d = (data_toggle_d & ~in_datatog_mask_i) |
Tests: T18 T19 T104
371 (in_datatog_status_i & in_datatog_mask_i);
372 end
MISSING_ELSE
373 end
374 // Supply current data toggles to register interface
375 1/1 assign in_data_toggle_o = data_toggle_q;
Tests: T1 T2 T3
376
377 always_ff @(posedge clk_48mhz_i or negedge rst_ni) begin
378 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
379 1/1 data_toggle_q <= '0; // Clear for all endpoints
Tests: T1 T2 T3
380 1/1 end else if (link_reset_i) begin
Tests: T1 T2 T3
381 1/1 data_toggle_q <= '0; // Clear for all endpoints
Tests: T1 T2 T3
382 end else begin
383 1/1 data_toggle_q <= data_toggle_d;
Tests: T1 T2 T3
384 end
385 end
386
387 always_ff @(posedge clk_48mhz_i or negedge rst_ni) begin
388 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
389 1/1 in_ep_data_get_o <= 1'b0;
Tests: T1 T2 T3
390 end else begin
391 1/1 if ((in_xact_state == StSendData) && tx_data_get_i) begin
Tests: T1 T2 T3
392 1/1 in_ep_data_get_o <= 1'b1;
Tests: T19 T26 T8
393 end else begin
394 1/1 in_ep_data_get_o <= 1'b0;
Tests: T1 T2 T3
395 end
396 end
397 end
398
399 ////////////////////////////////////////////////////////////////////////////////
400 // Count non-Isochronous IN transactions not receiving a handshake response.
401 //
402 // - no handshake response within the timeout period
403 // - packet reception started within the timeout period but it was not ACK/NAK.
404 ////////////////////////////////////////////////////////////////////////////////
405 1/1 assign event_timeout_in_o = (in_xact_state == StWaitAckStart ||
Tests: T1 T2 T3
406 (in_xact_state == StWaitAck && rx_pkt_end_i && !nak_received))
407 & rollback_in_xact;
408
409 ////////////////////////////////////////////////////////////////////////////////
410 // Count IN transactions that are actively NAKed by the host.
411 ////////////////////////////////////////////////////////////////////////////////
412 1/1 assign event_nak_in_o = (in_xact_state == StWaitAck) && nak_received;
Tests: T1 T2 T3
413
414 ////////////////////////////////////////////////////////////////////////////////
415 // Count the number of IN requests for which data is not available, including
416 // endpoints which are supported but not presently enabled/configured.
417 // (These may be ignored using the event counter configuration if required.)
418 ////////////////////////////////////////////////////////////////////////////////
419 logic event_nodata_in_q;
420 // This event signal must be delayed by a single cycle so that 'in_ep_current_o' becomes valid.
421 always_ff @(posedge clk_48mhz_i or negedge rst_ni) begin
422 2/2 if (!rst_ni) event_nodata_in_q <= 1'b0;
Tests: T1 T2 T3 | T1 T2 T3
423 1/1 else event_nodata_in_q <= in_starting & (ep_in_hw ? !in_ep_has_data_i[in_ep_index_d] : 1'b0);
Tests: T1 T2 T3
424 end
425 1/1 assign event_nodata_in_o = event_nodata_in_q;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.usbdev_impl.u_usb_fs_nb_pe.u_usb_fs_nb_in_pe
| Total | Covered | Percent |
|---|
| Conditions | 114 | 109 | 95.61 |
| Logical | 114 | 109 | 95.61 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 135
EXPRESSION (rx_pkt_end_i && rx_pkt_valid_i && (rx_pid_type == UsbPidTypeToken) && (rx_addr_i == dev_addr_i))
------1----- -------2------ ----------------3--------------- ------------4------------
| -1- | -2- | -3- | -4- | Status | Tests |
|---|
| 0 | 1 | 1 | 1 | Covered | T2,T3,T18 |
| 1 | 0 | 1 | 1 | Covered | T71,T72,T69 |
| 1 | 1 | 0 | 1 | Covered | T2,T3,T18 |
| 1 | 1 | 1 | 0 | Covered | T17,T20,T21 |
| 1 | 1 | 1 | 1 | Covered | T2,T3,T18 |
LINE 135
SUB-EXPRESSION (rx_pid_type == UsbPidTypeToken)
----------------1---------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T17 |
LINE 135
SUB-EXPRESSION (rx_addr_i == dev_addr_i)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 141
EXPRESSION (token_received && (rx_pid == UsbPidSetup))
-------1------ -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T21,T80,T27 |
| 1 | 0 | Covered | T2,T3,T18 |
| 1 | 1 | Covered | T27,T28,T5 |
LINE 141
SUB-EXPRESSION (rx_pid == UsbPidSetup)
-----------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T21,T80,T27 |
LINE 145
EXPRESSION (token_received && (rx_pid == UsbPidIn))
-------1------ ----------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T18,T19,T21 |
| 1 | 0 | Covered | T2,T3,T18 |
| 1 | 1 | Covered | T18,T19,T26 |
LINE 145
SUB-EXPRESSION (rx_pid == UsbPidIn)
----------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T18,T19,T21 |
LINE 149
EXPRESSION (rx_pkt_end_i && rx_pkt_valid_i && (rx_pid == UsbPidAck))
------1----- -------2------ ----------3----------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T18,T19,T26 |
| 1 | 0 | 1 | Covered | T72,T76,T105 |
| 1 | 1 | 0 | Covered | T2,T3,T17 |
| 1 | 1 | 1 | Covered | T18,T19,T26 |
LINE 149
SUB-EXPRESSION (rx_pid == UsbPidAck)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T18,T19,T21 |
LINE 154
EXPRESSION (rx_pkt_end_i && rx_pkt_valid_i && (rx_pid == UsbPidNak))
------1----- -------2------ ----------3----------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T19,T102,T103 |
| 1 | 0 | 1 | Covered | T72,T106,T107 |
| 1 | 1 | 0 | Covered | T2,T3,T17 |
| 1 | 1 | 1 | Covered | T19,T103,T108 |
LINE 154
SUB-EXPRESSION (rx_pid == UsbPidNak)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T18,T19,T26 |
LINE 161
EXPRESSION (ep_in_hw ? rx_endp_i : '0)
----1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T80,T8,T4 |
| 1 | Covered | T1,T2,T3 |
LINE 172
EXPRESSION (in_ep_enabled_i[in_ep_index_d] & ep_in_hw)
---------------1-------------- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T4,T60,T109 |
| 1 | 1 | Covered | T18,T19,T21 |
LINE 178
EXPRESSION (has_data_q & ((~in_ep_data_done_i[in_ep_index])))
-----1---- -----------------2-----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T60,T86,T110 |
| 1 | 0 | Covered | T18,T19,T26 |
| 1 | 1 | Covered | T19,T26,T8 |
LINE 180
EXPRESSION ((logic'((in_xact_state == StSendData))) & more_data_to_send)
-------------------1------------------- --------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T19,T26,T8 |
| 1 | 0 | Covered | T18,T19,T26 |
| 1 | 1 | Covered | T19,T26,T8 |
LINE 186
EXPRESSION (((in_xact_state == StIdle) || (in_xact_state == StWaitAck)) && in_token_received)
-----------------------------1----------------------------- --------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T18,T19,T26 |
LINE 186
SUB-EXPRESSION ((in_xact_state == StIdle) || (in_xact_state == StWaitAck))
------------1------------ --------------2-------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T18,T19,T26 |
| 0 | 1 | Covered | T18,T19,T26 |
| 1 | 0 | Covered | T1,T2,T3 |
LINE 186
SUB-EXPRESSION (in_xact_state == StIdle)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 186
SUB-EXPRESSION (in_xact_state == StWaitAck)
--------------1-------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T18,T19,T26 |
LINE 188
EXPRESSION (in_starting & ep_active)
-----1----- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T18,T19,T21 |
| 1 | 0 | Covered | T60,T110,T111 |
| 1 | 1 | Covered | T18,T19,T26 |
LINE 207
EXPRESSION (ep_active && in_token_received)
----1---- --------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T60,T110,T111 |
| 1 | 0 | Covered | T18,T19,T21 |
| 1 | 1 | Covered | T18,T19,T26 |
LINE 239
EXPRESSION (((!more_data_to_send)) || (((&in_ep_get_addr_o)) && tx_data_get_i))
-----------1---------- --------------------2-------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T19,T26,T8 |
| 0 | 1 | Covered | T112,T5,T113 |
| 1 | 0 | Covered | T18,T19,T26 |
LINE 239
SUB-EXPRESSION (((&in_ep_get_addr_o)) && tx_data_get_i)
----------1---------- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T19,T26,T8 |
| 1 | 0 | Covered | T112,T5,T113 |
| 1 | 1 | Covered | T112,T5,T113 |
LINE 269
EXPRESSION (timeout_cntdown_q == '0)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T18,T19,T26 |
| 1 | Covered | T19,T29,T30 |
LINE 283
EXPRESSION (ep_active ? StRcvdIn : StIdle)
----1----
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Not Covered | |
LINE 322
EXPRESSION (link_reset_i || ((!link_active_i)))
------1----- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
LINE 335
EXPRESSION (in_xact_state == StIdle)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T18,T19,T26 |
| 1 | Covered | T1,T2,T3 |
LINE 337
EXPRESSION ((in_xact_state == StSendData) && tx_data_get_i)
--------------1-------------- ------2------
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | Excluded | |
VC_COV_UNR |
| 1 | 0 | Covered | T18,T19,T26 |
| 1 | 1 | Covered | T19,T26,T8 |
LINE 337
SUB-EXPRESSION (in_xact_state == StSendData)
--------------1--------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T18,T19,T26 |
| 1 | Covered | T18,T19,T26 |
LINE 363
EXPRESSION (setup_token_received && ep_active)
----------1--------- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T18,T19,T21 |
| 1 | 0 | Covered | T27,T28,T60 |
| 1 | 1 | Covered | T5,T60,T83 |
LINE 365
EXPRESSION ((in_xact_state == StWaitAck) && ack_received)
--------------1------------- ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T18,T19,T26 |
| 1 | 1 | Covered | T18,T19,T26 |
LINE 365
SUB-EXPRESSION (in_xact_state == StWaitAck)
--------------1-------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T18,T19,T26 |
LINE 391
EXPRESSION ((in_xact_state == StSendData) && tx_data_get_i)
--------------1-------------- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T114 |
| 1 | 0 | Covered | T18,T19,T26 |
| 1 | 1 | Covered | T19,T26,T8 |
LINE 391
SUB-EXPRESSION (in_xact_state == StSendData)
--------------1--------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T18,T19,T26 |
LINE 405
EXPRESSION (((in_xact_state == StWaitAckStart) || ((in_xact_state == StWaitAck) && rx_pkt_end_i && ((!nak_received)))) & rollback_in_xact)
-----------------------------------------------------1---------------------------------------------------- --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T19,T103,T108 |
| 1 | 0 | Covered | T18,T19,T26 |
| 1 | 1 | Covered | T19,T29,T30 |
LINE 405
SUB-EXPRESSION ((in_xact_state == StWaitAckStart) || ((in_xact_state == StWaitAck) && rx_pkt_end_i && ((!nak_received))))
----------------1---------------- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T18,T19,T26 |
| 1 | 0 | Covered | T18,T19,T26 |
LINE 405
SUB-EXPRESSION (in_xact_state == StWaitAckStart)
----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T18,T19,T26 |
LINE 405
SUB-EXPRESSION ((in_xact_state == StWaitAck) && rx_pkt_end_i && ((!nak_received)))
--------------1------------- ------2----- --------3--------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T2,T3,T17 |
| 1 | 0 | 1 | Covered | T18,T19,T26 |
| 1 | 1 | 0 | Covered | T19,T103,T108 |
| 1 | 1 | 1 | Covered | T18,T19,T26 |
LINE 405
SUB-EXPRESSION (in_xact_state == StWaitAck)
--------------1-------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T18,T19,T26 |
LINE 412
EXPRESSION ((in_xact_state == StWaitAck) && nak_received)
--------------1------------- ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T18,T19,T26 |
| 1 | 1 | Covered | T19,T103,T108 |
LINE 412
SUB-EXPRESSION (in_xact_state == StWaitAck)
--------------1-------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T18,T19,T26 |
LINE 423
EXPRESSION (in_starting & (ep_in_hw ? ((!in_ep_has_data_i[in_ep_index_d])) : 1'b0))
-----1----- ----------------------------2---------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T18,T19,T26 |
| 1 | 1 | Covered | T4,T5,T6 |
LINE 423
SUB-EXPRESSION (ep_in_hw ? ((!in_ep_has_data_i[in_ep_index_d])) : 1'b0)
----1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T80,T8,T4 |
| 1 | Covered | T1,T2,T3 |
FSM Coverage for Instance : tb.dut.usbdev_impl.u_usb_fs_nb_pe.u_usb_fs_nb_in_pe
Summary for FSM :: in_xact_state
| Total | Covered | Percent | |
| States |
6 |
6 |
100.00 |
(Not included in score) |
| Transitions |
11 |
10 |
90.91 |
|
| Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: in_xact_state
| states | Line No. | Covered | Tests |
| StIdle |
323 |
Covered |
T1,T2,T3 |
| StRcvdIn |
208 |
Covered |
T18,T19,T26 |
| StSendData |
223 |
Covered |
T18,T19,T26 |
| StWaitAck |
268 |
Covered |
T18,T19,T26 |
| StWaitAckStart |
245 |
Covered |
T18,T19,T26 |
| StWaitTxEnd |
247 |
Covered |
T18,T19,T26 |
| transitions | Line No. | Covered | Tests | Exclude Annotation |
| StIdle->StRcvdIn |
208 |
Covered |
T18,T19,T26 |
|
| StRcvdIn->StIdle |
323 |
Covered |
T100,T4,T5 |
|
| StRcvdIn->StSendData |
223 |
Covered |
T18,T19,T26 |
|
| StSendData->StIdle |
323 |
Covered |
T32,T99,T86 |
|
| StSendData->StWaitAckStart |
245 |
Excluded |
|
VC_COV_UNR |
| StSendData->StWaitTxEnd |
247 |
Covered |
T18,T19,T26 |
|
| StWaitAck->StIdle |
323 |
Covered |
T18,T19,T26 |
|
| StWaitAck->StRcvdIn |
283 |
Not Covered |
|
|
| StWaitAckStart->StIdle |
323 |
Covered |
T19,T29,T30 |
|
| StWaitAckStart->StWaitAck |
268 |
Covered |
T18,T19,T26 |
|
| StWaitTxEnd->StIdle |
323 |
Covered |
T115,T116,T117 |
|
| StWaitTxEnd->StWaitAckStart |
257 |
Covered |
T18,T19,T26 |
|
Branch Coverage for Instance : tb.dut.usbdev_impl.u_usb_fs_nb_pe.u_usb_fs_nb_in_pe
| Line No. | Total | Covered | Percent |
| Branches |
|
48 |
46 |
95.83 |
| TERNARY |
161 |
2 |
2 |
100.00 |
| CASE |
205 |
19 |
17 |
89.47 |
| IF |
303 |
2 |
2 |
100.00 |
| IF |
311 |
2 |
2 |
100.00 |
| IF |
319 |
3 |
3 |
100.00 |
| IF |
332 |
4 |
4 |
100.00 |
| IF |
344 |
3 |
3 |
100.00 |
| IF |
363 |
3 |
3 |
100.00 |
| IF |
369 |
2 |
2 |
100.00 |
| IF |
378 |
3 |
3 |
100.00 |
| IF |
388 |
3 |
3 |
100.00 |
| IF |
422 |
2 |
2 |
100.00 |
161 assign in_ep_current_d = ep_in_hw ? rx_endp_i : '0;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T80,T8,T4 |
205 unique case (in_xact_state)
-1-
206 StIdle: begin
207 if (ep_active && in_token_received) begin
-2-
208 in_xact_state_next = StRcvdIn;
==>
209 end else begin
210 // Ignore tokens to inactive endpoints. Send no response.
211 in_xact_state_next = StIdle;
==>
212 end
213 end
214
215 StRcvdIn: begin
216 tx_pkt_start_o = 1'b1; // Need to transmit NAK/STALL or DATA
217
218 if (in_ep_iso_i[in_ep_index]) begin
-3-
219 // ISO endpoint
220 // We always need to transmit. When no data is available, we send
221 // a zero-length packet.
222 // DATA0 always for full-speed isochronous endpoints
223 in_xact_state_next = StSendData;
==>
224 tx_pid_o = {UsbPidData0};
225 end else if (in_ep_stall_i[in_ep_index]) begin
-4-
226 in_xact_state_next = StIdle;
==>
227 tx_pid_o = {UsbPidStall}; // STALL
228 end else if (has_data_q) begin
-5-
229 in_xact_state_next = StSendData;
==>
230 tx_pid_o = {data_toggle_q[in_ep_index], 1'b0, {UsbPidTypeData}}; // DATA0/1
231 end else begin
232 in_xact_state_next = StIdle;
==>
233 tx_pid_o = {UsbPidNak}; // NAK
234 end
235 end
236
237 StSendData: begin
238 // Use &in_ep_get_addr so width can vary, looking for all ones
239 if ((!more_data_to_send) || ((&in_ep_get_addr_o) && tx_data_get_i)) begin
-6-
240 if (in_ep_iso_i[in_ep_index]) begin
-7-
241 in_xact_state_next = StIdle; // no ACK for ISO EPs
==>
242 in_xact_end = has_data_q;
243 end else begin
244 if (tx_pkt_end_i) begin
-8-
245 in_xact_state_next = StWaitAckStart;
==> (Excluded)
Exclude Annotation: VC_COV_UNR
246 end else begin
247 in_xact_state_next = StWaitTxEnd;
==>
248 end
249 end
250 end else begin
251 in_xact_state_next = StSendData;
==>
252 end
253 end
254
255 StWaitTxEnd: begin
256 if (tx_pkt_end_i) begin
-9-
257 in_xact_state_next = StWaitAckStart;
==>
258 end
MISSING_ELSE
==>
259 end
260
261 StWaitAckStart: begin
262 // The spec says we have up to 18 bit times to wait for the host
263 // response. If it doesn't arrive in time, we must invalidate the
264 // transaction.
265 timeout_cntdown_d = timeout_cntdown_q - 1'b1;
266
267 if (rx_pkt_start_i) begin
-10-
268 in_xact_state_next = StWaitAck;
==>
269 end else if (timeout_cntdown_q == '0) begin
-11-
270 in_xact_state_next = StIdle;
==>
271 rollback_in_xact = 1'b1;
272 end else begin
273 in_xact_state_next = StWaitAckStart;
==>
274 end
275 end
276
277 StWaitAck: begin
278 if (ack_received) begin
-12-
279 in_xact_state_next = StIdle;
==>
280 in_xact_end = 1'b1;
281 end else if (in_token_received) begin
-13-
282 // Handshake response is missing.
283 in_xact_state_next = ep_active ? StRcvdIn : StIdle;
-14-
==>
==>
284 rollback_in_xact = 1'b1;
285 end else if (rx_pkt_end_i) begin
-15-
286 // Includes NAK
287 in_xact_state_next = StIdle;
==>
288 rollback_in_xact = 1'b1;
289 end else begin
290 in_xact_state_next = StWaitAck;
==>
291 end
292 end
293
294 default: in_xact_state_next = StIdle;
==> (Excluded)
Exclude Annotation: VC_COV_UNR
Branches:
| -1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | -9- | -10- | -11- | -12- | -13- | -14- | -15- | Status | Tests | Exclude Annotation |
| StIdle |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T18,T19,T26 |
|
| StIdle |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
|
| StRcvdIn |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T32,T99,T86 |
|
| StRcvdIn |
- |
0 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T100,T60,T101 |
|
| StRcvdIn |
- |
0 |
0 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T18,T19,T26 |
|
| StRcvdIn |
- |
0 |
0 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T4,T5,T6 |
|
| StSendData |
- |
- |
- |
- |
1 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T32,T99,T86 |
|
| StSendData |
- |
- |
- |
- |
1 |
0 |
1 |
- |
- |
- |
- |
- |
- |
- |
Excluded |
|
VC_COV_UNR |
| StSendData |
- |
- |
- |
- |
1 |
0 |
0 |
- |
- |
- |
- |
- |
- |
- |
Covered |
T18,T19,T26 |
|
| StSendData |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T19,T26,T8 |
|
| StWaitTxEnd |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T18,T19,T26 |
|
| StWaitTxEnd |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
Covered |
T18,T19,T26 |
|
| StWaitAckStart |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
Covered |
T18,T19,T26 |
|
| StWaitAckStart |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
1 |
- |
- |
- |
- |
Covered |
T19,T29,T30 |
|
| StWaitAckStart |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
- |
- |
- |
- |
Covered |
T18,T19,T26 |
|
| StWaitAck |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
Covered |
T18,T19,T26 |
|
| StWaitAck |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
1 |
1 |
- |
Not Covered |
|
|
| StWaitAck |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
1 |
0 |
- |
Not Covered |
|
|
| StWaitAck |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
- |
1 |
Covered |
T19,T102,T103 |
|
| StWaitAck |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
- |
0 |
Covered |
T18,T19,T26 |
|
| default |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Excluded |
|
VC_COV_UNR |
303 if (!rst_ni) begin
-1-
304 timeout_cntdown_q <= AckTimeoutCnt[AckTimeoutCntW-1:0];
==>
305 end else begin
306 timeout_cntdown_q <= timeout_cntdown_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
311 if (!rst_ni) begin
-1-
312 tx_data_o <= '0;
==>
313 end else begin
314 tx_data_o <= in_ep_data_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
319 if (!rst_ni) begin
-1-
320 in_xact_state <= StIdle;
==>
321 in_ep_rollback_o <= 1'b0;
322 end else if (link_reset_i || !link_active_i) begin
-2-
323 in_xact_state <= StIdle;
==>
324 in_ep_rollback_o <= 1'b0;
325 end else begin
326 in_xact_state <= in_xact_state_next;
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
332 if (!rst_ni) begin
-1-
333 in_ep_get_addr_o <= '0;
==>
334 end else begin
335 if (in_xact_state == StIdle) begin
-2-
336 in_ep_get_addr_o <= '0;
==>
337 end else if ((in_xact_state == StSendData) && tx_data_get_i) begin
-3-
338 in_ep_get_addr_o <= in_ep_get_addr_o + 1'b1;
==>
339 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T1,T2,T3 |
| 0 |
0 |
1 |
Covered |
T19,T26,T8 |
| 0 |
0 |
0 |
Covered |
T18,T19,T26 |
344 if (!rst_ni) begin
-1-
345 in_ep_newpkt_o <= 1'b0;
==>
346 in_ep_current_o <= '0;
347 has_data_q <= 1'b0;
348 end else begin
349 if (in_token_received) begin
-2-
350 in_ep_current_o <= in_ep_current_d;
==>
351 in_ep_newpkt_o <= 1'b1;
352 has_data_q <= in_ep_has_data_i[in_ep_index_d];
353 end else begin
354 in_ep_newpkt_o <= 1'b0;
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T18,T19,T26 |
| 0 |
0 |
Covered |
T1,T2,T3 |
363 if (setup_token_received && ep_active) begin
-1-
364 data_toggle_d[in_ep_index_d] = 1'b1;
==>
365 end else if ((in_xact_state == StWaitAck) && ack_received) begin
-2-
366 data_toggle_d[in_ep_index] = ~data_toggle_q[in_ep_index];
==>
367 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T5,T60,T83 |
| 0 |
1 |
Covered |
T18,T19,T26 |
| 0 |
0 |
Covered |
T1,T2,T3 |
369 if (in_datatog_we_i) begin
-1-
370 data_toggle_d = (data_toggle_d & ~in_datatog_mask_i) |
==>
371 (in_datatog_status_i & in_datatog_mask_i);
372 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T18,T19,T104 |
| 0 |
Covered |
T1,T2,T3 |
378 if (!rst_ni) begin
-1-
379 data_toggle_q <= '0; // Clear for all endpoints
==>
380 end else if (link_reset_i) begin
-2-
381 data_toggle_q <= '0; // Clear for all endpoints
==>
382 end else begin
383 data_toggle_q <= data_toggle_d;
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
388 if (!rst_ni) begin
-1-
389 in_ep_data_get_o <= 1'b0;
==>
390 end else begin
391 if ((in_xact_state == StSendData) && tx_data_get_i) begin
-2-
392 in_ep_data_get_o <= 1'b1;
==>
393 end else begin
394 in_ep_data_get_o <= 1'b0;
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T19,T26,T8 |
| 0 |
0 |
Covered |
T1,T2,T3 |
422 if (!rst_ni) event_nodata_in_q <= 1'b0;
-1-
==>
423 else event_nodata_in_q <= in_starting & (ep_in_hw ? !in_ep_has_data_i[in_ep_index_d] : 1'b0);
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.usbdev_impl.u_usb_fs_nb_pe.u_usb_fs_nb_in_pe
Assertion Details
InXactStateValid_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
584743025 |
584444689 |
0 |
0 |
| T1 |
200035 |
199940 |
0 |
0 |
| T2 |
8838 |
8758 |
0 |
0 |
| T3 |
9382 |
9283 |
0 |
0 |
| T7 |
701361 |
701279 |
0 |
0 |
| T16 |
8019 |
7966 |
0 |
0 |
| T17 |
7604 |
7521 |
0 |
0 |
| T18 |
9070 |
9002 |
0 |
0 |
| T19 |
34405 |
34355 |
0 |
0 |
| T20 |
8875 |
8787 |
0 |
0 |
| T21 |
17497 |
17427 |
0 |
0 |