Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	9670378	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

10268313

1

T1

18

T2

9

T3

8

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	19291291	1			T1	17		T2	10		T3	7
values[0x0]	323048	1			T1	3		T2	6		T3	5
values[0x1]	324352	1			T1	4		T2	4		T3	6

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7687802	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

12250889

1

T1

20

T2

14

T3

10

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	175902	1			T7	1		T24	1		T25	4
valid_sources[0x01]	57985	1			T7	1		T25	1		T41	5
valid_sources[0x02]	58517	1			T7	2		T25	2		T29	1
valid_sources[0x03]	143423	1			T25	5		T41	3		T35	88
valid_sources[0x04]	82538	1			T20	1		T33	1		T41	3
valid_sources[0x05]	56961	1			T7	1		T25	7		T29	1
valid_sources[0x06]	64157	1			T25	2		T29	1		T41	10
valid_sources[0x07]	66538	1			T7	1		T25	5		T33	1
valid_sources[0x08]	129037	1			T1	5		T25	4		T41	5
valid_sources[0x09]	57608	1			T25	2		T29	1		T41	4
valid_sources[0x0a]	62896	1			T25	7		T29	1		T41	8
valid_sources[0x0b]	69247	1			T25	4		T41	3		T35	65
valid_sources[0x0c]	75321	1			T7	1		T25	7		T29	1
valid_sources[0x0d]	58273	1			T25	3		T29	1		T33	2
valid_sources[0x0e]	58010	1			T25	6		T29	1		T41	7
valid_sources[0x0f]	96746	1			T25	2		T41	5		T35	122
valid_sources[0x10]	57890	1			T7	1		T20	1		T25	3
valid_sources[0x11]	57022	1			T25	7		T29	1		T41	9
valid_sources[0x12]	104347	1			T7	1		T25	2		T29	2
valid_sources[0x13]	59227	1			T7	1		T20	3		T25	3
valid_sources[0x14]	79840	1			T23	3		T25	8		T41	4
valid_sources[0x15]	71091	1			T25	2		T29	1		T41	4
valid_sources[0x16]	56660	1			T7	1		T25	3		T41	5
valid_sources[0x17]	68828	1			T7	3		T25	4		T29	2
valid_sources[0x18]	57520	1			T25	4		T29	2		T41	6
valid_sources[0x19]	80365	1			T7	1		T20	2		T25	6
valid_sources[0x1a]	56881	1			T25	10		T41	8		T35	54
valid_sources[0x1b]	87652	1			T7	1		T25	3		T29	1
valid_sources[0x1c]	125076	1			T20	1		T25	5		T41	2
valid_sources[0x1d]	102505	1			T24	1		T25	5		T41	11
valid_sources[0x1e]	126887	1			T7	3		T25	7		T29	1
valid_sources[0x1f]	116332	1			T7	2		T20	1		T24	1
valid_sources[0x20]	109279	1			T7	1		T24	1		T25	9
valid_sources[0x21]	73048	1			T25	1		T41	11		T35	80
valid_sources[0x22]	57928	1			T25	2		T41	11		T35	46
valid_sources[0x23]	58230	1			T7	2		T25	3		T29	1
valid_sources[0x24]	56512	1			T20	2		T24	1		T29	2
valid_sources[0x25]	74983	1			T7	1		T17	1		T24	1
valid_sources[0x26]	58645	1			T7	1		T25	5		T29	1
valid_sources[0x27]	202788	1			T7	1		T25	2		T29	1
valid_sources[0x28]	60524	1			T29	1		T41	10		T35	59
valid_sources[0x29]	58592	1			T7	1		T25	2		T41	4
valid_sources[0x2a]	58068	1			T25	3		T32	1		T41	12
valid_sources[0x2b]	57697	1			T25	6		T29	1		T41	2
valid_sources[0x2c]	58654	1			T25	1		T32	1		T41	7
valid_sources[0x2d]	79545	1			T25	3		T29	1		T41	1
valid_sources[0x2e]	58509	1			T7	1		T25	2		T29	2
valid_sources[0x2f]	64257	1			T7	2		T25	6		T41	11
valid_sources[0x30]	58946	1			T7	3		T25	6		T29	1
valid_sources[0x31]	57611	1			T7	2		T25	4		T41	8
valid_sources[0x32]	57569	1			T7	1		T25	2		T29	1
valid_sources[0x33]	57275	1			T7	2		T25	4		T29	1
valid_sources[0x34]	58149	1			T25	8		T29	1		T41	9
valid_sources[0x35]	57698	1			T7	1		T24	1		T25	7
valid_sources[0x36]	57194	1			T25	2		T29	1		T41	5
valid_sources[0x37]	88992	1			T25	5		T29	1		T41	4
valid_sources[0x38]	96848	1			T25	2		T41	4		T35	112
valid_sources[0x39]	57950	1			T25	6		T29	1		T41	3
valid_sources[0x3a]	56940	1			T25	2		T33	1		T41	7
valid_sources[0x3b]	58148	1			T7	2		T25	3		T41	6
valid_sources[0x3c]	70476	1			T25	1		T41	10		T35	106
valid_sources[0x3d]	90391	1			T7	2		T25	3		T29	4
valid_sources[0x3e]	57606	1			T7	2		T20	1		T24	1
valid_sources[0x3f]	58062	1			T25	5		T29	1		T41	5
valid_sources[0x40]	76171	1			T7	1		T41	9		T35	73
valid_sources[0x41]	131910	1			T7	2		T25	3		T41	2
valid_sources[0x42]	76159	1			T7	1		T25	5		T29	3
valid_sources[0x43]	56191	1			T25	6		T29	1		T33	3
valid_sources[0x44]	125223	1			T7	3		T17	1		T25	3
valid_sources[0x45]	58748	1			T7	1		T25	4		T29	1
valid_sources[0x46]	56036	1			T7	1		T25	3		T41	6
valid_sources[0x47]	59534	1			T25	8		T29	1		T41	8
valid_sources[0x48]	125178	1			T7	1		T17	1		T25	2
valid_sources[0x49]	57207	1			T25	4		T29	2		T41	5
valid_sources[0x4a]	58105	1			T25	4		T29	1		T41	8
valid_sources[0x4b]	160201	1			T7	1		T25	5		T41	4
valid_sources[0x4c]	58501	1			T3	1		T7	2		T20	3
valid_sources[0x4d]	103318	1			T7	1		T25	3		T41	7
valid_sources[0x4e]	137095	1			T25	3		T41	8		T35	62
valid_sources[0x4f]	107962	1			T7	1		T25	1		T41	6
valid_sources[0x50]	59230	1			T7	2		T25	6		T41	6
valid_sources[0x51]	83085	1			T7	1		T23	19		T25	3
valid_sources[0x52]	73746	1			T25	8		T41	3		T35	89
valid_sources[0x53]	56102	1			T25	4		T41	4		T35	28
valid_sources[0x54]	74308	1			T7	1		T19	252		T25	3
valid_sources[0x55]	56975	1			T25	7		T41	5		T35	116
valid_sources[0x56]	59185	1			T25	2		T29	1		T41	4
valid_sources[0x57]	58509	1			T7	3		T20	1		T25	2
valid_sources[0x58]	57345	1			T7	1		T25	2		T41	8
valid_sources[0x59]	69908	1			T7	2		T23	1		T25	7
valid_sources[0x5a]	57864	1			T25	1		T41	2		T35	84
valid_sources[0x5b]	56931	1			T7	3		T20	1		T25	1
valid_sources[0x5c]	56823	1			T7	2		T25	1		T41	10
valid_sources[0x5d]	58042	1			T7	3		T25	4		T29	2
valid_sources[0x5e]	58943	1			T25	4		T29	2		T41	7
valid_sources[0x5f]	57111	1			T7	1		T20	1		T41	3
valid_sources[0x60]	56720	1			T25	2		T29	2		T41	8
valid_sources[0x61]	58739	1			T25	2		T41	6		T35	116
valid_sources[0x62]	77248	1			T7	1		T25	3		T29	1
valid_sources[0x63]	97472	1			T7	1		T25	4		T29	2
valid_sources[0x64]	59729	1			T20	1		T24	1		T25	1
valid_sources[0x65]	83470	1			T7	2		T25	4		T41	7
valid_sources[0x66]	81060	1			T7	1		T25	4		T33	1
valid_sources[0x67]	58582	1			T7	1		T25	5		T29	5
valid_sources[0x68]	59239	1			T7	2		T25	7		T41	6
valid_sources[0x69]	80354	1			T7	1		T25	2		T29	3
valid_sources[0x6a]	118648	1			T7	1		T25	2		T29	1
valid_sources[0x6b]	71823	1			T24	1		T25	2		T41	5
valid_sources[0x6c]	59104	1			T25	2		T29	3		T41	4
valid_sources[0x6d]	147452	1			T7	2		T25	2		T41	5
valid_sources[0x6e]	58047	1			T7	2		T20	2		T25	4
valid_sources[0x6f]	60606	1			T25	2		T41	4		T35	67
valid_sources[0x70]	58415	1			T3	8		T25	4		T35	45
valid_sources[0x71]	70310	1			T7	1		T25	4		T29	1
valid_sources[0x72]	88999	1			T25	5		T29	1		T41	10
valid_sources[0x73]	74420	1			T7	2		T25	10		T41	1
valid_sources[0x74]	65052	1			T7	3		T20	2		T25	4
valid_sources[0x75]	87503	1			T25	1		T41	7		T34	2
valid_sources[0x76]	58843	1			T3	1		T29	1		T41	6
valid_sources[0x77]	70014	1			T7	1		T17	1		T25	4
valid_sources[0x78]	60523	1			T25	1		T41	11		T35	95
valid_sources[0x79]	77094	1			T25	2		T29	1		T41	7
valid_sources[0x7a]	59187	1			T20	1		T25	3		T29	1
valid_sources[0x7b]	58647	1			T7	1		T17	1		T25	2
valid_sources[0x7c]	108425	1			T7	1		T25	4		T41	2
valid_sources[0x7d]	57172	1			T7	1		T29	1		T41	6
valid_sources[0x7e]	104337	1			T7	2		T29	1		T41	9
valid_sources[0x7f]	58490	1			T7	1		T25	2		T29	4
valid_sources[0x80]	55717	1			T25	4		T29	3		T41	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

9745853

1

T1

15

T2

2

T3

3

values[0x0]

all_enables

biggest_size

269890

1

T1

1

T2

5

T3

4

values[0x1]

all_enables

biggest_size

252570

1

T1

2

T2

2

T3

1