Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	9778876	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

10387427

1

T1

11

T2

7

T3

7

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	19513543	1			T1	7		T2	7		T3	8
values[0x0]	325437	1			T1	5		T2	4		T3	6
values[0x1]	327323	1			T1	10		T2	3		T3	3

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7775512	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

12390791

1

T1

11

T2

11

T3

9

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	62238	1			T30	2		T19	7		T8	10
valid_sources[0x01]	112770	1			T28	2		T30	1		T19	5
valid_sources[0x02]	78616	1			T1	1		T30	2		T17	1
valid_sources[0x03]	73372	1			T30	1		T19	1		T8	5
valid_sources[0x04]	61061	1			T30	1		T17	1		T19	3
valid_sources[0x05]	60970	1			T1	1		T30	4		T17	1
valid_sources[0x06]	61660	1			T17	1		T19	3		T8	6
valid_sources[0x07]	60340	1			T3	1		T30	1		T19	3
valid_sources[0x08]	60559	1			T30	1		T17	4		T19	4
valid_sources[0x09]	101443	1			T30	5		T35	1		T17	1
valid_sources[0x0a]	61300	1			T19	3		T31	91		T45	1
valid_sources[0x0b]	74858	1			T30	1		T19	6		T8	6
valid_sources[0x0c]	61069	1			T19	2		T8	3		T31	109
valid_sources[0x0d]	60974	1			T30	1		T17	2		T19	5
valid_sources[0x0e]	61450	1			T30	1		T19	3		T8	10
valid_sources[0x0f]	119625	1			T17	1		T19	5		T8	6
valid_sources[0x10]	60357	1			T30	2		T19	4		T20	7
valid_sources[0x11]	61241	1			T30	3		T19	6		T8	1
valid_sources[0x12]	60587	1			T19	3		T31	77		T45	9
valid_sources[0x13]	60961	1			T30	1		T17	1		T19	2
valid_sources[0x14]	60730	1			T37	1		T17	2		T19	4
valid_sources[0x15]	224672	1			T3	1		T30	2		T17	1
valid_sources[0x16]	74073	1			T30	5		T35	1		T19	4
valid_sources[0x17]	92581	1			T17	1		T19	3		T8	1
valid_sources[0x18]	60235	1			T28	1		T30	3		T19	3
valid_sources[0x19]	61509	1			T28	1		T30	2		T17	2
valid_sources[0x1a]	61231	1			T3	1		T30	3		T19	1
valid_sources[0x1b]	71370	1			T30	3		T36	17		T17	1
valid_sources[0x1c]	61122	1			T28	1		T30	1		T19	2
valid_sources[0x1d]	79843	1			T30	4		T19	2		T23	1
valid_sources[0x1e]	61629	1			T28	1		T30	1		T35	2
valid_sources[0x1f]	61464	1			T19	2		T8	4		T31	74
valid_sources[0x20]	61150	1			T28	3		T30	2		T17	1
valid_sources[0x21]	65306	1			T30	1		T17	1		T8	5
valid_sources[0x22]	81218	1			T17	4		T19	5		T8	2
valid_sources[0x23]	65014	1			T30	1		T8	6		T31	110
valid_sources[0x24]	79646	1			T28	2		T19	5		T8	6
valid_sources[0x25]	61633	1			T30	2		T17	2		T19	1
valid_sources[0x26]	63182	1			T30	1		T19	4		T8	1
valid_sources[0x27]	96601	1			T30	5		T19	3		T8	2
valid_sources[0x28]	60720	1			T28	2		T30	1		T19	4
valid_sources[0x29]	62284	1			T30	2		T7	61		T17	1
valid_sources[0x2a]	61418	1			T19	5		T31	79		T45	6
valid_sources[0x2b]	61903	1			T30	1		T17	2		T19	1
valid_sources[0x2c]	61801	1			T30	1		T8	6		T31	108
valid_sources[0x2d]	73243	1			T28	1		T30	1		T17	2
valid_sources[0x2e]	116230	1			T28	2		T30	2		T17	1
valid_sources[0x2f]	79360	1			T30	1		T17	2		T19	3
valid_sources[0x30]	62107	1			T2	1		T30	1		T19	1
valid_sources[0x31]	61421	1			T30	1		T19	4		T8	1
valid_sources[0x32]	61151	1			T19	5		T8	11		T31	77
valid_sources[0x33]	133191	1			T17	2		T19	3		T8	9
valid_sources[0x34]	62483	1			T28	2		T30	1		T36	4
valid_sources[0x35]	84368	1			T30	1		T17	1		T19	2
valid_sources[0x36]	61660	1			T1	1		T19	1		T8	3
valid_sources[0x37]	103733	1			T1	1		T30	1		T36	9
valid_sources[0x38]	76799	1			T30	4		T8	2		T31	104
valid_sources[0x39]	61118	1			T30	2		T19	1		T8	24
valid_sources[0x3a]	61324	1			T3	1		T28	1		T30	2
valid_sources[0x3b]	94914	1			T30	2		T19	2		T8	8
valid_sources[0x3c]	92393	1			T30	2		T17	2		T19	3
valid_sources[0x3d]	60906	1			T30	1		T19	2		T8	2
valid_sources[0x3e]	99961	1			T17	4		T19	5		T8	1
valid_sources[0x3f]	79065	1			T28	1		T29	2		T17	1
valid_sources[0x40]	62675	1			T29	3		T30	4		T17	1
valid_sources[0x41]	73239	1			T30	2		T17	2		T19	1
valid_sources[0x42]	79878	1			T30	1		T17	1		T19	1
valid_sources[0x43]	88656	1			T3	1		T30	1		T17	1
valid_sources[0x44]	59684	1			T28	1		T30	5		T19	4
valid_sources[0x45]	131047	1			T3	1		T30	7		T19	4
valid_sources[0x46]	69385	1			T28	1		T17	1		T19	5
valid_sources[0x47]	121829	1			T1	1		T30	6		T19	3
valid_sources[0x48]	73596	1			T2	1		T3	1		T34	12
valid_sources[0x49]	61392	1			T29	2		T17	1		T19	3
valid_sources[0x4a]	61828	1			T30	2		T18	5		T19	1
valid_sources[0x4b]	60260	1			T30	2		T18	6		T19	4
valid_sources[0x4c]	61696	1			T1	1		T2	2		T28	1
valid_sources[0x4d]	60609	1			T30	2		T17	1		T8	3
valid_sources[0x4e]	78218	1			T1	1		T28	2		T30	3
valid_sources[0x4f]	65198	1			T28	1		T30	2		T17	1
valid_sources[0x50]	95574	1			T30	3		T17	1		T19	6
valid_sources[0x51]	60413	1			T30	2		T17	1		T19	2
valid_sources[0x52]	155929	1			T17	2		T19	2		T8	8
valid_sources[0x53]	59374	1			T30	1		T17	2		T19	2
valid_sources[0x54]	97826	1			T30	1		T17	1		T19	5
valid_sources[0x55]	60227	1			T30	1		T19	1		T8	4
valid_sources[0x56]	60716	1			T28	2		T17	2		T19	8
valid_sources[0x57]	60861	1			T29	1		T30	1		T19	8
valid_sources[0x58]	106860	1			T19	2		T8	1		T31	105
valid_sources[0x59]	61085	1			T30	1		T17	1		T19	2
valid_sources[0x5a]	59586	1			T2	1		T36	9		T19	9
valid_sources[0x5b]	60592	1			T29	1		T8	7		T31	95
valid_sources[0x5c]	89732	1			T30	1		T19	5		T8	5
valid_sources[0x5d]	61398	1			T28	2		T17	1		T18	2
valid_sources[0x5e]	60337	1			T19	1		T31	120		T45	8
valid_sources[0x5f]	168855	1			T30	2		T19	13		T8	8
valid_sources[0x60]	80089	1			T30	1		T8	2		T31	127
valid_sources[0x61]	68936	1			T17	2		T19	2		T8	2
valid_sources[0x62]	63746	1			T19	2		T8	2		T31	106
valid_sources[0x63]	148912	1			T30	5		T17	3		T19	5
valid_sources[0x64]	77785	1			T30	3		T19	7		T8	2
valid_sources[0x65]	81179	1			T30	1		T19	3		T20	2
valid_sources[0x66]	60671	1			T36	4		T17	1		T31	108
valid_sources[0x67]	61277	1			T17	1		T19	4		T8	13
valid_sources[0x68]	60298	1			T30	1		T19	3		T8	1
valid_sources[0x69]	61455	1			T30	4		T19	2		T8	9
valid_sources[0x6a]	61339	1			T30	8		T17	2		T8	11
valid_sources[0x6b]	61132	1			T30	2		T17	1		T19	8
valid_sources[0x6c]	61847	1			T30	1		T17	1		T19	2
valid_sources[0x6d]	60036	1			T30	3		T36	3		T19	8
valid_sources[0x6e]	61092	1			T19	5		T20	1		T8	2
valid_sources[0x6f]	61387	1			T3	1		T30	3		T17	1
valid_sources[0x70]	78134	1			T3	1		T28	1		T30	2
valid_sources[0x71]	72527	1			T30	3		T19	4		T8	3
valid_sources[0x72]	112620	1			T18	1		T19	6		T8	1
valid_sources[0x73]	104450	1			T1	1		T30	2		T22	9
valid_sources[0x74]	64650	1			T30	1		T17	2		T19	1
valid_sources[0x75]	61706	1			T30	1		T17	1		T19	2
valid_sources[0x76]	89939	1			T28	2		T17	1		T19	1
valid_sources[0x77]	60015	1			T19	2		T31	74		T45	5
valid_sources[0x78]	92879	1			T30	1		T37	1		T19	4
valid_sources[0x79]	60249	1			T19	4		T8	1		T23	1
valid_sources[0x7a]	161876	1			T30	1		T36	1		T19	6
valid_sources[0x7b]	61188	1			T28	1		T30	1		T19	4
valid_sources[0x7c]	89653	1			T30	3		T19	3		T8	4
valid_sources[0x7d]	65497	1			T17	1		T19	2		T8	5
valid_sources[0x7e]	138553	1			T28	2		T30	6		T37	1
valid_sources[0x7f]	76359	1			T28	3		T30	1		T19	3
valid_sources[0x80]	61416	1			T1	1		T3	1		T17	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

9857180

1

T1

4

T2

4

T3

2

values[0x0]

all_enables

biggest_size

273456

1

T1

4

T2

2

T3

5

values[0x1]

all_enables

biggest_size

256791

1

T1

3

T2

1

T34

1