Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

9794532

1

T1

11

T2

7

T3

10

full_word

10388589

1

T1

11

T2

7

T3

7

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	20182811	1			T1	22		T2	14		T3	17
auto[TlIntgErrCmd]	122	1			T241	4		T248	6		T249	12
auto[TlIntgErrData]	99	1			T241	8		T248	8		T249	6
auto[TlIntgErrBoth]	89	1			T241	8		T248	6		T249	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19515601

1

T1

7

T2

7

T3

8

auto[1]

667520

1

T1

15

T2

7

T3

9

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrCmd]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	9658052	1			T1	3		T2	3		T3	6
auto[TlIntgErrNone]	partial	auto[1]	136200	1			T1	8		T2	4		T3	4
auto[TlIntgErrNone]	full_word	auto[0]	9857408	1			T1	4		T2	4		T3	2
auto[TlIntgErrNone]	full_word	auto[1]	531151	1			T1	7		T2	3		T3	5
auto[TlIntgErrCmd]	partial	auto[0]	46	1			T248	2		T249	5		T261	4
auto[TlIntgErrCmd]	partial	auto[1]	67	1			T241	4		T248	4		T249	7
auto[TlIntgErrCmd]	full_word	auto[1]	9	1			T331	2		T332	1		T333	1
auto[TlIntgErrData]	partial	auto[0]	50	1			T241	3		T248	4		T249	4
auto[TlIntgErrData]	partial	auto[1]	39	1			T241	3		T248	3		T249	2
auto[TlIntgErrData]	full_word	auto[0]	6	1			T248	1		T261	1		T332	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T241	2		T334	1		T335	1
auto[TlIntgErrBoth]	partial	auto[0]	34	1			T241	5		T248	5		T249	1
auto[TlIntgErrBoth]	partial	auto[1]	44	1			T241	1		T248	1		T261	1
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T241	1		T249	1		T336	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T241	1		T261	2		T332	1