Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

9684729

1

T1

6

T2

11

T3

10

full_word

10269206

1

T1

18

T2

9

T3

8

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	19953575	1			T1	24		T2	20		T3	18
auto[TlIntgErrCmd]	127	1			T202	2		T229	5		T231	4
auto[TlIntgErrData]	121	1			T202	4		T229	8		T231	5
auto[TlIntgErrBoth]	112	1			T202	4		T229	7		T231	1

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19293080

1

T1

17

T2

10

T3

7

auto[1]

660855

1

T1

7

T2

10

T3

11

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	9546904	1			T1	2		T2	8		T3	4
auto[TlIntgErrNone]	partial	auto[1]	137501	1			T1	4		T2	3		T3	6
auto[TlIntgErrNone]	full_word	auto[0]	9746006	1			T1	15		T2	2		T3	3
auto[TlIntgErrNone]	full_word	auto[1]	523164	1			T1	3		T2	7		T3	5
auto[TlIntgErrCmd]	partial	auto[0]	48	1			T202	1		T229	2		T231	3
auto[TlIntgErrCmd]	partial	auto[1]	68	1			T202	1		T229	2		T242	2
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T242	1		T511	1		T509	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T229	1		T231	1		T511	1
auto[TlIntgErrData]	partial	auto[0]	54	1			T202	2		T229	4		T231	3
auto[TlIntgErrData]	partial	auto[1]	51	1			T202	2		T229	2		T231	2
auto[TlIntgErrData]	full_word	auto[0]	8	1			T229	1		T507	1		T510	2
auto[TlIntgErrData]	full_word	auto[1]	8	1			T229	1		T511	1		T508	1
auto[TlIntgErrBoth]	partial	auto[0]	52	1			T202	1		T229	6		T242	4
auto[TlIntgErrBoth]	partial	auto[1]	51	1			T202	3		T229	1		T231	1
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T511	1		T512	1		T513	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T508	1		T509	1		T514	1