Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.15	97.53	93.65	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	582536194	12422	0	0
ep_in_enable_rd_A	582536194	2904	0	0
ep_out_enable_rd_A	582536194	3018	0	0
in_iso_rd_A	582536194	2900	0	0
intr_enable_rd_A	582536194	4224	0	0
out_iso_rd_A	582536194	2961	0	0
phy_config_rd_A	582536194	1741	0	0
phy_pins_drive_rd_A	582536194	2589	0	0
rxenable_setup_rd_A	582536194	3431	0	0
set_nak_out_rd_A	582536194	2947	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	582536194	12422	0	0
T219	2873	11	0	0
T220	3457	478	0	0
T221	14808	1033	0	0
T241	35721	7	0	0
T248	34082	6	0	0
T249	52601	3	0	0
T251	4536	7	0	0
T252	7062	293	0	0
T253	3214	496	0	0
T263	7903	21	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	582536194	2904	0	0
T229	6146	4	0	0
T249	52601	308	0	0
T251	4536	49	0	0
T263	7903	45	0	0
T276	2674	57	0	0
T281	3473	19	0	0
T283	5921	10	0	0
T290	16122	7	0	0
T292	5907	15	0	0
T296	5671	8	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	582536194	3018	0	0
T225	5678	10	0	0
T229	6146	16	0	0
T249	52601	339	0	0
T251	4536	5	0	0
T263	7903	42	0	0
T276	2674	3	0	0
T281	3473	16	0	0
T290	16122	20	0	0
T292	5907	43	0	0
T296	5671	10	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	582536194	2900	0	0
T225	5678	6	0	0
T229	6146	9	0	0
T249	52601	649	0	0
T251	4536	36	0	0
T263	7903	57	0	0
T276	2674	31	0	0
T283	5921	10	0	0
T290	16122	60	0	0
T292	5907	20	0	0
T296	5671	8	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	582536194	4224	0	0
T225	5678	13	0	0
T226	4946	26	0	0
T228	1580	14	0	0
T249	52601	513	0	0
T251	4536	88	0	0
T252	7062	3	0	0
T263	7903	102	0	0
T276	2674	7	0	0
T290	16122	18	0	0
T296	5671	5	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	582536194	2961	0	0
T225	5678	4	0	0
T229	6146	1	0	0
T249	52601	438	0	0
T251	4536	24	0	0
T263	7903	73	0	0
T276	2674	34	0	0
T283	5921	4	0	0
T290	16122	24	0	0
T292	5907	34	0	0
T296	5671	13	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	582536194	1741	0	0
T225	5678	7	0	0
T229	6146	8	0	0
T249	52601	221	0	0
T251	4536	3	0	0
T263	7903	54	0	0
T276	2674	8	0	0
T283	5921	3	0	0
T290	16122	50	0	0
T292	5907	51	0	0
T296	5671	4	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	582536194	2589	0	0
T225	5678	4	0	0
T229	6146	12	0	0
T249	52601	370	0	0
T251	4536	38	0	0
T263	7903	23	0	0
T276	2674	1	0	0
T281	3473	3	0	0
T290	16122	47	0	0
T292	5907	14	0	0
T296	5671	10	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	582536194	3431	0	0
T225	5678	6	0	0
T229	6146	5	0	0
T249	52601	674	0	0
T251	4536	9	0	0
T263	7903	14	0	0
T276	2674	39	0	0
T283	5921	9	0	0
T290	16122	17	0	0
T292	5907	48	0	0
T296	5671	11	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	582536194	2947	0	0
T225	5678	5	0	0
T229	6146	1	0	0
T249	52601	507	0	0
T251	4536	12	0	0
T263	7903	62	0	0
T264	4804	2	0	0
T283	5921	13	0	0
T290	16122	21	0	0
T292	5907	25	0	0
T296	5671	5	0	0