Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.99	97.53	92.86	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	580087033	11246	0	0
ep_in_enable_rd_A	580087033	1645	0	0
ep_out_enable_rd_A	580087033	2004	0	0
in_iso_rd_A	580087033	2084	0	0
intr_enable_rd_A	580087033	2362	0	0
out_iso_rd_A	580087033	1855	0	0
phy_config_rd_A	580087033	1445	0	0
phy_pins_drive_rd_A	580087033	1841	0	0
rxenable_setup_rd_A	580087033	1761	0	0
set_nak_out_rd_A	580087033	1966	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	580087033	11246	0	0
T200	4936	160	0	0
T201	7741	30	0	0
T223	8759	21	0	0
T229	28953	7	0	0
T231	40037	2	0	0
T232	4830	213	0	0
T234	13881	843	0	0
T235	6956	353	0	0
T240	4999	5	0	0
T241	3798	4	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	580087033	1645	0	0
T223	8759	67	0	0
T226	9427	47	0	0
T231	40037	110	0	0
T240	4999	8	0	0
T255	11484	101	0	0
T257	2981	6	0	0
T258	17245	187	0	0
T259	17736	205	0	0
T260	3182	36	0	0
T270	34567	193	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	580087033	2004	0	0
T223	8759	52	0	0
T226	9427	28	0	0
T231	40037	266	0	0
T240	4999	3	0	0
T255	11484	95	0	0
T257	2981	6	0	0
T258	17245	185	0	0
T259	17736	211	0	0
T260	3182	37	0	0
T270	34567	226	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	580087033	2084	0	0
T223	8759	57	0	0
T226	9427	39	0	0
T231	40037	349	0	0
T240	4999	7	0	0
T255	11484	104	0	0
T257	2981	45	0	0
T258	17245	162	0	0
T259	17736	154	0	0
T260	3182	1	0	0
T270	34567	242	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	580087033	2362	0	0
T207	2306	12	0	0
T209	3073	3	0	0
T223	8759	82	0	0
T226	9427	60	0	0
T231	40037	363	0	0
T240	4999	13	0	0
T255	11484	110	0	0
T257	2981	1	0	0
T258	17245	136	0	0
T259	17736	205	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	580087033	1855	0	0
T223	8759	9	0	0
T226	9427	32	0	0
T231	40037	213	0	0
T240	4999	14	0	0
T255	11484	92	0	0
T257	2981	2	0	0
T258	17245	187	0	0
T259	17736	193	0	0
T260	3182	1	0	0
T270	34567	238	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	580087033	1445	0	0
T223	8759	29	0	0
T226	9427	62	0	0
T231	40037	157	0	0
T240	4999	4	0	0
T255	11484	111	0	0
T257	2981	20	0	0
T258	17245	167	0	0
T259	17736	203	0	0
T260	3182	1	0	0
T270	34567	221	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	580087033	1841	0	0
T223	8759	45	0	0
T226	9427	75	0	0
T231	40037	251	0	0
T240	4999	40	0	0
T255	11484	99	0	0
T258	17245	190	0	0
T259	17736	165	0	0
T260	3182	33	0	0
T270	34567	224	0	0
T271	3740	52	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	580087033	1761	0	0
T223	8759	89	0	0
T226	9427	46	0	0
T231	40037	109	0	0
T240	4999	5	0	0
T255	11484	102	0	0
T257	2981	55	0	0
T258	17245	168	0	0
T259	17736	157	0	0
T260	3182	39	0	0
T270	34567	216	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	580087033	1966	0	0
T223	8759	16	0	0
T226	9427	50	0	0
T231	40037	240	0	0
T240	4999	39	0	0
T255	11484	87	0	0
T257	2981	6	0	0
T258	17245	159	0	0
T259	17736	216	0	0
T260	3182	36	0	0
T270	34567	190	0	0