Line Coverage for Module :
usbdev_usbif
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 90 | 90 | 100.00 |
| CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 152 | 0 | 0 | |
| CONT_ASSIGN | 153 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| ALWAYS | 160 | 6 | 6 | 100.00 |
| CONT_ASSIGN | 182 | 1 | 1 | 100.00 |
| ALWAYS | 186 | 6 | 6 | 100.00 |
| ALWAYS | 198 | 11 | 11 | 100.00 |
| CONT_ASSIGN | 218 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 219 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 224 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 227 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 229 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 230 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 231 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 232 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 234 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 240 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 246 | 1 | 1 | 100.00 |
| ALWAYS | 249 | 5 | 5 | 100.00 |
| CONT_ASSIGN | 259 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 261 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 263 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 264 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 269 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 279 | 0 | 0 | |
| CONT_ASSIGN | 280 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 284 | 1 | 1 | 100.00 |
| ALWAYS | 286 | 2 | 2 | 100.00 |
| ALWAYS | 293 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 300 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 301 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 303 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 406 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 407 | 1 | 1 | 100.00 |
| ALWAYS | 410 | 5 | 5 | 100.00 |
| ALWAYS | 419 | 3 | 3 | 100.00 |
| ALWAYS | 459 | 16 | 16 | 100.00 |
| CONT_ASSIGN | 476 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 477 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 478 | 1 | 1 | 100.00 |
133 // Enable pull-up resistor only if VBUS is active
134 1/1 assign usb_pullup_en_o = connect_en_i & usb_sense_i;
Tests: T1 T2 T3
135
136 // OUT or SETUP direction
137 logic [PktW:0] out_max_used_d, out_max_used_q;
138 logic [PktW-1:0] out_ep_put_addr;
139 logic [7:0] out_ep_data;
140
141 logic [3:0] out_ep_current;
142 logic out_ep_newpkt, out_ep_data_put, out_ep_acked, out_ep_rollback;
143 logic current_setup, all_out_blocked;
144 logic [NEndpoints-1:0] out_ep_setup, out_ep_full, out_ep_stall;
145 logic [NEndpoints-1:0] out_blocked;
146 logic [31:0] wdata_q, wdata_d;
147 logic mem_read;
148 logic [SramAw-1:0] mem_waddr, mem_raddr;
149 logic link_reset;
150
151 // Make sure out_endpoint_o can safely be used to index signals of NEndpoints width.
152 unreachable assign out_endpoint_val_o = int'(out_ep_current) < NEndpoints;
153 1/1 assign out_endpoint_o = out_endpoint_val_o ? out_ep_current : '0;
Tests: T1 T2 T3
154
155 1/1 assign link_reset_o = link_reset;
Tests: T1 T2 T3
156 1/1 assign clr_devaddr_o = ~connect_en_i | link_reset;
Tests: T1 T2 T3
157 1/1 assign link_out_err_o = out_ep_rollback;
Tests: T1 T2 T3
158
159 always_comb begin
160 1/1 if (out_ep_acked || out_ep_rollback) begin
Tests: T1 T2 T3
161 1/1 out_max_used_d = 0;
Tests: T1 T2 T18
162
163 1/1 end else if (out_ep_data_put) begin
Tests: T1 T2 T3
164 // In the normal case <MaxPktSizeByte this is out_max_used_q <= out_ep_put_addr
165 // Following all ones out_max_used_q will get 1,00..00 and 1,00..01 to cover
166 // one and two bytes of the CRC overflowing, then stick at 1,00..01
167 1/1 if (int'(out_max_used_q) < MaxPktSizeByte - 1) begin
Tests: T1 T2 T18
168 1/1 out_max_used_d = {1'b0, out_ep_put_addr};
Tests: T1 T2 T18
169 unreachable end else if (int'(out_max_used_q) < MaxPktSizeByte + 1) begin
170 unreachable out_max_used_d = out_max_used_q + 1;
171 end else begin
172 unreachable out_max_used_d = out_max_used_q;
173 end
174
175 end else begin
176 1/1 out_max_used_d = out_max_used_q;
Tests: T1 T2 T3
177 end
178 end // always_comb
179
180 // don't write if the address has wrapped (happens for two CRC bytes after max data)
181 logic std_write_d, std_write_q;
182 1/1 assign std_write_d = out_ep_data_put & ((int'(out_max_used_q) < MaxPktSizeByte - 1) &
Tests: T1 T2 T3
183 (out_ep_put_addr[1:0] == 2'b11));
184
185 always_comb begin
186 1/1 wdata_d = wdata_q;
Tests: T1 T2 T3
187
188 1/1 unique case (out_ep_put_addr[1:0])
Tests: T1 T2 T3
189 1/1 0: wdata_d[7:0] = out_ep_data;
Tests: T1 T2 T3
190 1/1 1: wdata_d[15:8] = out_ep_data;
Tests: T1 T2 T18
191 1/1 2: wdata_d[23:16] = out_ep_data;
Tests: T1 T2 T18
192 1/1 3: wdata_d[31:24] = out_ep_data;
Tests: T1 T2 T18
193 default: wdata_d[7:0] = out_ep_data;
194 endcase
195 end
196
197 always_ff @(posedge clk_48mhz_i or negedge rst_ni) begin
198 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
199 1/1 out_max_used_q <= '0;
Tests: T1 T2 T3
200 1/1 wdata_q <= '0;
Tests: T1 T2 T3
201 1/1 std_write_q <= 1'b0;
Tests: T1 T2 T3
202 1/1 end else if (link_reset) begin
Tests: T1 T2 T3
203 1/1 out_max_used_q <= '0;
Tests: T1 T2 T3
204 1/1 std_write_q <= 1'b0;
Tests: T1 T2 T3
205 end else begin
206 1/1 out_max_used_q <= out_max_used_d;
Tests: T1 T2 T3
207 1/1 std_write_q <= std_write_d;
Tests: T1 T2 T3
208
209 1/1 if (out_ep_data_put) begin
Tests: T1 T2 T3
210 1/1 wdata_q <= wdata_d;
Tests: T1 T2 T18
211 end
MISSING_ELSE
212 end
213 end // always_ff @ (posedge clk_48mhz_i)
214
215 // select from the appropriate Available Buffer FIFO, SETUP or OUT.
216 logic av_rvalid;
217 logic [AVFifoWidth-1:0] av_rdata;
218 1/1 assign av_rvalid = current_setup ? avsetup_rvalid_i : avout_rvalid_i;
Tests: T1 T2 T3
219 1/1 assign av_rdata = current_setup ? avsetup_rdata_i : avout_rdata_i;
Tests: T1 T2 T3
220
221 // only SETUP packets are permitted to fill the RxFIFO completely, ensuring that we can always
222 // receive a SETUP packet even under heavy OUT traffic and high software latency.
223 logic rx_wready;
224 1/1 assign rx_wready = current_setup ? rx_wready_setup_i : rx_wready_out_i;
Tests: T1 T2 T3
225
226 // need extra write at end if packet not multiple of 4 bytes
227 1/1 assign mem_write_o = av_rvalid & (std_write_q |
Tests: T1 T2 T3
228 (~out_max_used_q[PktW] & (out_max_used_q[1:0] != 2'b11) & out_ep_acked));
229 1/1 assign mem_waddr = {av_rdata, out_max_used_q[PktW-1:2]};
Tests: T1 T2 T3
230 1/1 assign mem_wdata_o = wdata_q;
Tests: T1 T2 T3
231 1/1 assign mem_addr_o = mem_write_o ? mem_waddr : mem_raddr;
Tests: T1 T2 T3
232 1/1 assign mem_req_o = mem_read | mem_write_o;
Tests: T1 T2 T3
233 // Is the DATA packet currently being received a SETUP DATA packet or a regular OUT DATA packet?
234 1/1 assign current_setup = out_ep_setup[out_endpoint_o];
Tests: T1 T2 T3
235
236 logic [PktW:0] out_max_minus1;
237 // -2 for CRC bytes but +1 for zero-based address to size
238 1/1 assign out_max_minus1 = out_max_used_q - 1;
Tests: T1 T2 T3
239
240 1/1 assign rx_wdata_o = {
Tests: T1 T2 T3
241 out_endpoint_o,
242 current_setup,
243 out_max_minus1,
244 av_rdata
245 };
246 1/1 assign rx_wvalid_o = out_ep_acked;
Tests: T1 T2 T3
247 // Pop the available fifo after the write that used the previous value
248 always_ff @(posedge clk_48mhz_i or negedge rst_ni) begin
249 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
250 1/1 avsetup_rready_o <= 1'b0;
Tests: T1 T2 T3
251 1/1 avout_rready_o <= 1'b0;
Tests: T1 T2 T3
252 end else begin
253 1/1 avsetup_rready_o <= rx_wvalid_o & current_setup;
Tests: T1 T2 T3
254 1/1 avout_rready_o <= rx_wvalid_o & ~current_setup;
Tests: T1 T2 T3
255 end
256 end
257
258 // full here covers the software blocking by clearing the enable
259 1/1 assign out_blocked = ~out_ep_setup & ~rx_out_i;
Tests: T1 T2 T3
260 // full also covers being blocked because the hardware can't take any transactions at all
261 1/1 assign all_out_blocked = (~rx_wready) | (~av_rvalid);
Tests: T1 T2 T3
262
263 1/1 assign out_ep_full = {NEndpoints{all_out_blocked}} | out_blocked;
Tests: T1 T2 T3
264 1/1 assign out_ep_stall = rx_stall_i;
Tests: T1 T2 T3
265
266 // Need to clear IN read if a SETUP is received because it may use the IN channel
267 // This will not trigger, if the AV Buffer is empty, in that case we have replied
268 // with a NAK, which is illegal anyway
269 1/1 assign setup_received_o = current_setup & rx_wvalid_o;
Tests: T1 T2 T3
270
271 // IN (device to host) transactions
272 logic in_ep_data_get, in_data_done, in_ep_newpkt, pkt_start_rd;
273 logic [NEndpoints-1:0] in_ep_data_done;
274 logic [PktW-1:0] in_ep_get_addr;
275 logic [7:0] in_ep_data;
276 logic [3:0] in_ep_current;
277
278 // Make sure in_endpoint_o can safely be used to index signals of NEndpoints width.
279 unreachable assign in_endpoint_val_o = int'(in_ep_current) < NEndpoints;
280 1/1 assign in_endpoint_o = in_endpoint_val_o ? in_ep_current : '0;
Tests: T1 T2 T3
281
282 // The protocol engine will automatically generate done for a full-length packet
283 // Note: this does the correct thing for sending zero length packets
284 1/1 assign in_data_done = {1'b0, in_ep_get_addr} == in_size_i;
Tests: T1 T2 T3
285 always_comb begin
286 1/1 in_ep_data_done = '0;
Tests: T1 T2 T3
287 1/1 in_ep_data_done[in_endpoint_o] = in_data_done;
Tests: T1 T2 T3
288 end
289
290 // Need extra read at start of packet to get the first word of data
291 // Delay by one cycle from the in_endpoint update
292 always_ff @(posedge clk_48mhz_i or negedge rst_ni) begin
293 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
294 1/1 pkt_start_rd <= 1'b0;
Tests: T1 T2 T3
295 end else begin
296 1/1 pkt_start_rd <= in_ep_newpkt;
Tests: T1 T2 T3
297 end
298 end
299
300 1/1 assign mem_raddr = {in_buf_i,in_ep_get_addr[PktW-1:2]};
Tests: T1 T2 T3
301 1/1 assign mem_read = pkt_start_rd | (in_ep_data_get & (in_ep_get_addr[1:0] == 2'b0));
Tests: T1 T2 T3
302
303 1/1 assign in_ep_data = in_ep_get_addr[1] ?
Tests: T1 T2 T3
304 (in_ep_get_addr[0] ? mem_rdata_i[31:24] : mem_rdata_i[23:16]) :
305 (in_ep_get_addr[0] ? mem_rdata_i[15:8] : mem_rdata_i[7:0]);
306
307 logic sof_valid;
308 logic [10:0] frame_index_raw;
309 logic rx_idle_det;
310 logic rx_j_det;
311
312 usb_fs_nb_pe #(
313 .NumOutEps (NEndpoints),
314 .NumInEps (NEndpoints),
315 .MaxPktSizeByte (MaxPktSizeByte)
316 ) u_usb_fs_nb_pe (
317 .clk_48mhz_i (clk_48mhz_i),
318 .rst_ni (rst_ni),
319 .link_reset_i (link_reset),
320 .link_active_i (link_active_o),
321
322 .cfg_eop_single_bit_i (cfg_eop_single_bit_i),
323 .cfg_use_diff_rcvr_i (cfg_use_diff_rcvr_i),
324 .cfg_pinflip_i (cfg_pinflip_i),
325 .tx_osc_test_mode_i (tx_osc_test_mode_i),
326 .out_data_toggle_o (out_data_toggle_o),
327 .out_datatog_we_i (out_datatog_we_i),
328 .out_datatog_status_i (out_datatog_status_i),
329 .out_datatog_mask_i (out_datatog_mask_i),
330 .in_data_toggle_o (in_data_toggle_o),
331 .in_datatog_we_i (in_datatog_we_i),
332 .in_datatog_status_i (in_datatog_status_i),
333 .in_datatog_mask_i (in_datatog_mask_i),
334 .diff_rx_ok_i (diff_rx_ok_i),
335
336 .usb_d_i (usb_d_i),
337 .usb_dp_i (usb_dp_i),
338 .usb_dn_i (usb_dn_i),
339 .usb_d_o (usb_d_o),
340 .usb_se0_o (usb_se0_o),
341 .usb_dp_o (usb_dp_o),
342 .usb_dn_o (usb_dn_o),
343 .usb_oe_o (usb_oe_o),
344
345 .dev_addr_i (devaddr_i),
346
347 // out endpoint interfaces
348 .out_ep_current_o (out_ep_current),
349 .out_ep_newpkt_o (out_ep_newpkt),
350 .out_ep_data_put_o (out_ep_data_put),
351 .out_ep_put_addr_o (out_ep_put_addr),
352 .out_ep_data_o (out_ep_data),
353 .out_ep_acked_o (out_ep_acked),
354 .out_ep_rollback_o (out_ep_rollback),
355 .out_ep_setup_o (out_ep_setup),
356 .out_ep_enabled_i (out_ep_enabled_i),
357 .out_ep_control_i (rx_setup_i),
358 .out_ep_full_i (out_ep_full),
359 .out_ep_stall_i (out_ep_stall),
360 .out_ep_iso_i (out_ep_iso_i),
361
362 // in endpoint interfaces
363 .in_xact_starting_o (in_xact_starting_o),
364 .in_xact_start_ep_o (in_xact_start_ep_o),
365
366 .in_ep_current_o (in_ep_current),
367 .in_ep_rollback_o (link_in_err_o),
368 .in_ep_xact_end_o (in_ep_xact_end_o),
369 .in_ep_get_addr_o (in_ep_get_addr),
370 .in_ep_data_get_o (in_ep_data_get),
371 .in_ep_newpkt_o (in_ep_newpkt),
372 .in_ep_enabled_i (in_ep_enabled_i),
373 .in_ep_stall_i (in_stall_i),
374 .in_ep_has_data_i (in_rdy_i),
375 .in_ep_data_i (in_ep_data),
376 .in_ep_data_done_i (in_ep_data_done),
377 .in_ep_iso_i (in_ep_iso_i),
378
379 // rx status
380 .rx_idle_det_o (rx_idle_det),
381 .rx_j_det_o (rx_j_det),
382
383 // error signals
384 .rx_crc5_err_o (rx_crc5_err_o),
385 .rx_crc16_err_o (rx_crc16_err_o),
386 .rx_pid_err_o (rx_pid_err_o),
387 .rx_bitstuff_err_o (rx_bitstuff_err_o),
388
389 // sof interface
390 .sof_detected_o (sof_detected_o),
391 .sof_valid_o (sof_valid),
392 .frame_index_o (frame_index_raw),
393
394 // event counters
395 .event_datatog_out_o (event_datatog_out_o),
396 .event_timeout_in_o (event_timeout_in_o),
397 .event_nak_in_o (event_nak_in_o),
398 .event_nodata_in_o (event_nodata_in_o)
399 );
400
401 // Capture frame number (host sends every 1ms)
402 // Generate an internal SOF if the host's is missing.
403 logic do_internal_sof;
404 logic [10:0] frame_d, frame_q;
405
406 1/1 assign frame_o = frame_q;
Tests: T1 T2 T3
407 1/1 assign frame_start_o = (frame_q != frame_d);
Tests: T1 T2 T3
408
409 always_comb begin
410 1/1 frame_d = frame_q;
Tests: T1 T2 T3
411 1/1 if (sof_valid) begin
Tests: T1 T2 T3
412 1/1 frame_d = frame_index_raw;
Tests: T21 T41 T8
413 1/1 end else if (sof_detected_o | do_internal_sof) begin
Tests: T1 T2 T3
414 1/1 frame_d = frame_q + 1;
Tests: T41 T8 T97
415 end
MISSING_ELSE
416 end
417
418 always_ff @(posedge clk_48mhz_i or negedge rst_ni) begin
419 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
420 1/1 frame_q <= '0;
Tests: T1 T2 T3
421 end else begin
422 1/1 frame_q <= frame_d;
Tests: T1 T2 T3
423 end
424 end
425
426 usbdev_linkstate u_usbdev_linkstate (
427 .clk_48mhz_i (clk_48mhz_i),
428 .rst_ni (rst_ni),
429 .us_tick_i (us_tick_i),
430 .usb_sense_i (usb_sense_i),
431 .usb_dp_i (usb_dp_i),
432 .usb_dn_i (usb_dn_i),
433 .usb_oe_i (usb_oe_o),
434 .usb_pullup_en_i (connect_en_i),
435 .rx_idle_det_i (rx_idle_det),
436 .rx_j_det_i (rx_j_det),
437 .sof_detected_i (sof_detected_o),
438 .resume_link_active_i (resume_link_active_i),
439 .link_disconnect_o (link_disconnect_o),
440 .link_powered_o (link_powered_o),
441 .link_reset_o (link_reset),
442 .link_active_o (link_active_o),
443 .link_suspend_o (link_suspend_o),
444 .link_resume_o (link_resume_o),
445 .link_state_o (link_state_o),
446 .host_lost_o (host_lost_o),
447 .sof_missed_o (do_internal_sof)
448 );
449
450 //////////////////////////////////////////////////////////////////////////////////////////////
451 // Count the number of SETUP and OUT packets ignored because there is no available buffer in
452 // the appropriate FIFO, and the number of SETUP/OUT packets dropped because the RX FIFO
453 // will not accept another buffer.
454 //////////////////////////////////////////////////////////////////////////////////////////////
455 logic ign_avsetup;
456 logic drop_avout;
457 logic drop_rx;
458 always_ff @(posedge clk_48mhz_i or negedge rst_ni) begin
459 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
460 1/1 ign_avsetup <= 1'b0;
Tests: T1 T2 T3
461 1/1 drop_avout <= 1'b0;
Tests: T1 T2 T3
462 1/1 drop_rx <= 1'b0;
Tests: T1 T2 T3
463 end else begin
464 // Ignore SETUP packets because no Available SETUP Buffer
465 2/2 if (out_ep_newpkt) ign_avsetup <= 1'b0;
Tests: T1 T2 T3 | T1 T2 T18
466 2/2 else if (out_ep_data_put & current_setup & !avsetup_rvalid_i) ign_avsetup <= 1'b1;
Tests: T1 T2 T3 | T221 T222 T179
MISSING_ELSE
467 // Dropped OUT packets because no Available OUT Buffer
468 2/2 if (out_ep_newpkt) drop_avout <= 1'b0;
Tests: T1 T2 T3 | T1 T2 T18
469 2/2 else if (out_ep_data_put & !current_setup & !avout_rvalid_i) drop_avout <= 1'b1;
Tests: T1 T2 T3 | T30 T66 T67
MISSING_ELSE
470 // Dropped SETUP/OUT packets because no space in RX FIFO
471 2/2 if (out_ep_newpkt) drop_rx <= 1'b0;
Tests: T1 T2 T3 | T1 T2 T18
472 2/2 else if (out_ep_data_put & !rx_wready) drop_rx <= 1'b1;
Tests: T1 T2 T3 | T24 T30 T66
MISSING_ELSE
473 end
474 end
475
476 1/1 assign event_ign_avsetup_o = ign_avsetup;
Tests: T1 T2 T3
477 1/1 assign event_drop_avout_o = drop_avout;
Tests: T1 T2 T3
478 1/1 assign event_drop_rx_o = drop_rx;
Tests: T1 T2 T3
Cond Coverage for Module :
usbdev_usbif
| Total | Covered | Percent |
|---|
| Conditions | 83 | 81 | 97.59 |
| Logical | 83 | 81 | 97.59 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 134
EXPRESSION (connect_en_i & usb_sense_i)
------1----- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T7,T21,T93 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 153
EXPRESSION (out_endpoint_val_o ? out_ep_current : '0)
---------1--------
| -1- | Status | Tests |
|---|
| 0 | Unreachable | |
| 1 | Covered | T1,T2,T3 |
LINE 156
EXPRESSION (((~connect_en_i)) | link_reset)
--------1-------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
LINE 160
EXPRESSION (out_ep_acked || out_ep_rollback)
------1----- -------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T19,T24,T30 |
| 1 | 0 | Covered | T1,T2,T18 |
LINE 182
EXPRESSION (out_ep_data_put & (int'(out_max_used_q) < (MaxPktSizeByte - 1)) & (out_ep_put_addr[1:0] == 2'b11))
-------1------- ----------------------2---------------------- ---------------3---------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T18 |
| 1 | 0 | 1 | Unreachable | T117,T80,T67 |
| 1 | 1 | 0 | Covered | T1,T2,T18 |
| 1 | 1 | 1 | Covered | T1,T2,T18 |
LINE 182
SUB-EXPRESSION (out_ep_put_addr[1:0] == 2'b11)
---------------1---------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T18 |
LINE 218
EXPRESSION (current_setup ? avsetup_rvalid_i : avout_rvalid_i)
------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T24,T82 |
LINE 219
EXPRESSION (current_setup ? avsetup_rdata_i : avout_rdata_i)
------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T24,T82 |
LINE 224
EXPRESSION (current_setup ? rx_wready_setup_i : rx_wready_out_i)
------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T24,T82 |
LINE 227
EXPRESSION (av_rvalid & (std_write_q | (((~out_max_used_q[PktW])) & (out_max_used_q[1:0] != 2'b11) & out_ep_acked)))
----1---- ---------------------------------------------2---------------------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T1,T2,T17 |
| 1 | 1 | Covered | T1,T2,T18 |
LINE 227
SUB-EXPRESSION (std_write_q | (((~out_max_used_q[PktW])) & (out_max_used_q[1:0] != 2'b11) & out_ep_acked))
-----1----- -------------------------------------2-------------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T18 |
| 1 | 0 | Covered | T1,T2,T18 |
LINE 227
SUB-EXPRESSION (((~out_max_used_q[PktW])) & (out_max_used_q[1:0] != 2'b11) & out_ep_acked)
------------1------------ ---------------2-------------- ------3-----
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T117,T80,T67 |
| 1 | 0 | 1 | Covered | T18,T19,T29 |
| 1 | 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | 1 | Covered | T1,T2,T18 |
LINE 227
SUB-EXPRESSION (out_max_used_q[1:0] != 2'b11)
---------------1--------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 231
EXPRESSION (mem_write_o ? mem_waddr : mem_raddr)
-----1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T18 |
LINE 232
EXPRESSION (mem_read | mem_write_o)
----1--- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T18 |
| 1 | 0 | Covered | T18,T19,T29 |
LINE 253
EXPRESSION (rx_wvalid_o & current_setup)
-----1----- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T24,T82 |
| 1 | 0 | Covered | T1,T18,T19 |
| 1 | 1 | Covered | T2,T24,T82 |
LINE 254
EXPRESSION (rx_wvalid_o & ((~current_setup)))
-----1----- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T24,T82 |
| 1 | 1 | Covered | T1,T18,T19 |
LINE 261
EXPRESSION (((~rx_wready)) | ((~av_rvalid)))
-------1------ -------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T17 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T24,T30,T66 |
LINE 269
EXPRESSION (current_setup & rx_wvalid_o)
------1------ -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T18,T19 |
| 1 | 0 | Covered | T2,T24,T82 |
| 1 | 1 | Covered | T2,T24,T82 |
LINE 280
EXPRESSION (in_endpoint_val_o ? in_ep_current : '0)
--------1--------
| -1- | Status | Tests |
|---|
| 0 | Unreachable | |
| 1 | Covered | T1,T2,T3 |
LINE 284
EXPRESSION ({1'b0, in_ep_get_addr} == in_size_i)
------------------1------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 301
EXPRESSION (pkt_start_rd | (in_ep_data_get & (in_ep_get_addr[1:0] == 2'b0)))
------1----- ------------------------2-----------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T19,T29,T31 |
| 1 | 0 | Covered | T18,T19,T29 |
LINE 301
SUB-EXPRESSION (in_ep_data_get & (in_ep_get_addr[1:0] == 2'b0))
-------1------ --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T19,T29,T31 |
| 1 | 1 | Covered | T19,T29,T31 |
LINE 301
SUB-EXPRESSION (in_ep_get_addr[1:0] == 2'b0)
--------------1--------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 303
EXPRESSION (in_ep_get_addr[1] ? (in_ep_get_addr[0] ? mem_rdata_i[31:24] : mem_rdata_i[23:16]) : (in_ep_get_addr[0] ? mem_rdata_i[15:8] : mem_rdata_i[7:0]))
--------1--------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T19,T29,T31 |
LINE 303
SUB-EXPRESSION (in_ep_get_addr[0] ? mem_rdata_i[31:24] : mem_rdata_i[23:16])
--------1--------
| -1- | Status | Tests |
|---|
| 0 | Covered | T19,T29,T31 |
| 1 | Covered | T19,T29,T31 |
LINE 303
SUB-EXPRESSION (in_ep_get_addr[0] ? mem_rdata_i[15:8] : mem_rdata_i[7:0])
--------1--------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T19,T29,T31 |
LINE 407
EXPRESSION (frame_q != frame_d)
----------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T21,T41,T8 |
LINE 413
EXPRESSION (sof_detected_o | do_internal_sof)
-------1------ -------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T41,T8,T97 |
| 1 | 0 | Not Covered | |
LINE 466
EXPRESSION (out_ep_data_put & current_setup & ((!avsetup_rvalid_i)))
-------1------- ------2------ ----------3----------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T2,T24,T82 |
| 1 | 0 | 1 | Covered | T1,T18,T19 |
| 1 | 1 | 0 | Covered | T2,T24,T82 |
| 1 | 1 | 1 | Covered | T221,T222,T179 |
LINE 469
EXPRESSION (out_ep_data_put & ((!current_setup)) & ((!avout_rvalid_i)))
-------1------- ---------2-------- ---------3---------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T2,T24,T82 |
| 1 | 1 | 0 | Covered | T1,T18,T19 |
| 1 | 1 | 1 | Covered | T30,T66,T67 |
LINE 472
EXPRESSION (out_ep_data_put & ((!rx_wready)))
-------1------- -------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T18 |
| 1 | 1 | Covered | T24,T30,T66 |
Branch Coverage for Module :
usbdev_usbif
| Line No. | Total | Covered | Percent |
| Branches |
|
45 |
44 |
97.78 |
| TERNARY |
153 |
1 |
1 |
100.00 |
| TERNARY |
218 |
2 |
2 |
100.00 |
| TERNARY |
219 |
2 |
2 |
100.00 |
| TERNARY |
224 |
2 |
2 |
100.00 |
| TERNARY |
231 |
2 |
2 |
100.00 |
| TERNARY |
280 |
1 |
1 |
100.00 |
| TERNARY |
303 |
4 |
4 |
100.00 |
| IF |
160 |
3 |
3 |
100.00 |
| CASE |
188 |
5 |
4 |
80.00 |
| IF |
198 |
4 |
4 |
100.00 |
| IF |
249 |
2 |
2 |
100.00 |
| IF |
293 |
2 |
2 |
100.00 |
| IF |
411 |
3 |
3 |
100.00 |
| IF |
419 |
2 |
2 |
100.00 |
| IF |
459 |
10 |
10 |
100.00 |
153 assign out_endpoint_o = out_endpoint_val_o ? out_ep_current : '0;
-1-
==>
==> (Unreachable)
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Unreachable |
|
218 assign av_rvalid = current_setup ? avsetup_rvalid_i : avout_rvalid_i;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T24,T82 |
| 0 |
Covered |
T1,T2,T3 |
219 assign av_rdata = current_setup ? avsetup_rdata_i : avout_rdata_i;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T24,T82 |
| 0 |
Covered |
T1,T2,T3 |
224 assign rx_wready = current_setup ? rx_wready_setup_i : rx_wready_out_i;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T24,T82 |
| 0 |
Covered |
T1,T2,T3 |
231 assign mem_addr_o = mem_write_o ? mem_waddr : mem_raddr;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T18 |
| 0 |
Covered |
T1,T2,T3 |
280 assign in_endpoint_o = in_endpoint_val_o ? in_ep_current : '0;
-1-
==>
==> (Unreachable)
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Unreachable |
|
303 assign in_ep_data = in_ep_get_addr[1] ?
-1-
304 (in_ep_get_addr[0] ? mem_rdata_i[31:24] : mem_rdata_i[23:16]) :
-2-
==>
==>
305 (in_ep_get_addr[0] ? mem_rdata_i[15:8] : mem_rdata_i[7:0]);
-3-
==>
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
1 |
- |
Covered |
T19,T29,T31 |
| 1 |
0 |
- |
Covered |
T19,T29,T31 |
| 0 |
- |
1 |
Covered |
T19,T29,T31 |
| 0 |
- |
0 |
Covered |
T1,T2,T3 |
160 if (out_ep_acked || out_ep_rollback) begin
-1-
161 out_max_used_d = 0;
==>
162
163 end else if (out_ep_data_put) begin
-2-
164 // In the normal case -3-
168 out_max_used_d = {1'b0, out_ep_put_addr};
==>
169 end else if (int'(out_max_used_q) < MaxPktSizeByte + 1) begin
-4-
170 out_max_used_d = out_max_used_q + 1;
==> (Unreachable)
171 end else begin
172 out_max_used_d = out_max_used_q;
==> (Unreachable)
173 end
174
175 end else begin
176 out_max_used_d = out_max_used_q;
==>
Branches:
| -1- | -2- | -3- | -4- | Status | Tests |
| 1 |
- |
- |
- |
Covered |
T1,T2,T18 |
| 0 |
1 |
1 |
- |
Covered |
T1,T2,T18 |
| 0 |
1 |
0 |
1 |
Unreachable |
T117,T80,T67 |
| 0 |
1 |
0 |
0 |
Unreachable |
|
| 0 |
0 |
- |
- |
Covered |
T1,T2,T3 |
188 unique case (out_ep_put_addr[1:0])
-1-
189 0: wdata_d[7:0] = out_ep_data;
==>
190 1: wdata_d[15:8] = out_ep_data;
==>
191 2: wdata_d[23:16] = out_ep_data;
==>
192 3: wdata_d[31:24] = out_ep_data;
==>
193 default: wdata_d[7:0] = out_ep_data;
==>
Branches:
| -1- | Status | Tests |
| 0 |
Covered |
T1,T2,T3 |
| 1 |
Covered |
T1,T2,T18 |
| 2 |
Covered |
T1,T2,T18 |
| 3 |
Covered |
T1,T2,T18 |
| default |
Not Covered |
|
198 if (!rst_ni) begin
-1-
199 out_max_used_q <= '0;
==>
200 wdata_q <= '0;
201 std_write_q <= 1'b0;
202 end else if (link_reset) begin
-2-
203 out_max_used_q <= '0;
==>
204 std_write_q <= 1'b0;
205 end else begin
206 out_max_used_q <= out_max_used_d;
207 std_write_q <= std_write_d;
208
209 if (out_ep_data_put) begin
-3-
210 wdata_q <= wdata_d;
==>
211 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T1,T2,T3 |
| 0 |
0 |
1 |
Covered |
T1,T2,T18 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
249 if (!rst_ni) begin
-1-
250 avsetup_rready_o <= 1'b0;
==>
251 avout_rready_o <= 1'b0;
252 end else begin
253 avsetup_rready_o <= rx_wvalid_o & current_setup;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
293 if (!rst_ni) begin
-1-
294 pkt_start_rd <= 1'b0;
==>
295 end else begin
296 pkt_start_rd <= in_ep_newpkt;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
411 if (sof_valid) begin
-1-
412 frame_d = frame_index_raw;
==>
413 end else if (sof_detected_o | do_internal_sof) begin
-2-
414 frame_d = frame_q + 1;
==>
415 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T21,T41,T8 |
| 0 |
1 |
Covered |
T41,T8,T97 |
| 0 |
0 |
Covered |
T1,T2,T3 |
419 if (!rst_ni) begin
-1-
420 frame_q <= '0;
==>
421 end else begin
422 frame_q <= frame_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
459 if (!rst_ni) begin
-1-
460 ign_avsetup <= 1'b0;
==>
461 drop_avout <= 1'b0;
462 drop_rx <= 1'b0;
463 end else begin
464 // Ignore SETUP packets because no Available SETUP Buffer
465 if (out_ep_newpkt) ign_avsetup <= 1'b0;
-2-
==>
466 else if (out_ep_data_put & current_setup & !avsetup_rvalid_i) ign_avsetup <= 1'b1;
-3-
==>
MISSING_ELSE
==>
467 // Dropped OUT packets because no Available OUT Buffer
468 if (out_ep_newpkt) drop_avout <= 1'b0;
-4-
==>
469 else if (out_ep_data_put & !current_setup & !avout_rvalid_i) drop_avout <= 1'b1;
-5-
==>
MISSING_ELSE
==>
470 // Dropped SETUP/OUT packets because no space in RX FIFO
471 if (out_ep_newpkt) drop_rx <= 1'b0;
-6-
==>
472 else if (out_ep_data_put & !rx_wready) drop_rx <= 1'b1;
-7-
==>
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | -4- | -5- | -6- | -7- | Status | Tests |
| 1 |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
- |
- |
- |
- |
Covered |
T1,T2,T18 |
| 0 |
0 |
1 |
- |
- |
- |
- |
Covered |
T221,T222,T179 |
| 0 |
0 |
0 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
- |
- |
1 |
- |
- |
- |
Covered |
T1,T2,T18 |
| 0 |
- |
- |
0 |
1 |
- |
- |
Covered |
T30,T66,T67 |
| 0 |
- |
- |
0 |
0 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
- |
- |
- |
- |
1 |
- |
Covered |
T1,T2,T18 |
| 0 |
- |
- |
- |
- |
0 |
1 |
Covered |
T24,T30,T66 |
| 0 |
- |
- |
- |
- |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
usbdev_usbif
Assertion Details
ParamAVFifoWidthValid
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
3633 |
3633 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T7 |
1 |
1 |
0 |
0 |
| T17 |
1 |
1 |
0 |
0 |
| T18 |
1 |
1 |
0 |
0 |
| T19 |
1 |
1 |
0 |
0 |
| T20 |
1 |
1 |
0 |
0 |
| T21 |
1 |
1 |
0 |
0 |
| T22 |
1 |
1 |
0 |
0 |
ParamMaxPktSizeByteValid
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
3633 |
3633 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T7 |
1 |
1 |
0 |
0 |
| T17 |
1 |
1 |
0 |
0 |
| T18 |
1 |
1 |
0 |
0 |
| T19 |
1 |
1 |
0 |
0 |
| T20 |
1 |
1 |
0 |
0 |
| T21 |
1 |
1 |
0 |
0 |
| T22 |
1 |
1 |
0 |
0 |
ParamNBufValid
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
3633 |
3633 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T7 |
1 |
1 |
0 |
0 |
| T17 |
1 |
1 |
0 |
0 |
| T18 |
1 |
1 |
0 |
0 |
| T19 |
1 |
1 |
0 |
0 |
| T20 |
1 |
1 |
0 |
0 |
| T21 |
1 |
1 |
0 |
0 |
| T22 |
1 |
1 |
0 |
0 |
ParamNEndpointsValid
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
3633 |
3633 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T7 |
1 |
1 |
0 |
0 |
| T17 |
1 |
1 |
0 |
0 |
| T18 |
1 |
1 |
0 |
0 |
| T19 |
1 |
1 |
0 |
0 |
| T20 |
1 |
1 |
0 |
0 |
| T21 |
1 |
1 |
0 |
0 |
| T22 |
1 |
1 |
0 |
0 |
ParamRXFifoWidthValid
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
3633 |
3633 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T7 |
1 |
1 |
0 |
0 |
| T17 |
1 |
1 |
0 |
0 |
| T18 |
1 |
1 |
0 |
0 |
| T19 |
1 |
1 |
0 |
0 |
| T20 |
1 |
1 |
0 |
0 |
| T21 |
1 |
1 |
0 |
0 |
| T22 |
1 |
1 |
0 |
0 |
ParamSramAwValid
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
3633 |
3633 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T7 |
1 |
1 |
0 |
0 |
| T17 |
1 |
1 |
0 |
0 |
| T18 |
1 |
1 |
0 |
0 |
| T19 |
1 |
1 |
0 |
0 |
| T20 |
1 |
1 |
0 |
0 |
| T21 |
1 |
1 |
0 |
0 |
| T22 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.usbdev_impl
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 90 | 90 | 100.00 |
| CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 152 | 0 | 0 | |
| CONT_ASSIGN | 153 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| ALWAYS | 160 | 6 | 6 | 100.00 |
| CONT_ASSIGN | 182 | 1 | 1 | 100.00 |
| ALWAYS | 186 | 6 | 6 | 100.00 |
| ALWAYS | 198 | 11 | 11 | 100.00 |
| CONT_ASSIGN | 218 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 219 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 224 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 227 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 229 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 230 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 231 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 232 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 234 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 240 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 246 | 1 | 1 | 100.00 |
| ALWAYS | 249 | 5 | 5 | 100.00 |
| CONT_ASSIGN | 259 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 261 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 263 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 264 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 269 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 279 | 0 | 0 | |
| CONT_ASSIGN | 280 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 284 | 1 | 1 | 100.00 |
| ALWAYS | 286 | 2 | 2 | 100.00 |
| ALWAYS | 293 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 300 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 301 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 303 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 406 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 407 | 1 | 1 | 100.00 |
| ALWAYS | 410 | 5 | 5 | 100.00 |
| ALWAYS | 419 | 3 | 3 | 100.00 |
| ALWAYS | 459 | 16 | 16 | 100.00 |
| CONT_ASSIGN | 476 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 477 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 478 | 1 | 1 | 100.00 |
133 // Enable pull-up resistor only if VBUS is active
134 1/1 assign usb_pullup_en_o = connect_en_i & usb_sense_i;
Tests: T1 T2 T3
135
136 // OUT or SETUP direction
137 logic [PktW:0] out_max_used_d, out_max_used_q;
138 logic [PktW-1:0] out_ep_put_addr;
139 logic [7:0] out_ep_data;
140
141 logic [3:0] out_ep_current;
142 logic out_ep_newpkt, out_ep_data_put, out_ep_acked, out_ep_rollback;
143 logic current_setup, all_out_blocked;
144 logic [NEndpoints-1:0] out_ep_setup, out_ep_full, out_ep_stall;
145 logic [NEndpoints-1:0] out_blocked;
146 logic [31:0] wdata_q, wdata_d;
147 logic mem_read;
148 logic [SramAw-1:0] mem_waddr, mem_raddr;
149 logic link_reset;
150
151 // Make sure out_endpoint_o can safely be used to index signals of NEndpoints width.
152 unreachable assign out_endpoint_val_o = int'(out_ep_current) < NEndpoints;
153 1/1 assign out_endpoint_o = out_endpoint_val_o ? out_ep_current : '0;
Tests: T1 T2 T3
154
155 1/1 assign link_reset_o = link_reset;
Tests: T1 T2 T3
156 1/1 assign clr_devaddr_o = ~connect_en_i | link_reset;
Tests: T1 T2 T3
157 1/1 assign link_out_err_o = out_ep_rollback;
Tests: T1 T2 T3
158
159 always_comb begin
160 1/1 if (out_ep_acked || out_ep_rollback) begin
Tests: T1 T2 T3
161 1/1 out_max_used_d = 0;
Tests: T1 T2 T18
162
163 1/1 end else if (out_ep_data_put) begin
Tests: T1 T2 T3
164 // In the normal case <MaxPktSizeByte this is out_max_used_q <= out_ep_put_addr
165 // Following all ones out_max_used_q will get 1,00..00 and 1,00..01 to cover
166 // one and two bytes of the CRC overflowing, then stick at 1,00..01
167 1/1 if (int'(out_max_used_q) < MaxPktSizeByte - 1) begin
Tests: T1 T2 T18
168 1/1 out_max_used_d = {1'b0, out_ep_put_addr};
Tests: T1 T2 T18
169 unreachable end else if (int'(out_max_used_q) < MaxPktSizeByte + 1) begin
170 unreachable out_max_used_d = out_max_used_q + 1;
171 end else begin
172 unreachable out_max_used_d = out_max_used_q;
173 end
174
175 end else begin
176 1/1 out_max_used_d = out_max_used_q;
Tests: T1 T2 T3
177 end
178 end // always_comb
179
180 // don't write if the address has wrapped (happens for two CRC bytes after max data)
181 logic std_write_d, std_write_q;
182 1/1 assign std_write_d = out_ep_data_put & ((int'(out_max_used_q) < MaxPktSizeByte - 1) &
Tests: T1 T2 T3
183 (out_ep_put_addr[1:0] == 2'b11));
184
185 always_comb begin
186 1/1 wdata_d = wdata_q;
Tests: T1 T2 T3
187
188 1/1 unique case (out_ep_put_addr[1:0])
Tests: T1 T2 T3
189 1/1 0: wdata_d[7:0] = out_ep_data;
Tests: T1 T2 T3
190 1/1 1: wdata_d[15:8] = out_ep_data;
Tests: T1 T2 T18
191 1/1 2: wdata_d[23:16] = out_ep_data;
Tests: T1 T2 T18
192 1/1 3: wdata_d[31:24] = out_ep_data;
Tests: T1 T2 T18
193 default: wdata_d[7:0] = out_ep_data;
Exclude Annotation: VC_COV_UNR
194 endcase
195 end
196
197 always_ff @(posedge clk_48mhz_i or negedge rst_ni) begin
198 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
199 1/1 out_max_used_q <= '0;
Tests: T1 T2 T3
200 1/1 wdata_q <= '0;
Tests: T1 T2 T3
201 1/1 std_write_q <= 1'b0;
Tests: T1 T2 T3
202 1/1 end else if (link_reset) begin
Tests: T1 T2 T3
203 1/1 out_max_used_q <= '0;
Tests: T1 T2 T3
204 1/1 std_write_q <= 1'b0;
Tests: T1 T2 T3
205 end else begin
206 1/1 out_max_used_q <= out_max_used_d;
Tests: T1 T2 T3
207 1/1 std_write_q <= std_write_d;
Tests: T1 T2 T3
208
209 1/1 if (out_ep_data_put) begin
Tests: T1 T2 T3
210 1/1 wdata_q <= wdata_d;
Tests: T1 T2 T18
211 end
MISSING_ELSE
212 end
213 end // always_ff @ (posedge clk_48mhz_i)
214
215 // select from the appropriate Available Buffer FIFO, SETUP or OUT.
216 logic av_rvalid;
217 logic [AVFifoWidth-1:0] av_rdata;
218 1/1 assign av_rvalid = current_setup ? avsetup_rvalid_i : avout_rvalid_i;
Tests: T1 T2 T3
219 1/1 assign av_rdata = current_setup ? avsetup_rdata_i : avout_rdata_i;
Tests: T1 T2 T3
220
221 // only SETUP packets are permitted to fill the RxFIFO completely, ensuring that we can always
222 // receive a SETUP packet even under heavy OUT traffic and high software latency.
223 logic rx_wready;
224 1/1 assign rx_wready = current_setup ? rx_wready_setup_i : rx_wready_out_i;
Tests: T1 T2 T3
225
226 // need extra write at end if packet not multiple of 4 bytes
227 1/1 assign mem_write_o = av_rvalid & (std_write_q |
Tests: T1 T2 T3
228 (~out_max_used_q[PktW] & (out_max_used_q[1:0] != 2'b11) & out_ep_acked));
229 1/1 assign mem_waddr = {av_rdata, out_max_used_q[PktW-1:2]};
Tests: T1 T2 T3
230 1/1 assign mem_wdata_o = wdata_q;
Tests: T1 T2 T3
231 1/1 assign mem_addr_o = mem_write_o ? mem_waddr : mem_raddr;
Tests: T1 T2 T3
232 1/1 assign mem_req_o = mem_read | mem_write_o;
Tests: T1 T2 T3
233 // Is the DATA packet currently being received a SETUP DATA packet or a regular OUT DATA packet?
234 1/1 assign current_setup = out_ep_setup[out_endpoint_o];
Tests: T1 T2 T3
235
236 logic [PktW:0] out_max_minus1;
237 // -2 for CRC bytes but +1 for zero-based address to size
238 1/1 assign out_max_minus1 = out_max_used_q - 1;
Tests: T1 T2 T3
239
240 1/1 assign rx_wdata_o = {
Tests: T1 T2 T3
241 out_endpoint_o,
242 current_setup,
243 out_max_minus1,
244 av_rdata
245 };
246 1/1 assign rx_wvalid_o = out_ep_acked;
Tests: T1 T2 T3
247 // Pop the available fifo after the write that used the previous value
248 always_ff @(posedge clk_48mhz_i or negedge rst_ni) begin
249 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
250 1/1 avsetup_rready_o <= 1'b0;
Tests: T1 T2 T3
251 1/1 avout_rready_o <= 1'b0;
Tests: T1 T2 T3
252 end else begin
253 1/1 avsetup_rready_o <= rx_wvalid_o & current_setup;
Tests: T1 T2 T3
254 1/1 avout_rready_o <= rx_wvalid_o & ~current_setup;
Tests: T1 T2 T3
255 end
256 end
257
258 // full here covers the software blocking by clearing the enable
259 1/1 assign out_blocked = ~out_ep_setup & ~rx_out_i;
Tests: T1 T2 T3
260 // full also covers being blocked because the hardware can't take any transactions at all
261 1/1 assign all_out_blocked = (~rx_wready) | (~av_rvalid);
Tests: T1 T2 T3
262
263 1/1 assign out_ep_full = {NEndpoints{all_out_blocked}} | out_blocked;
Tests: T1 T2 T3
264 1/1 assign out_ep_stall = rx_stall_i;
Tests: T1 T2 T3
265
266 // Need to clear IN read if a SETUP is received because it may use the IN channel
267 // This will not trigger, if the AV Buffer is empty, in that case we have replied
268 // with a NAK, which is illegal anyway
269 1/1 assign setup_received_o = current_setup & rx_wvalid_o;
Tests: T1 T2 T3
270
271 // IN (device to host) transactions
272 logic in_ep_data_get, in_data_done, in_ep_newpkt, pkt_start_rd;
273 logic [NEndpoints-1:0] in_ep_data_done;
274 logic [PktW-1:0] in_ep_get_addr;
275 logic [7:0] in_ep_data;
276 logic [3:0] in_ep_current;
277
278 // Make sure in_endpoint_o can safely be used to index signals of NEndpoints width.
279 unreachable assign in_endpoint_val_o = int'(in_ep_current) < NEndpoints;
280 1/1 assign in_endpoint_o = in_endpoint_val_o ? in_ep_current : '0;
Tests: T1 T2 T3
281
282 // The protocol engine will automatically generate done for a full-length packet
283 // Note: this does the correct thing for sending zero length packets
284 1/1 assign in_data_done = {1'b0, in_ep_get_addr} == in_size_i;
Tests: T1 T2 T3
285 always_comb begin
286 1/1 in_ep_data_done = '0;
Tests: T1 T2 T3
287 1/1 in_ep_data_done[in_endpoint_o] = in_data_done;
Tests: T1 T2 T3
288 end
289
290 // Need extra read at start of packet to get the first word of data
291 // Delay by one cycle from the in_endpoint update
292 always_ff @(posedge clk_48mhz_i or negedge rst_ni) begin
293 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
294 1/1 pkt_start_rd <= 1'b0;
Tests: T1 T2 T3
295 end else begin
296 1/1 pkt_start_rd <= in_ep_newpkt;
Tests: T1 T2 T3
297 end
298 end
299
300 1/1 assign mem_raddr = {in_buf_i,in_ep_get_addr[PktW-1:2]};
Tests: T1 T2 T3
301 1/1 assign mem_read = pkt_start_rd | (in_ep_data_get & (in_ep_get_addr[1:0] == 2'b0));
Tests: T1 T2 T3
302
303 1/1 assign in_ep_data = in_ep_get_addr[1] ?
Tests: T1 T2 T3
304 (in_ep_get_addr[0] ? mem_rdata_i[31:24] : mem_rdata_i[23:16]) :
305 (in_ep_get_addr[0] ? mem_rdata_i[15:8] : mem_rdata_i[7:0]);
306
307 logic sof_valid;
308 logic [10:0] frame_index_raw;
309 logic rx_idle_det;
310 logic rx_j_det;
311
312 usb_fs_nb_pe #(
313 .NumOutEps (NEndpoints),
314 .NumInEps (NEndpoints),
315 .MaxPktSizeByte (MaxPktSizeByte)
316 ) u_usb_fs_nb_pe (
317 .clk_48mhz_i (clk_48mhz_i),
318 .rst_ni (rst_ni),
319 .link_reset_i (link_reset),
320 .link_active_i (link_active_o),
321
322 .cfg_eop_single_bit_i (cfg_eop_single_bit_i),
323 .cfg_use_diff_rcvr_i (cfg_use_diff_rcvr_i),
324 .cfg_pinflip_i (cfg_pinflip_i),
325 .tx_osc_test_mode_i (tx_osc_test_mode_i),
326 .out_data_toggle_o (out_data_toggle_o),
327 .out_datatog_we_i (out_datatog_we_i),
328 .out_datatog_status_i (out_datatog_status_i),
329 .out_datatog_mask_i (out_datatog_mask_i),
330 .in_data_toggle_o (in_data_toggle_o),
331 .in_datatog_we_i (in_datatog_we_i),
332 .in_datatog_status_i (in_datatog_status_i),
333 .in_datatog_mask_i (in_datatog_mask_i),
334 .diff_rx_ok_i (diff_rx_ok_i),
335
336 .usb_d_i (usb_d_i),
337 .usb_dp_i (usb_dp_i),
338 .usb_dn_i (usb_dn_i),
339 .usb_d_o (usb_d_o),
340 .usb_se0_o (usb_se0_o),
341 .usb_dp_o (usb_dp_o),
342 .usb_dn_o (usb_dn_o),
343 .usb_oe_o (usb_oe_o),
344
345 .dev_addr_i (devaddr_i),
346
347 // out endpoint interfaces
348 .out_ep_current_o (out_ep_current),
349 .out_ep_newpkt_o (out_ep_newpkt),
350 .out_ep_data_put_o (out_ep_data_put),
351 .out_ep_put_addr_o (out_ep_put_addr),
352 .out_ep_data_o (out_ep_data),
353 .out_ep_acked_o (out_ep_acked),
354 .out_ep_rollback_o (out_ep_rollback),
355 .out_ep_setup_o (out_ep_setup),
356 .out_ep_enabled_i (out_ep_enabled_i),
357 .out_ep_control_i (rx_setup_i),
358 .out_ep_full_i (out_ep_full),
359 .out_ep_stall_i (out_ep_stall),
360 .out_ep_iso_i (out_ep_iso_i),
361
362 // in endpoint interfaces
363 .in_xact_starting_o (in_xact_starting_o),
364 .in_xact_start_ep_o (in_xact_start_ep_o),
365
366 .in_ep_current_o (in_ep_current),
367 .in_ep_rollback_o (link_in_err_o),
368 .in_ep_xact_end_o (in_ep_xact_end_o),
369 .in_ep_get_addr_o (in_ep_get_addr),
370 .in_ep_data_get_o (in_ep_data_get),
371 .in_ep_newpkt_o (in_ep_newpkt),
372 .in_ep_enabled_i (in_ep_enabled_i),
373 .in_ep_stall_i (in_stall_i),
374 .in_ep_has_data_i (in_rdy_i),
375 .in_ep_data_i (in_ep_data),
376 .in_ep_data_done_i (in_ep_data_done),
377 .in_ep_iso_i (in_ep_iso_i),
378
379 // rx status
380 .rx_idle_det_o (rx_idle_det),
381 .rx_j_det_o (rx_j_det),
382
383 // error signals
384 .rx_crc5_err_o (rx_crc5_err_o),
385 .rx_crc16_err_o (rx_crc16_err_o),
386 .rx_pid_err_o (rx_pid_err_o),
387 .rx_bitstuff_err_o (rx_bitstuff_err_o),
388
389 // sof interface
390 .sof_detected_o (sof_detected_o),
391 .sof_valid_o (sof_valid),
392 .frame_index_o (frame_index_raw),
393
394 // event counters
395 .event_datatog_out_o (event_datatog_out_o),
396 .event_timeout_in_o (event_timeout_in_o),
397 .event_nak_in_o (event_nak_in_o),
398 .event_nodata_in_o (event_nodata_in_o)
399 );
400
401 // Capture frame number (host sends every 1ms)
402 // Generate an internal SOF if the host's is missing.
403 logic do_internal_sof;
404 logic [10:0] frame_d, frame_q;
405
406 1/1 assign frame_o = frame_q;
Tests: T1 T2 T3
407 1/1 assign frame_start_o = (frame_q != frame_d);
Tests: T1 T2 T3
408
409 always_comb begin
410 1/1 frame_d = frame_q;
Tests: T1 T2 T3
411 1/1 if (sof_valid) begin
Tests: T1 T2 T3
412 1/1 frame_d = frame_index_raw;
Tests: T21 T41 T8
413 1/1 end else if (sof_detected_o | do_internal_sof) begin
Tests: T1 T2 T3
414 1/1 frame_d = frame_q + 1;
Tests: T41 T8 T97
415 end
MISSING_ELSE
416 end
417
418 always_ff @(posedge clk_48mhz_i or negedge rst_ni) begin
419 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
420 1/1 frame_q <= '0;
Tests: T1 T2 T3
421 end else begin
422 1/1 frame_q <= frame_d;
Tests: T1 T2 T3
423 end
424 end
425
426 usbdev_linkstate u_usbdev_linkstate (
427 .clk_48mhz_i (clk_48mhz_i),
428 .rst_ni (rst_ni),
429 .us_tick_i (us_tick_i),
430 .usb_sense_i (usb_sense_i),
431 .usb_dp_i (usb_dp_i),
432 .usb_dn_i (usb_dn_i),
433 .usb_oe_i (usb_oe_o),
434 .usb_pullup_en_i (connect_en_i),
435 .rx_idle_det_i (rx_idle_det),
436 .rx_j_det_i (rx_j_det),
437 .sof_detected_i (sof_detected_o),
438 .resume_link_active_i (resume_link_active_i),
439 .link_disconnect_o (link_disconnect_o),
440 .link_powered_o (link_powered_o),
441 .link_reset_o (link_reset),
442 .link_active_o (link_active_o),
443 .link_suspend_o (link_suspend_o),
444 .link_resume_o (link_resume_o),
445 .link_state_o (link_state_o),
446 .host_lost_o (host_lost_o),
447 .sof_missed_o (do_internal_sof)
448 );
449
450 //////////////////////////////////////////////////////////////////////////////////////////////
451 // Count the number of SETUP and OUT packets ignored because there is no available buffer in
452 // the appropriate FIFO, and the number of SETUP/OUT packets dropped because the RX FIFO
453 // will not accept another buffer.
454 //////////////////////////////////////////////////////////////////////////////////////////////
455 logic ign_avsetup;
456 logic drop_avout;
457 logic drop_rx;
458 always_ff @(posedge clk_48mhz_i or negedge rst_ni) begin
459 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
460 1/1 ign_avsetup <= 1'b0;
Tests: T1 T2 T3
461 1/1 drop_avout <= 1'b0;
Tests: T1 T2 T3
462 1/1 drop_rx <= 1'b0;
Tests: T1 T2 T3
463 end else begin
464 // Ignore SETUP packets because no Available SETUP Buffer
465 2/2 if (out_ep_newpkt) ign_avsetup <= 1'b0;
Tests: T1 T2 T3 | T1 T2 T18
466 2/2 else if (out_ep_data_put & current_setup & !avsetup_rvalid_i) ign_avsetup <= 1'b1;
Tests: T1 T2 T3 | T221 T222 T179
MISSING_ELSE
467 // Dropped OUT packets because no Available OUT Buffer
468 2/2 if (out_ep_newpkt) drop_avout <= 1'b0;
Tests: T1 T2 T3 | T1 T2 T18
469 2/2 else if (out_ep_data_put & !current_setup & !avout_rvalid_i) drop_avout <= 1'b1;
Tests: T1 T2 T3 | T30 T66 T67
MISSING_ELSE
470 // Dropped SETUP/OUT packets because no space in RX FIFO
471 2/2 if (out_ep_newpkt) drop_rx <= 1'b0;
Tests: T1 T2 T3 | T1 T2 T18
472 2/2 else if (out_ep_data_put & !rx_wready) drop_rx <= 1'b1;
Tests: T1 T2 T3 | T24 T30 T66
MISSING_ELSE
473 end
474 end
475
476 1/1 assign event_ign_avsetup_o = ign_avsetup;
Tests: T1 T2 T3
477 1/1 assign event_drop_avout_o = drop_avout;
Tests: T1 T2 T3
478 1/1 assign event_drop_rx_o = drop_rx;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.usbdev_impl
| Total | Covered | Percent |
|---|
| Conditions | 82 | 81 | 98.78 |
| Logical | 82 | 81 | 98.78 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 134
EXPRESSION (connect_en_i & usb_sense_i)
------1----- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T7,T21,T93 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 153
EXPRESSION (out_endpoint_val_o ? out_ep_current : '0)
---------1--------
| -1- | Status | Tests |
|---|
| 0 | Unreachable | |
| 1 | Covered | T1,T2,T3 |
LINE 156
EXPRESSION (((~connect_en_i)) | link_reset)
--------1-------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
LINE 160
EXPRESSION (out_ep_acked || out_ep_rollback)
------1----- -------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T19,T24,T30 |
| 1 | 0 | Covered | T1,T2,T18 |
LINE 182
EXPRESSION (out_ep_data_put & (int'(out_max_used_q) < (MaxPktSizeByte - 1)) & (out_ep_put_addr[1:0] == 2'b11))
-------1------- ----------------------2---------------------- ---------------3---------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T18 |
| 1 | 0 | 1 | Unreachable | T117,T80,T67 |
| 1 | 1 | 0 | Covered | T1,T2,T18 |
| 1 | 1 | 1 | Covered | T1,T2,T18 |
LINE 182
SUB-EXPRESSION (out_ep_put_addr[1:0] == 2'b11)
---------------1---------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T18 |
LINE 218
EXPRESSION (current_setup ? avsetup_rvalid_i : avout_rvalid_i)
------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T24,T82 |
LINE 219
EXPRESSION (current_setup ? avsetup_rdata_i : avout_rdata_i)
------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T24,T82 |
LINE 224
EXPRESSION (current_setup ? rx_wready_setup_i : rx_wready_out_i)
------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T24,T82 |
LINE 227
EXPRESSION (av_rvalid & (std_write_q | (((~out_max_used_q[PktW])) & (out_max_used_q[1:0] != 2'b11) & out_ep_acked)))
----1---- ---------------------------------------------2---------------------------------------------
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | Excluded | |
DUT shall not write into full FIFO |
| 1 | 0 | Covered | T1,T2,T17 |
| 1 | 1 | Covered | T1,T2,T18 |
LINE 227
SUB-EXPRESSION (std_write_q | (((~out_max_used_q[PktW])) & (out_max_used_q[1:0] != 2'b11) & out_ep_acked))
-----1----- -------------------------------------2-------------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T18 |
| 1 | 0 | Covered | T1,T2,T18 |
LINE 227
SUB-EXPRESSION (((~out_max_used_q[PktW])) & (out_max_used_q[1:0] != 2'b11) & out_ep_acked)
------------1------------ ---------------2-------------- ------3-----
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T117,T80,T67 |
| 1 | 0 | 1 | Covered | T18,T19,T29 |
| 1 | 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | 1 | Covered | T1,T2,T18 |
LINE 227
SUB-EXPRESSION (out_max_used_q[1:0] != 2'b11)
---------------1--------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 231
EXPRESSION (mem_write_o ? mem_waddr : mem_raddr)
-----1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T18 |
LINE 232
EXPRESSION (mem_read | mem_write_o)
----1--- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T18 |
| 1 | 0 | Covered | T18,T19,T29 |
LINE 253
EXPRESSION (rx_wvalid_o & current_setup)
-----1----- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T24,T82 |
| 1 | 0 | Covered | T1,T18,T19 |
| 1 | 1 | Covered | T2,T24,T82 |
LINE 254
EXPRESSION (rx_wvalid_o & ((~current_setup)))
-----1----- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T24,T82 |
| 1 | 1 | Covered | T1,T18,T19 |
LINE 261
EXPRESSION (((~rx_wready)) | ((~av_rvalid)))
-------1------ -------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T17 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T24,T30,T66 |
LINE 269
EXPRESSION (current_setup & rx_wvalid_o)
------1------ -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T18,T19 |
| 1 | 0 | Covered | T2,T24,T82 |
| 1 | 1 | Covered | T2,T24,T82 |
LINE 280
EXPRESSION (in_endpoint_val_o ? in_ep_current : '0)
--------1--------
| -1- | Status | Tests |
|---|
| 0 | Unreachable | |
| 1 | Covered | T1,T2,T3 |
LINE 284
EXPRESSION ({1'b0, in_ep_get_addr} == in_size_i)
------------------1------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 301
EXPRESSION (pkt_start_rd | (in_ep_data_get & (in_ep_get_addr[1:0] == 2'b0)))
------1----- ------------------------2-----------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T19,T29,T31 |
| 1 | 0 | Covered | T18,T19,T29 |
LINE 301
SUB-EXPRESSION (in_ep_data_get & (in_ep_get_addr[1:0] == 2'b0))
-------1------ --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T19,T29,T31 |
| 1 | 1 | Covered | T19,T29,T31 |
LINE 301
SUB-EXPRESSION (in_ep_get_addr[1:0] == 2'b0)
--------------1--------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 303
EXPRESSION (in_ep_get_addr[1] ? (in_ep_get_addr[0] ? mem_rdata_i[31:24] : mem_rdata_i[23:16]) : (in_ep_get_addr[0] ? mem_rdata_i[15:8] : mem_rdata_i[7:0]))
--------1--------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T19,T29,T31 |
LINE 303
SUB-EXPRESSION (in_ep_get_addr[0] ? mem_rdata_i[31:24] : mem_rdata_i[23:16])
--------1--------
| -1- | Status | Tests |
|---|
| 0 | Covered | T19,T29,T31 |
| 1 | Covered | T19,T29,T31 |
LINE 303
SUB-EXPRESSION (in_ep_get_addr[0] ? mem_rdata_i[15:8] : mem_rdata_i[7:0])
--------1--------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T19,T29,T31 |
LINE 407
EXPRESSION (frame_q != frame_d)
----------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T21,T41,T8 |
LINE 413
EXPRESSION (sof_detected_o | do_internal_sof)
-------1------ -------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T41,T8,T97 |
| 1 | 0 | Not Covered | |
LINE 466
EXPRESSION (out_ep_data_put & current_setup & ((!avsetup_rvalid_i)))
-------1------- ------2------ ----------3----------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T2,T24,T82 |
| 1 | 0 | 1 | Covered | T1,T18,T19 |
| 1 | 1 | 0 | Covered | T2,T24,T82 |
| 1 | 1 | 1 | Covered | T221,T222,T179 |
LINE 469
EXPRESSION (out_ep_data_put & ((!current_setup)) & ((!avout_rvalid_i)))
-------1------- ---------2-------- ---------3---------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T2,T24,T82 |
| 1 | 1 | 0 | Covered | T1,T18,T19 |
| 1 | 1 | 1 | Covered | T30,T66,T67 |
LINE 472
EXPRESSION (out_ep_data_put & ((!rx_wready)))
-------1------- -------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T18 |
| 1 | 1 | Covered | T24,T30,T66 |
Branch Coverage for Instance : tb.dut.usbdev_impl
| Line No. | Total | Covered | Percent |
| Branches |
|
44 |
44 |
100.00 |
| TERNARY |
153 |
1 |
1 |
100.00 |
| TERNARY |
218 |
2 |
2 |
100.00 |
| TERNARY |
219 |
2 |
2 |
100.00 |
| TERNARY |
224 |
2 |
2 |
100.00 |
| TERNARY |
231 |
2 |
2 |
100.00 |
| TERNARY |
280 |
1 |
1 |
100.00 |
| TERNARY |
303 |
4 |
4 |
100.00 |
| IF |
160 |
3 |
3 |
100.00 |
| CASE |
188 |
4 |
4 |
100.00 |
| IF |
198 |
4 |
4 |
100.00 |
| IF |
249 |
2 |
2 |
100.00 |
| IF |
293 |
2 |
2 |
100.00 |
| IF |
411 |
3 |
3 |
100.00 |
| IF |
419 |
2 |
2 |
100.00 |
| IF |
459 |
10 |
10 |
100.00 |
153 assign out_endpoint_o = out_endpoint_val_o ? out_ep_current : '0;
-1-
==>
==> (Unreachable)
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Unreachable |
|
218 assign av_rvalid = current_setup ? avsetup_rvalid_i : avout_rvalid_i;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T24,T82 |
| 0 |
Covered |
T1,T2,T3 |
219 assign av_rdata = current_setup ? avsetup_rdata_i : avout_rdata_i;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T24,T82 |
| 0 |
Covered |
T1,T2,T3 |
224 assign rx_wready = current_setup ? rx_wready_setup_i : rx_wready_out_i;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T24,T82 |
| 0 |
Covered |
T1,T2,T3 |
231 assign mem_addr_o = mem_write_o ? mem_waddr : mem_raddr;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T18 |
| 0 |
Covered |
T1,T2,T3 |
280 assign in_endpoint_o = in_endpoint_val_o ? in_ep_current : '0;
-1-
==>
==> (Unreachable)
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Unreachable |
|
303 assign in_ep_data = in_ep_get_addr[1] ?
-1-
304 (in_ep_get_addr[0] ? mem_rdata_i[31:24] : mem_rdata_i[23:16]) :
-2-
==>
==>
305 (in_ep_get_addr[0] ? mem_rdata_i[15:8] : mem_rdata_i[7:0]);
-3-
==>
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
1 |
- |
Covered |
T19,T29,T31 |
| 1 |
0 |
- |
Covered |
T19,T29,T31 |
| 0 |
- |
1 |
Covered |
T19,T29,T31 |
| 0 |
- |
0 |
Covered |
T1,T2,T3 |
160 if (out_ep_acked || out_ep_rollback) begin
-1-
161 out_max_used_d = 0;
==>
162
163 end else if (out_ep_data_put) begin
-2-
164 // In the normal case -3-
168 out_max_used_d = {1'b0, out_ep_put_addr};
==>
169 end else if (int'(out_max_used_q) < MaxPktSizeByte + 1) begin
-4-
170 out_max_used_d = out_max_used_q + 1;
==> (Unreachable)
171 end else begin
172 out_max_used_d = out_max_used_q;
==> (Unreachable)
173 end
174
175 end else begin
176 out_max_used_d = out_max_used_q;
==>
Branches:
| -1- | -2- | -3- | -4- | Status | Tests |
| 1 |
- |
- |
- |
Covered |
T1,T2,T18 |
| 0 |
1 |
1 |
- |
Covered |
T1,T2,T18 |
| 0 |
1 |
0 |
1 |
Unreachable |
T117,T80,T67 |
| 0 |
1 |
0 |
0 |
Unreachable |
|
| 0 |
0 |
- |
- |
Covered |
T1,T2,T3 |
188 unique case (out_ep_put_addr[1:0])
-1-
189 0: wdata_d[7:0] = out_ep_data;
==>
190 1: wdata_d[15:8] = out_ep_data;
==>
191 2: wdata_d[23:16] = out_ep_data;
==>
192 3: wdata_d[31:24] = out_ep_data;
==>
193 default: wdata_d[7:0] = out_ep_data;
==> (Excluded)
Exclude Annotation: VC_COV_UNR
Branches:
| -1- | Status | Tests | Exclude Annotation |
| 0 |
Covered |
T1,T2,T3 |
|
| 1 |
Covered |
T1,T2,T18 |
|
| 2 |
Covered |
T1,T2,T18 |
|
| 3 |
Covered |
T1,T2,T18 |
|
| default |
Excluded |
|
VC_COV_UNR |
198 if (!rst_ni) begin
-1-
199 out_max_used_q <= '0;
==>
200 wdata_q <= '0;
201 std_write_q <= 1'b0;
202 end else if (link_reset) begin
-2-
203 out_max_used_q <= '0;
==>
204 std_write_q <= 1'b0;
205 end else begin
206 out_max_used_q <= out_max_used_d;
207 std_write_q <= std_write_d;
208
209 if (out_ep_data_put) begin
-3-
210 wdata_q <= wdata_d;
==>
211 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T1,T2,T3 |
| 0 |
0 |
1 |
Covered |
T1,T2,T18 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
249 if (!rst_ni) begin
-1-
250 avsetup_rready_o <= 1'b0;
==>
251 avout_rready_o <= 1'b0;
252 end else begin
253 avsetup_rready_o <= rx_wvalid_o & current_setup;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
293 if (!rst_ni) begin
-1-
294 pkt_start_rd <= 1'b0;
==>
295 end else begin
296 pkt_start_rd <= in_ep_newpkt;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
411 if (sof_valid) begin
-1-
412 frame_d = frame_index_raw;
==>
413 end else if (sof_detected_o | do_internal_sof) begin
-2-
414 frame_d = frame_q + 1;
==>
415 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T21,T41,T8 |
| 0 |
1 |
Covered |
T41,T8,T97 |
| 0 |
0 |
Covered |
T1,T2,T3 |
419 if (!rst_ni) begin
-1-
420 frame_q <= '0;
==>
421 end else begin
422 frame_q <= frame_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
459 if (!rst_ni) begin
-1-
460 ign_avsetup <= 1'b0;
==>
461 drop_avout <= 1'b0;
462 drop_rx <= 1'b0;
463 end else begin
464 // Ignore SETUP packets because no Available SETUP Buffer
465 if (out_ep_newpkt) ign_avsetup <= 1'b0;
-2-
==>
466 else if (out_ep_data_put & current_setup & !avsetup_rvalid_i) ign_avsetup <= 1'b1;
-3-
==>
MISSING_ELSE
==>
467 // Dropped OUT packets because no Available OUT Buffer
468 if (out_ep_newpkt) drop_avout <= 1'b0;
-4-
==>
469 else if (out_ep_data_put & !current_setup & !avout_rvalid_i) drop_avout <= 1'b1;
-5-
==>
MISSING_ELSE
==>
470 // Dropped SETUP/OUT packets because no space in RX FIFO
471 if (out_ep_newpkt) drop_rx <= 1'b0;
-6-
==>
472 else if (out_ep_data_put & !rx_wready) drop_rx <= 1'b1;
-7-
==>
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | -4- | -5- | -6- | -7- | Status | Tests |
| 1 |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
- |
- |
- |
- |
Covered |
T1,T2,T18 |
| 0 |
0 |
1 |
- |
- |
- |
- |
Covered |
T221,T222,T179 |
| 0 |
0 |
0 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
- |
- |
1 |
- |
- |
- |
Covered |
T1,T2,T18 |
| 0 |
- |
- |
0 |
1 |
- |
- |
Covered |
T30,T66,T67 |
| 0 |
- |
- |
0 |
0 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
- |
- |
- |
- |
1 |
- |
Covered |
T1,T2,T18 |
| 0 |
- |
- |
- |
- |
0 |
1 |
Covered |
T24,T30,T66 |
| 0 |
- |
- |
- |
- |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.usbdev_impl
Assertion Details
ParamAVFifoWidthValid
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
3633 |
3633 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T7 |
1 |
1 |
0 |
0 |
| T17 |
1 |
1 |
0 |
0 |
| T18 |
1 |
1 |
0 |
0 |
| T19 |
1 |
1 |
0 |
0 |
| T20 |
1 |
1 |
0 |
0 |
| T21 |
1 |
1 |
0 |
0 |
| T22 |
1 |
1 |
0 |
0 |
ParamMaxPktSizeByteValid
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
3633 |
3633 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T7 |
1 |
1 |
0 |
0 |
| T17 |
1 |
1 |
0 |
0 |
| T18 |
1 |
1 |
0 |
0 |
| T19 |
1 |
1 |
0 |
0 |
| T20 |
1 |
1 |
0 |
0 |
| T21 |
1 |
1 |
0 |
0 |
| T22 |
1 |
1 |
0 |
0 |
ParamNBufValid
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
3633 |
3633 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T7 |
1 |
1 |
0 |
0 |
| T17 |
1 |
1 |
0 |
0 |
| T18 |
1 |
1 |
0 |
0 |
| T19 |
1 |
1 |
0 |
0 |
| T20 |
1 |
1 |
0 |
0 |
| T21 |
1 |
1 |
0 |
0 |
| T22 |
1 |
1 |
0 |
0 |
ParamNEndpointsValid
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
3633 |
3633 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T7 |
1 |
1 |
0 |
0 |
| T17 |
1 |
1 |
0 |
0 |
| T18 |
1 |
1 |
0 |
0 |
| T19 |
1 |
1 |
0 |
0 |
| T20 |
1 |
1 |
0 |
0 |
| T21 |
1 |
1 |
0 |
0 |
| T22 |
1 |
1 |
0 |
0 |
ParamRXFifoWidthValid
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
3633 |
3633 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T7 |
1 |
1 |
0 |
0 |
| T17 |
1 |
1 |
0 |
0 |
| T18 |
1 |
1 |
0 |
0 |
| T19 |
1 |
1 |
0 |
0 |
| T20 |
1 |
1 |
0 |
0 |
| T21 |
1 |
1 |
0 |
0 |
| T22 |
1 |
1 |
0 |
0 |
ParamSramAwValid
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
3633 |
3633 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T7 |
1 |
1 |
0 |
0 |
| T17 |
1 |
1 |
0 |
0 |
| T18 |
1 |
1 |
0 |
0 |
| T19 |
1 |
1 |
0 |
0 |
| T20 |
1 |
1 |
0 |
0 |
| T21 |
1 |
1 |
0 |
0 |
| T22 |
1 |
1 |
0 |
0 |