Unified Coverage Report :: Module :: usbdev_usbif

Module : usbdev_usbif

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.06	96.55	92.77			90.91	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_usbif.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_impl	95.06	96.55	92.77			90.91	100.00

---

Module Instance : tb.dut.usbdev_impl

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.06	96.55	92.77			90.91	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
86.81	95.32	88.54		60.94	89.23	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
89.84	93.83	70.15	93.58		91.67	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_usb_fs_nb_pe	89.32	96.53	87.74		70.27	92.09	100.00
u_usbdev_linkstate	80.46	88.28	89.41		48.15	76.47	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : usbdev_usbif

	Line No.	Total	Covered	Percent
TOTAL		87	84	96.55
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	152	0	0
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
ALWAYS	160	6	6	100.00
CONT_ASSIGN	182	1	1	100.00
ALWAYS	186	6	6	100.00
ALWAYS	198	8	8	100.00
CONT_ASSIGN	215	1	1	100.00
CONT_ASSIGN	216	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	224	1	1	100.00
CONT_ASSIGN	226	1	1	100.00
CONT_ASSIGN	227	1	1	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	229	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	235	1	1	100.00
CONT_ASSIGN	237	1	1	100.00
CONT_ASSIGN	243	1	1	100.00
ALWAYS	246	5	5	100.00
CONT_ASSIGN	256	1	1	100.00
CONT_ASSIGN	258	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	261	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	276	0	0
CONT_ASSIGN	277	1	1	100.00
CONT_ASSIGN	281	1	1	100.00
ALWAYS	283	2	2	100.00
ALWAYS	290	3	3	100.00
CONT_ASSIGN	297	1	1	100.00
CONT_ASSIGN	298	1	1	100.00
CONT_ASSIGN	300	1	1	100.00
CONT_ASSIGN	403	1	1	100.00
CONT_ASSIGN	404	1	1	100.00
ALWAYS	407	5	5	100.00
ALWAYS	416	3	3	100.00
ALWAYS	456	16	13	81.25
CONT_ASSIGN	473	1	1	100.00
CONT_ASSIGN	474	1	1	100.00
CONT_ASSIGN	475	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_usbif.sv' or '../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_usbif.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
134	1	1
152		unreachable
153	1	1
155	1	1
156	1	1
157	1	1
160	1	1
161	1	1
163	1	1
167	1	1
168	1	1
169		unreachable
170		unreachable
172		unreachable
176	1	1
182	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
198	1	1
199	1	1
200	1	1
201	1	1
203	1	1
204	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
221	1	1
224	1	1
226	1	1
227	1	1
228	1	1
229	1	1
231	1	1
235	1	1
237	1	1
243	1	1
246	1	1
247	1	1
248	1	1
250	1	1
251	1	1
256	1	1
258	1	1
260	1	1
261	1	1
266	1	1
276		unreachable
277	1	1
281	1	1
283	1	1
284	1	1
290	1	1
291	1	1
293	1	1
297	1	1
298	1	1
300	1	1
403	1	1
404	1	1
407	1	1
408	1	1
409	1	1
410	1	1
411	1	1
			MISSING_ELSE
416	1	1
417	1	1
419	1	1
456	1	1
457	1	1
458	1	1
459	1	1
462	2	2
463	1	2
			MISSING_ELSE
465	2	2
466	1	2
			MISSING_ELSE
468	2	2
469	1	2
			MISSING_ELSE
473	1	1
474	1	1
475	1	1

---

Cond Coverage for Module : usbdev_usbif

	Total	Covered	Percent
Conditions	83	77	92.77
Logical	83	77	92.77
Non-Logical	0	0
Event	0	0

 LINE       134
 EXPRESSION (connect_en_i & usb_sense_i)
             ------1-----   -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T8,T9,T11
1	1	Covered	T2,T3,T4

 LINE       153
 EXPRESSION (out_endpoint_val_o ? out_ep_current : '0)
             ---------1--------

-1-	Status	Tests
0	Unreachable
1	Covered	T2,T3,T4

 LINE       156
 EXPRESSION (((~connect_en_i)) | link_reset)
             --------1--------   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       160
 EXPRESSION (out_ep_acked || out_ep_rollback)
             ------1-----    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T96,T97,T98
1	0	Covered	T2,T4,T5

 LINE       182
 EXPRESSION (out_ep_data_put & (int'(out_max_used_q) < (MaxPktSizeByte - 1)) & (out_ep_put_addr[1:0] == 2'b11))
             -------1-------   ----------------------2----------------------   ---------------3---------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Unreachable	T2,T4,T22
1	1	0	Covered	T2,T3,T4
1	1	1	Covered	T2,T3,T4

 LINE       182
 SUB-EXPRESSION (out_ep_put_addr[1:0] == 2'b11)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T4

 LINE       215
 EXPRESSION (current_setup ? avsetup_rvalid_i : avout_rvalid_i)
             ------1------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T19,T37,T38

 LINE       216
 EXPRESSION (current_setup ? avsetup_rdata_i : avout_rdata_i)
             ------1------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T19,T37,T38

 LINE       221
 EXPRESSION (current_setup ? rx_wready_setup_i : rx_wready_out_i)
             ------1------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T19,T37,T38

 LINE       224
 EXPRESSION (av_rvalid & (std_write_q | (((~out_max_used_q[PktW])) & (out_max_used_q[1:0] != 2'b11) & out_ep_acked)))
             ----1----   ---------------------------------------------2---------------------------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       224
 SUB-EXPRESSION (std_write_q | (((~out_max_used_q[PktW])) & (out_max_used_q[1:0] != 2'b11) & out_ep_acked))
                 -----1-----   -------------------------------------2-------------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T4,T5,T17
1	0	Covered	T2,T3,T4

 LINE       224
 SUB-EXPRESSION (((~out_max_used_q[PktW])) & (out_max_used_q[1:0] != 2'b11) & out_ep_acked)
                 ------------1------------   ---------------2--------------   ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T4,T22
1	0	1	Covered	T4,T23,T109
1	1	0	Covered	T2,T3,T4
1	1	1	Covered	T4,T5,T17

 LINE       224
 SUB-EXPRESSION (out_max_used_q[1:0] != 2'b11)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T4

 LINE       228
 EXPRESSION (mem_write_o ? mem_waddr : mem_raddr)
             -----1-----

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T4

 LINE       229
 EXPRESSION (mem_read | mem_write_o)
             ----1---   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T2,T3,T4
1	0	Covered	T4,T5,T17

 LINE       250
 EXPRESSION (rx_wvalid_o & current_setup)
             -----1-----   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T19,T37,T38
1	0	Covered	T2,T4,T5
1	1	Covered	T19,T37,T38

 LINE       251
 EXPRESSION (rx_wvalid_o & ((~current_setup)))
             -----1-----   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T19,T37,T38
1	1	Covered	T2,T4,T5

 LINE       258
 EXPRESSION (((~rx_wready)) | ((~av_rvalid)))
             -------1------   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T2,T3,T4
1	0	Not Covered

 LINE       266
 EXPRESSION (current_setup & rx_wvalid_o)
             ------1------   -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T19,T37,T38
1	1	Covered	T19,T37,T38

 LINE       277
 EXPRESSION (in_endpoint_val_o ? in_ep_current : '0)
             --------1--------

-1-	Status	Tests
0	Unreachable
1	Covered	T2,T3,T4

 LINE       281
 EXPRESSION ({1'b0, in_ep_get_addr} == in_size_i)
            ------------------1------------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T4

 LINE       298
 EXPRESSION (pkt_start_rd | (in_ep_data_get & (in_ep_get_addr[1:0] == 2'b0)))
             ------1-----   ------------------------2-----------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T4,T5,T17
1	0	Covered	T4,T5,T17

 LINE       298
 SUB-EXPRESSION (in_ep_data_get & (in_ep_get_addr[1:0] == 2'b0))
                 -------1------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T4,T5,T17
1	1	Covered	T4,T5,T17

 LINE       298
 SUB-EXPRESSION (in_ep_get_addr[1:0] == 2'b0)
                --------------1--------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T4

 LINE       300
 EXPRESSION (in_ep_get_addr[1] ? (in_ep_get_addr[0] ? mem_rdata_i[31:24] : mem_rdata_i[23:16]) : (in_ep_get_addr[0] ? mem_rdata_i[15:8] : mem_rdata_i[7:0]))
             --------1--------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T4,T5,T17

 LINE       300
 SUB-EXPRESSION (in_ep_get_addr[0] ? mem_rdata_i[31:24] : mem_rdata_i[23:16])
                 --------1--------

-1-	Status	Tests
0	Covered	T4,T5,T17
1	Covered	T4,T5,T17

 LINE       300
 SUB-EXPRESSION (in_ep_get_addr[0] ? mem_rdata_i[15:8] : mem_rdata_i[7:0])
                 --------1--------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T4,T5,T17

 LINE       404
 EXPRESSION (frame_q != frame_d)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T4,T5,T8

 LINE       410
 EXPRESSION (sof_detected_o | do_internal_sof)
             -------1------   -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T4,T5,T15
1	0	Not Covered

 LINE       463
 EXPRESSION (out_ep_data_put & current_setup & ((!avsetup_rvalid_i)))
             -------1-------   ------2------   ----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T19,T37,T38
1	0	1	Covered	T2,T3,T4
1	1	0	Covered	T19,T37,T38
1	1	1	Not Covered

 LINE       466
 EXPRESSION (out_ep_data_put & ((!current_setup)) & ((!avout_rvalid_i)))
             -------1-------   ---------2--------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Covered	T19,T37,T38
1	1	0	Covered	T2,T3,T4
1	1	1	Not Covered

 LINE       469
 EXPRESSION (out_ep_data_put & ((!rx_wready)))
             -------1-------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4
1	1	Not Covered

---

Branch Coverage for Module : usbdev_usbif

	Line No.	Total	Covered	Percent
Branches		44	40	90.91
TERNARY	153	1	1	100.00
TERNARY	215	2	2	100.00
TERNARY	216	2	2	100.00
TERNARY	221	2	2	100.00
TERNARY	228	2	2	100.00
TERNARY	277	1	1	100.00
TERNARY	300	4	4	100.00
IF	160	3	3	100.00
CASE	188	5	4	80.00
IF	198	3	3	100.00
IF	246	2	2	100.00
IF	290	2	2	100.00
IF	408	3	3	100.00
IF	416	2	2	100.00
IF	456	10	7	70.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_usbif.sv' or '../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_usbif.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	153	(out_endpoint_val_o) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Unreachable

	LineNo.	Expression
-1-:	215	(current_setup) ? 

Branches:

-1-	Status	Tests
1	Covered	T19,T37,T38
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	216	(current_setup) ? 

Branches:

-1-	Status	Tests
1	Covered	T19,T37,T38
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	221	(current_setup) ? 

Branches:

-1-	Status	Tests
1	Covered	T19,T37,T38
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	228	(mem_write_o) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	277	(in_endpoint_val_o) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Unreachable

	LineNo.	Expression
-1-:	300	(in_ep_get_addr[1]) ? 
-2-:	300	(in_ep_get_addr[0]) ? 
-3-:	300	(in_ep_get_addr[0]) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T4,T5,T17
1	0	-	Covered	T4,T5,T17
0	-	1	Covered	T4,T5,T17
0	-	0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	160	if ((out_ep_acked || out_ep_rollback))
-2-:	163	if (out_ep_data_put)
-3-:	167	if ((int'(out_max_used_q) < (MaxPktSizeByte - 1)))
-4-:	169	if ((int'(out_max_used_q) < (MaxPktSizeByte + 1)))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T2,T4,T5
0	1	1	-	Covered	T2,T3,T4
0	1	0	1	Unreachable	T2,T4,T22
0	1	0	0	Unreachable
0	0	-	-	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	188	case (out_ep_put_addr[1:0])

Branches:

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T4
2	Covered	T2,T3,T4
3	Covered	T2,T3,T4
default	Not Covered

	LineNo.	Expression
-1-:	198	if ((!rst_ni))
-2-:	206	if (out_ep_data_put)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T4
0	1	Covered	T2,T3,T4
0	0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	246	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	290	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	408	if (sof_valid)
-2-:	410	if ((sof_detected_o | do_internal_sof))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T8,T9,T10
0	1	Covered	T4,T5,T15
0	0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	416	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	456	if ((!rst_ni))
-2-:	462	if (out_ep_newpkt)
-3-:	463	if (((out_ep_data_put & current_setup) & (!avsetup_rvalid_i)))
-4-:	465	if (out_ep_newpkt)
-5-:	466	if (((out_ep_data_put & (!current_setup)) & (!avout_rvalid_i)))
-6-:	468	if (out_ep_newpkt)
-7-:	469	if ((out_ep_data_put & (!rx_wready)))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
1	-	-	-	-	-	-	Covered	T2,T3,T4
0	1	-	-	-	-	-	Covered	T2,T3,T4
0	0	1	-	-	-	-	Not Covered
0	0	0	-	-	-	-	Covered	T2,T3,T4
0	-	-	1	-	-	-	Covered	T2,T3,T4
0	-	-	0	1	-	-	Not Covered
0	-	-	0	0	-	-	Covered	T2,T3,T4
0	-	-	-	-	1	-	Covered	T2,T3,T4
0	-	-	-	-	0	1	Not Covered
0	-	-	-	-	0	0	Covered	T2,T3,T4

---

Assert Coverage for Module : usbdev_usbif

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ParamAVFifoWidthValid	1693	1693	0	0
ParamMaxPktSizeByteValid	1693	1693	0	0
ParamNBufValid	1693	1693	0	0
ParamNEndpointsValid	1693	1693	0	0
ParamRXFifoWidthValid	1693	1693	0	0
ParamSramAwValid	1693	1693	0	0

ParamAVFifoWidthValid

Name	Attempts	Real Successes	Failures	Incomplete
Total	1693	1693	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

ParamMaxPktSizeByteValid

Name	Attempts	Real Successes	Failures	Incomplete
Total	1693	1693	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

ParamNBufValid

Name	Attempts	Real Successes	Failures	Incomplete
Total	1693	1693	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

ParamNEndpointsValid

Name	Attempts	Real Successes	Failures	Incomplete
Total	1693	1693	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

ParamRXFifoWidthValid

Name	Attempts	Real Successes	Failures	Incomplete
Total	1693	1693	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

ParamSramAwValid

Name	Attempts	Real Successes	Failures	Incomplete
Total	1693	1693	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0