3df77bec1| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | chip_sw_uart_tx_rx | chip_sw_uart_tx_rx | 17.632m | 5.254ms | 5 | 5 | 100.00 |
| V1 | chip_sw_uart_rx_overflow | chip_sw_uart_tx_rx | 17.632m | 5.254ms | 5 | 5 | 100.00 |
| chip_sw_uart_tx_rx_idx1 | 17.357m | 5.582ms | 5 | 5 | 100.00 | ||
| chip_sw_uart_tx_rx_idx2 | 19.035m | 6.238ms | 5 | 5 | 100.00 | ||
| chip_sw_uart_tx_rx_idx3 | 16.236m | 5.081ms | 5 | 5 | 100.00 | ||
| V1 | chip_sw_uart_rand_baudrate | chip_sw_uart_rand_baudrate | 46.228m | 13.644ms | 20 | 20 | 100.00 |
| V1 | chip_sw_uart_tx_rx_alt_clk_freq | chip_sw_uart_tx_rx_alt_clk_freq | 1.025h | 23.454ms | 5 | 5 | 100.00 |
| chip_sw_uart_tx_rx_alt_clk_freq_low_speed | 26.999m | 13.153ms | 5 | 5 | 100.00 | ||
| V1 | chip_sw_gpio_out | chip_sw_gpio | 9.277m | 3.821ms | 3 | 3 | 100.00 |
| V1 | chip_sw_gpio_in | chip_sw_gpio | 9.277m | 3.821ms | 3 | 3 | 100.00 |
| V1 | chip_sw_gpio_irq | chip_sw_gpio | 9.277m | 3.821ms | 3 | 3 | 100.00 |
| V1 | chip_sw_example_tests | chip_sw_example_flash | 4.373m | 3.103ms | 3 | 3 | 100.00 |
| chip_sw_example_rom | 2.608m | 2.603ms | 3 | 3 | 100.00 | ||
| chip_sw_example_manufacturer | 3.777m | 3.076ms | 3 | 3 | 100.00 | ||
| chip_sw_example_concurrency | 5.146m | 2.815ms | 3 | 3 | 100.00 | ||
| chip_sw_uart_smoketest_signed | 31.421m | 8.356ms | 3 | 3 | 100.00 | ||
| V1 | csr_hw_reset | chip_csr_hw_reset | 5.737m | 7.269ms | 5 | 5 | 100.00 |
| V1 | csr_rw | chip_csr_rw | 10.550m | 5.036ms | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | chip_csr_bit_bash | 50.860m | 27.812ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | chip_csr_aliasing | 2.697h | 66.463ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | chip_csr_mem_rw_with_rand_reset | 6.808m | 8.378ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | chip_csr_aliasing | 2.697h | 66.463ms | 5 | 5 | 100.00 |
| chip_csr_rw | 10.550m | 5.036ms | 20 | 20 | 100.00 | ||
| V1 | xbar_smoke | xbar_smoke | 12.280s | 234.621us | 100 | 100 | 100.00 |
| V1 | TOTAL | 223 | 223 | 100.00 | |||
| V2 | chip_sw_spi_device_tx_rx | chip_sw_spi_device_tx_rx | 7.855m | 3.676ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_flash_mode | chip_sw_uart_tx_rx_bootstrap | 2.644h | 59.091ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_pass_through | chip_sw_spi_device_pass_through | 13.802m | 7.857ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_pass_through_collision | chip_sw_spi_device_pass_through_collision | 9.893m | 4.222ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_tpm | chip_sw_spi_device_tpm | 5.867m | 3.577ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_host_tx_rx | chip_sw_spi_host_tx_rx | 4.338m | 2.806ms | 3 | 3 | 100.00 |
| V2 | chip_sw_i2c_host_tx_rx | chip_sw_i2c_host_tx_rx | 9.156m | 4.935ms | 3 | 3 | 100.00 |
| chip_sw_i2c_host_tx_rx_idx1 | 9.914m | 3.790ms | 3 | 3 | 100.00 | ||
| chip_sw_i2c_host_tx_rx_idx2 | 10.991m | 4.779ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_i2c_device_tx_rx | chip_sw_i2c_device_tx_rx | 10.626m | 5.020ms | 3 | 3 | 100.00 |
| V2 | chip_sw_usbdev_dpi | chip_sw_usbdev_dpi | 28.049m | 8.057ms | 1 | 1 | 100.00 |
| V2 | chip_pin_mux | chip_padctrl_attributes | 6.431m | 5.165ms | 10 | 10 | 100.00 |
| V2 | chip_padctrl_attributes | chip_padctrl_attributes | 6.431m | 5.165ms | 10 | 10 | 100.00 |
| V2 | chip_sw_sleep_pin_mio_dio_val | chip_sw_sleep_pin_mio_dio_val | 6.090m | 3.312ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sleep_pin_wake | chip_sw_sleep_pin_wake | 6.012m | 3.815ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sleep_pin_retention | chip_sw_sleep_pin_retention | 5.697m | 3.768ms | 3 | 3 | 100.00 |
| V2 | chip_sw_tap_strap_sampling | chip_tap_straps_dev | 28.281m | 17.150ms | 5 | 5 | 100.00 |
| chip_tap_straps_testunlock0 | 6.587m | 5.366ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_rma | 10.916m | 7.555ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_prod | 22.980m | 15.997ms | 5 | 5 | 100.00 | ||
| V2 | chip_sw_pattgen_ios | chip_sw_pattgen_ios | 4.503m | 2.367ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sleep_pwm_pulses | chip_sw_sleep_pwm_pulses | 20.982m | 8.443ms | 3 | 3 | 100.00 |
| V2 | chip_sw_data_integrity | chip_sw_data_integrity_escalation | 12.452m | 5.799ms | 5 | 6 | 83.33 |
| V2 | chip_sw_instruction_integrity | chip_sw_data_integrity_escalation | 12.452m | 5.799ms | 5 | 6 | 83.33 |
| V2 | chip_jtag_csr_rw | chip_jtag_csr_rw | 20.079m | 12.232ms | 3 | 3 | 100.00 |
| V2 | chip_jtag_mem_access | chip_jtag_mem_access | 26.192m | 12.888ms | 3 | 3 | 100.00 |
| V2 | chip_rv_dm_ndm_reset_req | chip_rv_dm_ndm_reset_req | 6.393m | 4.485ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | 8.694m | 5.352ms | 3 | 3 | 100.00 |
| V2 | chip_rv_dm_access_after_wakeup | chip_sw_rv_dm_access_after_wakeup | 8.223m | 5.467ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_dm_jtag_tap_sel | chip_tap_straps_rma | 10.916m | 7.555ms | 5 | 5 | 100.00 |
| V2 | chip_rv_dm_lc_disabled | chip_rv_dm_lc_disabled | 6.903m | 10.990ms | 3 | 3 | 100.00 |
| V2 | chip_sw_timer | chip_sw_rv_timer_irq | 4.550m | 3.125ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wakeup_irq | chip_sw_aon_timer_irq | 6.879m | 4.434ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_sleep_wakeup | chip_sw_pwrmgr_smoketest | 6.766m | 4.685ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wdog_bark_irq | chip_sw_aon_timer_irq | 6.879m | 4.434ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wdog_lc_escalate | chip_sw_aon_timer_wdog_lc_escalate | 8.788m | 4.537ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wdog_bite_reset | chip_sw_aon_timer_wdog_bite_reset | 16.323m | 7.252ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_sleep_wdog_bite_reset | chip_sw_aon_timer_wdog_bite_reset | 16.323m | 7.252ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_sleep_wdog_sleep_pause | chip_sw_aon_timer_sleep_wdog_sleep_pause | 6.829m | 7.144ms | 5 | 5 | 100.00 |
| V2 | chip_sw_plic_all_irqs | chip_plic_all_irqs | 24.648m | 7.626ms | 3 | 3 | 100.00 |
| V2 | chip_sw_plic_sw_irq | chip_sw_plic_sw_irq | 4.497m | 2.696ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_idle_trans | chip_sw_otbn_randomness | 10.370m | 6.383ms | 3 | 3 | 100.00 |
| chip_sw_aes_idle | 4.031m | 3.330ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_idle | 5.625m | 2.639ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_idle | 3.754m | 2.278ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_off_trans | chip_sw_clkmgr_off_aes_trans | 8.083m | 5.421ms | 3 | 3 | 100.00 |
| chip_sw_clkmgr_off_hmac_trans | 6.670m | 5.170ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_off_kmac_trans | 7.878m | 4.221ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_off_otbn_trans | 7.347m | 4.235ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_off_peri | chip_sw_clkmgr_off_peri | 20.290m | 11.938ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_div | chip_sw_clkmgr_external_clk_src_for_lc | 17.729m | 14.088ms | 3 | 3 | 100.00 |
| chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 | 11.808m | 4.324ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 | 11.792m | 5.256ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 10.436m | 4.311ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 10.511m | 4.425ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_rma | 13.159m | 4.117ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_rma | 12.409m | 4.721ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_external_clk_src_for_lc | chip_sw_clkmgr_external_clk_src_for_lc | 17.729m | 14.088ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_external_clk_src_for_sw | chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 | 11.808m | 4.324ms | 3 | 3 | 100.00 |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 | 11.792m | 5.256ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 10.436m | 4.311ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 10.511m | 4.425ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_rma | 13.159m | 4.117ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_rma | 12.409m | 4.721ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_jitter | chip_sw_flash_ctrl_ops_jitter_en | 15.853m | 4.556ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_access_jitter_en | 18.764m | 6.206ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 58.066m | 21.029ms | 3 | 3 | 100.00 | ||
| chip_sw_aes_enc_jitter_en | 5.824m | 2.400ms | 3 | 3 | 100.00 | ||
| chip_sw_edn_entropy_reqs_jitter | 15.752m | 5.010ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_jitter_en | 6.408m | 2.786ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation_jitter_en | 8.173m | 4.594ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 5.707m | 3.342ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 8.601m | 4.554ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_jitter | 3.843m | 2.728ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_extended_range | chip_sw_clkmgr_jitter_reduced_freq | 3.626m | 3.251ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_ops_jitter_en_reduced_freq | 17.407m | 6.435ms | 3 | 3 | 100.00 | ||
| chip_sw_flash_ctrl_access_jitter_en_reduced_freq | 19.572m | 8.053ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq | 55.697m | 28.033ms | 3 | 3 | 100.00 | ||
| chip_sw_aes_enc_jitter_en_reduced_freq | 4.299m | 3.143ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_jitter_en_reduced_freq | 4.944m | 3.427ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation_jitter_en_reduced_freq | 7.311m | 5.503ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en_reduced_freq | 6.087m | 2.850ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq | 8.675m | 4.970ms | 3 | 3 | 100.00 | ||
| chip_sw_flash_init_reduced_freq | 33.960m | 20.185ms | 3 | 3 | 100.00 | ||
| chip_sw_csrng_edn_concurrency_reduced_freq | 40.863m | 13.124ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_deep_sleep_frequency | chip_sw_ast_clk_outputs | 17.656m | 7.519ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_sleep_frequency | chip_sw_clkmgr_sleep_frequency | 10.307m | 4.757ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_reset_frequency | chip_sw_clkmgr_reset_frequency | 6.817m | 3.639ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_escalation_reset | chip_sw_all_escalation_resets | 13.911m | 5.196ms | 100 | 100 | 100.00 |
| V2 | chip_sw_pwrmgr_external_full_reset | chip_sw_pwrmgr_full_aon_reset | 8.524m | 7.438ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_random_sleep_all_wake_ups | chip_sw_pwrmgr_random_sleep_all_wake_ups | 29.336m | 19.999ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_normal_sleep_all_wake_ups | chip_sw_pwrmgr_normal_sleep_all_wake_ups | 7.291m | 7.800ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sleep_all_reset_reqs | chip_sw_aon_timer_wdog_bite_reset | 16.323m | 7.252ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_all_wake_ups | chip_sw_pwrmgr_deep_sleep_all_wake_ups | 22.487m | 16.194ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_all_reset_reqs | chip_sw_pwrmgr_deep_sleep_all_reset_reqs | 36.152m | 22.065ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_normal_sleep_all_reset_reqs | chip_sw_pwrmgr_normal_sleep_all_reset_reqs | 34.711m | 15.368ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_wdog_reset | chip_sw_pwrmgr_wdog_reset | 7.650m | 4.491ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_aon_power_glitch_reset | chip_sw_pwrmgr_full_aon_reset | 8.524m | 7.438ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_main_power_glitch_reset | chip_sw_pwrmgr_main_power_glitch_reset | 8.570m | 3.673ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_random_sleep_power_glitch_reset | chip_sw_pwrmgr_random_sleep_power_glitch_reset | 57.255m | 48.132ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_power_glitch_reset | chip_sw_pwrmgr_deep_sleep_power_glitch_reset | 8.552m | 6.224ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sleep_power_glitch_reset | chip_sw_pwrmgr_sleep_power_glitch_reset | 8.014m | 5.892ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_random_sleep_all_reset_reqs | chip_sw_pwrmgr_random_sleep_all_reset_reqs | 44.096m | 38.214ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sysrst_ctrl_reset | chip_sw_pwrmgr_sysrst_ctrl_reset | 19.717m | 7.101ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_b2b_sleep_reset_req | chip_sw_pwrmgr_b2b_sleep_reset_req | 33.487m | 20.122ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sleep_disabled | chip_sw_pwrmgr_sleep_disabled | 5.330m | 2.863ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_escalation_reset | chip_sw_all_escalation_resets | 13.911m | 5.196ms | 100 | 100 | 100.00 |
| V2 | chip_sw_rstmgr_non_sys_reset_info | chip_sw_pwrmgr_smoketest | 6.766m | 4.685ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_sys_reset_info | chip_rv_dm_ndm_reset_req | 6.393m | 4.485ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_cpu_info | chip_sw_rstmgr_cpu_info | 12.947m | 7.732ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_sw_req_reset | chip_sw_rstmgr_sw_req | 7.921m | 4.589ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_alert_info | chip_sw_rstmgr_alert_info | 35.188m | 12.703ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_sw_rst | chip_sw_rstmgr_sw_rst | 5.715m | 3.002ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_escalation_reset | chip_sw_all_escalation_resets | 13.911m | 5.196ms | 100 | 100 | 100.00 |
| V2 | chip_sw_alert_handler_alerts | chip_sw_alert_test | 6.776m | 3.495ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_escalations | chip_sw_alert_handler_escalation | 10.081m | 5.613ms | 3 | 3 | 100.00 |
| V2 | chip_sw_all_escalation_resets | chip_sw_all_escalation_resets | 13.911m | 5.196ms | 100 | 100 | 100.00 |
| V2 | chip_sw_alert_handler_irqs | chip_plic_all_irqs | 24.648m | 7.626ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_entropy | chip_sw_alert_handler_entropy | 6.285m | 2.910ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_crashdump | chip_sw_rstmgr_alert_info | 35.188m | 12.703ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_ping_timeout | chip_sw_alert_handler_ping_timeout | 6.331m | 4.554ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_sleep_mode_alerts | chip_sw_alert_handler_lpg_sleep_mode_alerts | 10.450m | 3.293ms | 90 | 90 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_sleep_mode_pings | chip_sw_alert_handler_lpg_sleep_mode_pings | 34.837m | 14.012ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_clock_off | chip_sw_alert_handler_lpg_clkoff | 36.860m | 10.696ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_reset_toggle | chip_sw_alert_handler_lpg_reset_toggle | 29.766m | 8.086ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_reverse_ping_in_deep_sleep | chip_sw_alert_handler_reverse_ping_in_deep_sleep | 3.414h | 254.393ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_alert_handler_escalation | chip_sw_alert_handler_escalation | 10.081m | 5.613ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_jtag_access | chip_tap_straps_dev | 28.281m | 17.150ms | 5 | 5 | 100.00 |
| chip_tap_straps_rma | 10.916m | 7.555ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_prod | 22.980m | 15.997ms | 5 | 5 | 100.00 | ||
| V2 | chip_sw_lc_ctrl_otp_hw_cfg | chip_sw_lc_ctrl_otp_hw_cfg | 5.353m | 3.547ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_init | chip_sw_lc_ctrl_transition | 18.092m | 10.022ms | 15 | 15 | 100.00 |
| V2 | chip_sw_lc_ctrl_transitions | chip_sw_lc_ctrl_transition | 18.092m | 10.022ms | 15 | 15 | 100.00 |
| V2 | chip_sw_lc_ctrl_kmac_req | chip_sw_lc_ctrl_transition | 18.092m | 10.022ms | 15 | 15 | 100.00 |
| V2 | chip_sw_lc_ctrl_key_div | chip_sw_keymgr_key_derivation_prod | 7.970m | 4.486ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_broadcast | chip_sw_flash_ctrl_lc_rw_en | 10.680m | 5.901ms | 3 | 3 | 100.00 |
| chip_sw_flash_rma_unlocked | 1.290h | 42.933ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 10.351m | 3.982ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_dev | 21.352m | 9.124ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_prod | 17.673m | 8.286ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_rma | 19.041m | 7.431ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_ctrl_transition | 18.092m | 10.022ms | 15 | 15 | 100.00 | ||
| chip_sw_keymgr_key_derivation | 7.650m | 4.477ms | 3 | 3 | 100.00 | ||
| chip_sw_rom_ctrl_integrity_check | 10.805m | 8.182ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_execution_main | 13.799m | 7.932ms | 3 | 3 | 100.00 | ||
| chip_prim_tl_access | 5.739m | 9.466ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_lc | 17.729m | 14.088ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 | 11.808m | 4.324ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 | 11.792m | 5.256ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 10.436m | 4.311ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 10.511m | 4.425ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_rma | 13.159m | 4.117ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_rma | 12.409m | 4.721ms | 3 | 3 | 100.00 | ||
| chip_tap_straps_dev | 28.281m | 17.150ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_rma | 10.916m | 7.555ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_prod | 22.980m | 15.997ms | 5 | 5 | 100.00 | ||
| chip_rv_dm_lc_disabled | 6.903m | 10.990ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sysrst_ctrl_inputs | chip_sw_sysrst_ctrl_inputs | 5.103m | 3.046ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_outputs | chip_sw_sysrst_ctrl_outputs | 7.000m | 4.133ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_in_irq | chip_sw_sysrst_ctrl_in_irq | 9.863m | 3.902ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_sleep_wakeup | chip_sw_sysrst_ctrl_reset | 32.886m | 21.887ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_reset | chip_sw_sysrst_ctrl_reset | 32.886m | 21.887ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_sleep_reset | chip_sw_sysrst_ctrl_reset | 32.886m | 21.887ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_ec_rst_l | chip_sw_sysrst_ctrl_ec_rst_l | 50.339m | 20.005ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_flash_wp_l | chip_sw_sysrst_ctrl_ec_rst_l | 50.339m | 20.005ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_ulp_z3_wakeup | chip_sw_sysrst_ctrl_ulp_z3_wakeup | 10.129m | 5.739ms | 3 | 3 | 100.00 |
| chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 10.879m | 19.810ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_adc_ctrl_debug_cable_irq | chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 10.879m | 19.810ms | 3 | 3 | 100.00 |
| V2 | chip_sw_adc_ctrl_sleep_debug_cable_wakeup | chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 10.879m | 19.810ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aes_enc | chip_sw_aes_enc | 4.775m | 2.535ms | 3 | 3 | 100.00 |
| chip_sw_aes_enc_jitter_en | 5.824m | 2.400ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_aes_entropy | chip_sw_aes_entropy | 5.217m | 2.748ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aes_idle | chip_sw_aes_idle | 4.031m | 3.330ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aes_sideload | chip_sw_keymgr_sideload_aes | 6.876m | 4.097ms | 3 | 3 | 100.00 |
| V2 | chip_sw_hmac_enc | chip_sw_hmac_enc | 5.412m | 2.940ms | 3 | 3 | 100.00 |
| chip_sw_hmac_enc_jitter_en | 6.408m | 2.786ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_hmac_idle | chip_sw_hmac_enc_idle | 5.625m | 2.639ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_enc | chip_sw_kmac_mode_cshake | 3.305m | 2.635ms | 3 | 3 | 100.00 |
| chip_sw_kmac_mode_kmac | 4.120m | 2.978ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 5.707m | 3.342ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_kmac_app_keymgr | chip_sw_keymgr_key_derivation | 7.650m | 4.477ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_app_lc | chip_sw_lc_ctrl_transition | 18.092m | 10.022ms | 15 | 15 | 100.00 |
| V2 | chip_sw_kmac_app_rom | chip_sw_kmac_app_rom | 5.563m | 2.415ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_entropy | chip_sw_kmac_entropy | 4.240m | 3.553ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_idle | chip_sw_kmac_idle | 3.754m | 2.278ms | 3 | 3 | 100.00 |
| V2 | chip_sw_entropy_src_ast_rng_req | chip_sw_entropy_src_ast_rng_req | 4.827m | 3.024ms | 3 | 3 | 100.00 |
| V2 | chip_sw_entropy_src_csrng | chip_sw_entropy_src_csrng | 23.884m | 7.593ms | 3 | 3 | 100.00 |
| V2 | chip_sw_entropy_src_fuse_en_fw_read | chip_sw_entropy_src_fuse_en_fw_read_test | 9.684m | 4.715ms | 3 | 3 | 100.00 |
| V2 | chip_sw_entropy_src_known_answer_tests | chip_sw_entropy_src_kat_test | 4.519m | 2.963ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_edn_cmd | chip_sw_entropy_src_csrng | 23.884m | 7.593ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_fuse_en_sw_app_read | chip_sw_csrng_fuse_en_sw_app_read_test | 7.546m | 3.661ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_lc_hw_debug_en | chip_sw_csrng_lc_hw_debug_en_test | 10.496m | 5.457ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_known_answer_tests | chip_sw_csrng_kat_test | 4.316m | 2.395ms | 3 | 3 | 100.00 |
| V2 | chip_sw_edn_entropy_reqs | chip_sw_csrng_edn_concurrency | 48.811m | 11.518ms | 3 | 3 | 100.00 |
| chip_sw_edn_entropy_reqs | 20.943m | 5.628ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_keymgr_key_derivation | chip_sw_keymgr_key_derivation | 7.650m | 4.477ms | 3 | 3 | 100.00 |
| chip_sw_keymgr_key_derivation_jitter_en | 8.173m | 4.594ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_keymgr_sideload_kmac | chip_sw_keymgr_sideload_kmac | 9.047m | 4.948ms | 3 | 3 | 100.00 |
| V2 | chip_sw_keymgr_sideload_aes | chip_sw_keymgr_sideload_aes | 6.876m | 4.097ms | 3 | 3 | 100.00 |
| V2 | chip_sw_keymgr_sideload_otbn | chip_sw_keymgr_sideload_otbn | 39.216m | 9.531ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otbn_op | chip_sw_otbn_ecdsa_op_irq | 54.321m | 18.904ms | 3 | 3 | 100.00 |
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 58.066m | 21.029ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otbn_rnd_entropy | chip_sw_otbn_randomness | 10.370m | 6.383ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otbn_urnd_entropy | chip_sw_otbn_randomness | 10.370m | 6.383ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otbn_idle | chip_sw_otbn_randomness | 10.370m | 6.383ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otbn_mem_scramble | chip_sw_otbn_mem_scramble | 7.201m | 4.062ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rom_access | chip_sw_rom_ctrl_integrity_check | 10.805m | 8.182ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rom_ctrl_integrity_check | chip_sw_rom_ctrl_integrity_check | 10.805m | 8.182ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sram_scrambled_access | chip_sw_sram_ctrl_scrambled_access | 7.514m | 5.114ms | 3 | 3 | 100.00 |
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 8.601m | 4.554ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sleep_sram_ret_contents | chip_sw_sleep_sram_ret_contents | 24.305m | 10.565ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sram_execution | chip_sw_sram_ctrl_execution_main | 13.799m | 7.932ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sram_lc_escalation | chip_sw_all_escalation_resets | 13.911m | 5.196ms | 100 | 100 | 100.00 |
| chip_sw_data_integrity_escalation | 12.452m | 5.799ms | 5 | 6 | 83.33 | ||
| V2 | chip_otp_ctrl_init | chip_sw_lc_ctrl_transition | 18.092m | 10.022ms | 15 | 15 | 100.00 |
| V2 | chip_sw_otp_ctrl_keys | chip_sw_flash_init | 34.471m | 21.117ms | 3 | 3 | 100.00 |
| chip_sw_otbn_mem_scramble | 7.201m | 4.062ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation | 7.650m | 4.477ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access | 7.514m | 5.114ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_icache_invalidate | 3.614m | 2.919ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_ctrl_entropy | chip_sw_flash_init | 34.471m | 21.117ms | 3 | 3 | 100.00 |
| chip_sw_otbn_mem_scramble | 7.201m | 4.062ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation | 7.650m | 4.477ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access | 7.514m | 5.114ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_icache_invalidate | 3.614m | 2.919ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_ctrl_program | chip_sw_lc_ctrl_transition | 18.092m | 10.022ms | 15 | 15 | 100.00 |
| V2 | chip_sw_otp_ctrl_program_error | chip_sw_lc_ctrl_program_error | 8.191m | 4.416ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otp_ctrl_hw_cfg | chip_sw_lc_ctrl_otp_hw_cfg | 5.353m | 3.547ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otp_ctrl_lc_signals | chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 10.351m | 3.982ms | 3 | 3 | 100.00 |
| chip_sw_otp_ctrl_lc_signals_dev | 21.352m | 9.124ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_prod | 17.673m | 8.286ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_rma | 19.041m | 7.431ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_ctrl_transition | 18.092m | 10.022ms | 15 | 15 | 100.00 | ||
| chip_prim_tl_access | 5.739m | 9.466ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_prim_tl_access | chip_prim_tl_access | 5.739m | 9.466ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_init | chip_sw_flash_init | 34.471m | 21.117ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_host_access | chip_sw_flash_ctrl_access | 21.467m | 6.019ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_access_jitter_en | 18.764m | 6.206ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_flash_ctrl_ops | chip_sw_flash_ctrl_ops | 15.747m | 4.923ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_ops_jitter_en | 15.853m | 4.556ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_flash_rma_unlocked | chip_sw_flash_rma_unlocked | 1.290h | 42.933ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_scramble | chip_sw_flash_init | 34.471m | 21.117ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_idle_low_power | chip_sw_flash_ctrl_idle_low_power | 5.353m | 3.174ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_keymgr_seeds | chip_sw_keymgr_key_derivation | 7.650m | 4.477ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_creator_seed_sw_rw_en | chip_sw_flash_ctrl_lc_rw_en | 10.680m | 5.901ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_creator_seed_wipe_on_rma | chip_sw_flash_rma_unlocked | 1.290h | 42.933ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_owner_seed_sw_rw_en | chip_sw_flash_ctrl_lc_rw_en | 10.680m | 5.901ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_iso_part_sw_rd_en | chip_sw_flash_ctrl_lc_rw_en | 10.680m | 5.901ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_iso_part_sw_wr_en | chip_sw_flash_ctrl_lc_rw_en | 10.680m | 5.901ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_seed_hw_rd_en | chip_sw_flash_ctrl_lc_rw_en | 10.680m | 5.901ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_escalate_en | chip_sw_all_escalation_resets | 13.911m | 5.196ms | 100 | 100 | 100.00 |
| V2 | chip_sw_flash_prim_tl_access | chip_prim_tl_access | 5.739m | 9.466ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_ctrl_clock_freqs | chip_sw_flash_ctrl_clock_freqs | 18.104m | 5.565ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_ctrl_escalation_reset | chip_sw_flash_crash_alert | 11.552m | 5.752ms | 3 | 3 | 100.00 |
| V2 | chip_sw_ast_clk_outputs | chip_sw_ast_clk_outputs | 17.656m | 7.519ms | 3 | 3 | 100.00 |
| V2 | chip_sw_ast_clk_rst_inputs | chip_sw_ast_clk_rst_inputs | 11.711m | 11.362ms | 3 | 3 | 100.00 |
| V2 | chip_sw_ast_sys_clk_jitter | chip_sw_flash_ctrl_ops_jitter_en | 15.853m | 4.556ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_access_jitter_en | 18.764m | 6.206ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 58.066m | 21.029ms | 3 | 3 | 100.00 | ||
| chip_sw_aes_enc_jitter_en | 5.824m | 2.400ms | 3 | 3 | 100.00 | ||
| chip_sw_edn_entropy_reqs_jitter | 15.752m | 5.010ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_jitter_en | 6.408m | 2.786ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation_jitter_en | 8.173m | 4.594ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 5.707m | 3.342ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 8.601m | 4.554ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_jitter | 3.843m | 2.728ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_ast_usb_clk_calib | chip_sw_usb_ast_clk_calib | 4.431m | 3.552ms | 1 | 1 | 100.00 |
| V2 | chip_sw_ast_alerts | chip_sw_sensor_ctrl_alert | 26.579m | 15.742ms | 5 | 5 | 100.00 |
| V2 | chip_sw_sensor_ctrl_ast_alerts | chip_sw_sensor_ctrl_alert | 26.579m | 15.742ms | 5 | 5 | 100.00 |
| chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | 7.631m | 5.505ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sensor_ctrl_ast_status | chip_sw_sensor_ctrl_status | 4.089m | 2.892ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | 7.631m | 5.505ms | 3 | 3 | 100.00 |
| V2 | chip_sw_nmi_irq | chip_sw_rv_core_ibex_nmi_irq | 14.256m | 4.634ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_core_ibex_rnd | chip_sw_rv_core_ibex_rnd | 15.919m | 5.500ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_core_ibex_address_translation | chip_sw_rv_core_ibex_address_translation | 4.487m | 2.361ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_core_ibex_icache_scrambled_access | chip_sw_rv_core_ibex_icache_invalidate | 3.614m | 2.919ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_core_ibex_fault_dump | chip_sw_rstmgr_cpu_info | 12.947m | 7.732ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_core_ibex_double_fault | chip_sw_rstmgr_cpu_info | 12.947m | 7.732ms | 3 | 3 | 100.00 |
| V2 | chip_sw_smoketest | chip_sw_flash_scrambling_smoketest | 4.946m | 2.941ms | 3 | 3 | 100.00 |
| chip_sw_aes_smoketest | 5.667m | 2.957ms | 3 | 3 | 100.00 | ||
| chip_sw_aon_timer_smoketest | 5.026m | 2.960ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_smoketest | 4.345m | 2.411ms | 3 | 3 | 100.00 | ||
| chip_sw_csrng_smoketest | 4.745m | 2.560ms | 3 | 3 | 100.00 | ||
| chip_sw_entropy_src_smoketest | 9.805m | 4.123ms | 3 | 3 | 100.00 | ||
| chip_sw_gpio_smoketest | 4.802m | 2.512ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_smoketest | 6.135m | 3.693ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_smoketest | 5.811m | 2.917ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_smoketest | 20.220m | 6.454ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_smoketest | 5.075m | 2.483ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_smoketest | 6.766m | 4.685ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_usbdev_smoketest | 5.690m | 5.431ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_plic_smoketest | 4.892m | 2.217ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_timer_smoketest | 5.251m | 3.084ms | 3 | 3 | 100.00 | ||
| chip_sw_rstmgr_smoketest | 4.054m | 3.164ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_smoketest | 3.998m | 2.597ms | 3 | 3 | 100.00 | ||
| chip_sw_uart_smoketest | 3.788m | 3.108ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_rom_functests | rom_keymgr_functest | 9.792m | 3.962ms | 3 | 3 | 100.00 |
| V2 | chip_sw_signed | chip_sw_uart_smoketest_signed | 31.421m | 8.356ms | 3 | 3 | 100.00 |
| V2 | chip_sw_boot | chip_sw_uart_tx_rx_bootstrap | 2.644h | 59.091ms | 3 | 3 | 100.00 |
| V2 | chip_sw_secure_boot | rom_e2e_smoke | 30.723m | 8.231ms | 3 | 3 | 100.00 |
| V2 | chip_lc_scrap | chip_sw_lc_ctrl_rma_to_scrap | 3.426m | 3.067ms | 1 | 1 | 100.00 |
| chip_sw_lc_ctrl_raw_to_scrap | 2.135m | 2.642ms | 1 | 1 | 100.00 | ||
| chip_sw_lc_ctrl_test_locked0_to_scrap | 2.454m | 2.590ms | 1 | 1 | 100.00 | ||
| chip_sw_lc_ctrl_rand_to_scrap | 4.626m | 3.503ms | 3 | 3 | 100.00 | ||
| V2 | chip_lc_test_locked | chip_sw_lc_walkthrough_testunlocks | 40.493m | 23.462ms | 3 | 3 | 100.00 |
| chip_rv_dm_lc_disabled | 6.903m | 10.990ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_lc_walkthrough | chip_sw_lc_walkthrough_dev | 1.356h | 47.446ms | 3 | 3 | 100.00 |
| chip_sw_lc_walkthrough_prod | 1.274h | 46.294ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_walkthrough_prodend | 15.001m | 9.341ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_walkthrough_rma | 1.336h | 45.833ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_walkthrough_testunlocks | 40.493m | 23.462ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_lc_ctrl_volatile_raw_unlock | chip_sw_lc_ctrl_volatile_raw_unlock | 5.272m | 4.349ms | 3 | 3 | 100.00 |
| chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz | 4.951m | 3.825ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_96mhz | 5.429m | 4.502ms | 3 | 3 | 100.00 | ||
| rom_volatile_raw_unlock | 5.450h | 114.729ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_power_idle_load | chip_sw_power_idle_load | 10.041m | 4.252ms | 3 | 3 | 100.00 |
| V2 | chip_sw_power_sleep_load | chip_sw_power_sleep_load | 7.294m | 10.494ms | 3 | 3 | 100.00 |
| V2 | chip_sw_exit_test_unlocked_bootstrap | chip_sw_exit_test_unlocked_bootstrap | 2.163h | 48.055ms | 3 | 3 | 100.00 |
| V2 | chip_sw_inject_scramble_seed | chip_sw_inject_scramble_seed | 2.344h | 52.691ms | 3 | 3 | 100.00 |
| V2 | tl_d_oob_addr_access | chip_tl_errors | 10.123m | 5.630ms | 30 | 30 | 100.00 |
| V2 | tl_d_illegal_access | chip_tl_errors | 10.123m | 5.630ms | 30 | 30 | 100.00 |
| V2 | tl_d_outstanding_access | chip_csr_aliasing | 2.697h | 66.463ms | 5 | 5 | 100.00 |
| chip_same_csr_outstanding | 1.113h | 26.176ms | 20 | 20 | 100.00 | ||
| chip_csr_hw_reset | 5.737m | 7.269ms | 5 | 5 | 100.00 | ||
| chip_csr_rw | 10.550m | 5.036ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | chip_csr_aliasing | 2.697h | 66.463ms | 5 | 5 | 100.00 |
| chip_same_csr_outstanding | 1.113h | 26.176ms | 20 | 20 | 100.00 | ||
| chip_csr_hw_reset | 5.737m | 7.269ms | 5 | 5 | 100.00 | ||
| chip_csr_rw | 10.550m | 5.036ms | 20 | 20 | 100.00 | ||
| V2 | xbar_base_random_sequence | xbar_random | 2.165m | 2.583ms | 100 | 100 | 100.00 |
| V2 | xbar_random_delay | xbar_smoke_zero_delays | 7.250s | 49.088us | 100 | 100 | 100.00 |
| xbar_smoke_large_delays | 1.975m | 12.259ms | 100 | 100 | 100.00 | ||
| xbar_smoke_slow_rsp | 1.984m | 6.829ms | 100 | 100 | 100.00 | ||
| xbar_random_zero_delays | 1.012m | 547.411us | 100 | 100 | 100.00 | ||
| xbar_random_large_delays | 21.847m | 115.154ms | 100 | 100 | 100.00 | ||
| xbar_random_slow_rsp | 22.867m | 69.707ms | 100 | 100 | 100.00 | ||
| V2 | xbar_unmapped_address | xbar_unmapped_addr | 1.191m | 1.355ms | 100 | 100 | 100.00 |
| xbar_error_and_unmapped_addr | 58.380s | 1.110ms | 100 | 100 | 100.00 | ||
| V2 | xbar_error_cases | xbar_error_random | 1.995m | 2.628ms | 100 | 100 | 100.00 |
| xbar_error_and_unmapped_addr | 58.380s | 1.110ms | 100 | 100 | 100.00 | ||
| V2 | xbar_all_access_same_device | xbar_access_same_device | 2.505m | 3.405ms | 100 | 100 | 100.00 |
| xbar_access_same_device_slow_rsp | 46.871m | 160.791ms | 100 | 100 | 100.00 | ||
| V2 | xbar_all_hosts_use_same_source_id | xbar_same_source | 1.642m | 2.598ms | 100 | 100 | 100.00 |
| V2 | xbar_stress_all | xbar_stress_all | 13.690m | 22.263ms | 100 | 100 | 100.00 |
| xbar_stress_all_with_error | 11.634m | 18.894ms | 100 | 100 | 100.00 | ||
| V2 | xbar_stress_with_reset | xbar_stress_all_with_rand_reset | 20.364m | 19.174ms | 100 | 100 | 100.00 |
| xbar_stress_all_with_reset_error | 20.744m | 25.952ms | 100 | 100 | 100.00 | ||
| V2 | rom_e2e_smoke | rom_e2e_smoke | 30.723m | 8.231ms | 3 | 3 | 100.00 |
| V2 | rom_e2e_shutdown_output | rom_e2e_shutdown_output | 45.468m | 23.214ms | 3 | 3 | 100.00 |
| V2 | rom_e2e_shutdown_exception_c | rom_e2e_shutdown_exception_c | 34.504m | 7.789ms | 3 | 3 | 100.00 |
| V2 | rom_e2e_boot_policy_valid | rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 | 3.690h | 77.957ms | 1 | 1 | 100.00 |
| rom_e2e_boot_policy_valid_a_good_b_good_dev | 31.490m | 8.362ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_good_prod | 18.943m | 8.463ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_good_prod_end | 34.776m | 8.808ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_good_rma | 30.974m | 8.637ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 | 3.703h | 77.506ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_dev | 33.036m | 8.040ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_prod | 31.981m | 8.606ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_prod_end | 34.717m | 8.745ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_rma | 31.715m | 8.283ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 | 7.497h | 151.866ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_dev | 42.019m | 11.421ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_prod | 47.126m | 11.898ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_prod_end | 41.805m | 11.251ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_rma | 43.860m | 11.658ms | 1 | 1 | 100.00 | ||
| V2 | rom_e2e_sigverify_always | rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 | 7.309h | 151.603ms | 1 | 1 | 100.00 |
| rom_e2e_sigverify_always_a_bad_b_bad_dev | 51.073m | 10.777ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_bad_prod | 34.977m | 11.060ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_bad_prod_end | 47.566m | 11.551ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_bad_rma | 45.849m | 11.247ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 | 3.553h | 77.991ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_dev | 18.285m | 7.475ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_prod | 31.968m | 8.469ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_prod_end | 24.466m | 7.428ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_rma | 26.886m | 8.202ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 | 3.981h | 77.973ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_dev | 30.700m | 7.354ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_prod | 29.289m | 7.946ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_prod_end | 31.364m | 8.058ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_rma | 30.220m | 8.178ms | 1 | 1 | 100.00 | ||
| V2 | rom_e2e_sigverify_mod_exp | rom_e2e_sigverify_mod_exp_test_unlocked0_otbn | 4.148h | 77.475ms | 3 | 3 | 100.00 |
| rom_e2e_sigverify_mod_exp_test_unlocked0_sw | 3.910h | 77.094ms | 3 | 3 | 100.00 | ||
| rom_e2e_sigverify_mod_exp_dev_otbn | 35.207m | 8.503ms | 3 | 3 | 100.00 | ||
| rom_e2e_sigverify_mod_exp_dev_sw | 32.950m | 8.847ms | 3 | 3 | 100.00 | ||
| rom_e2e_sigverify_mod_exp_prod_otbn | 34.763m | 8.699ms | 3 | 3 | 100.00 | ||
| rom_e2e_sigverify_mod_exp_prod_sw | 32.610m | 9.051ms | 3 | 3 | 100.00 | ||
| rom_e2e_sigverify_mod_exp_prod_end_otbn | 30.433m | 8.085ms | 3 | 3 | 100.00 | ||
| rom_e2e_sigverify_mod_exp_prod_end_sw | 32.780m | 7.893ms | 3 | 3 | 100.00 | ||
| rom_e2e_sigverify_mod_exp_rma_otbn | 33.767m | 8.722ms | 3 | 3 | 100.00 | ||
| rom_e2e_sigverify_mod_exp_rma_sw | 30.069m | 8.243ms | 3 | 3 | 100.00 | ||
| V2 | rom_e2e_asm_init | rom_e2e_asm_init_test_unlocked0 | 4.355h | 77.092ms | 0 | 3 | 0.00 |
| rom_e2e_asm_init_dev | 33.724m | 8.629ms | 0 | 3 | 0.00 | ||
| rom_e2e_asm_init_prod | 32.044m | 8.559ms | 0 | 3 | 0.00 | ||
| rom_e2e_asm_init_prod_end | 34.252m | 8.420ms | 0 | 3 | 0.00 | ||
| rom_e2e_asm_init_rma | 35.392m | 8.397ms | 0 | 3 | 0.00 | ||
| V2 | rom_e2e_keymgr_init | rom_e2e_keymgr_init_rom_ext_meas | 32.693m | 8.351ms | 3 | 3 | 100.00 |
| rom_e2e_keymgr_init_rom_ext_no_meas | 33.248m | 8.642ms | 3 | 3 | 100.00 | ||
| rom_e2e_keymgr_init_rom_ext_invalid_meas | 26.950m | 8.427ms | 3 | 3 | 100.00 | ||
| V2 | rom_e2e_static_critical | rom_e2e_static_critical | 34.706m | 10.741ms | 3 | 3 | 100.00 |
| V2 | TOTAL | 2635 | 2651 | 99.40 | |||
| V2S | chip_sw_aes_masking_off | chip_sw_aes_masking_off | 5.934m | 3.158ms | 3 | 3 | 100.00 |
| V2S | chip_sw_rv_core_ibex_lockstep_glitch | chip_sw_rv_core_ibex_lockstep_glitch | 3.279m | 2.378ms | 3 | 3 | 100.00 |
| V2S | TOTAL | 6 | 6 | 100.00 | |||
| V3 | chip_sw_spi_device_pass_through_flash_model | chip_sw_spi_device_pass_through_flash_model | 0 | 0 | -- | ||
| V3 | chip_sw_spi_device_output_when_disabled_or_sleeping | chip_sw_spi_device_output_when_disabled_or_sleeping | 0 | 0 | -- | ||
| V3 | chip_sw_usb_fs_tx_rx | chip_sw_usbdev_stream | 56.425m | 13.611ms | 1 | 1 | 100.00 |
| V3 | chip_sw_usb_vbus | chip_sw_usb_vbus | 0 | 0 | -- | ||
| V3 | chip_sw_usb_suspend | chip_sw_usb_suspend | 0 | 0 | -- | ||
| V3 | chip_usb_sof | chip_usb_sof | 0 | 0 | -- | ||
| V3 | chip_usb_wake_debug | chip_usb_wake_debug | 0 | 0 | -- | ||
| V3 | chip_usb_enumeration | chip_usb_enumeration | 0 | 0 | -- | ||
| V3 | chip_rv_dm_perform_debug | rom_e2e_jtag_debug_test_unlocked0 | 29.851m | 10.387ms | 1 | 1 | 100.00 |
| rom_e2e_jtag_debug_dev | 31.800m | 10.956ms | 1 | 1 | 100.00 | ||
| rom_e2e_jtag_debug_rma | 35.403m | 10.697ms | 1 | 1 | 100.00 | ||
| V3 | chip_sw_rv_dm_access_after_hw_reset | chip_sw_rv_dm_access_after_escalation_reset | 10.479m | 5.478ms | 3 | 3 | 100.00 |
| V3 | chip_sw_plic_alerts | chip_sw_all_escalation_resets | 13.911m | 5.196ms | 100 | 100 | 100.00 |
| V3 | chip_sw_lc_ctrl_kmac_error | chip_sw_lc_ctrl_kmac_error | 0 | 0 | -- | ||
| V3 | chip_sw_csrng_edn_error | chip_sw_csrng_edn_error | 0 | 0 | -- | ||
| V3 | chip_sw_keymgr_sideload_kmac_error | chip_sw_keymgr_sideload_kmac_error | 0 | 0 | -- | ||
| V3 | chip_sw_rom_ctrl_kmac_error | chip_sw_rom_ctrl_kmac_error | 0 | 0 | -- | ||
| V3 | chip_sw_otp_ctrl_vendor_test_csr_access | chip_sw_otp_ctrl_vendor_test_csr_access | 3.333m | 2.945ms | 3 | 3 | 100.00 |
| V3 | chip_sw_otp_ctrl_escalation | chip_sw_otp_ctrl_escalation | 9.617m | 5.096ms | 1 | 1 | 100.00 |
| V3 | chip_sw_rv_core_ibex_alerts | chip_sw_rv_core_ibex_alerts | 0 | 0 | -- | ||
| V3 | chip_sw_coremark | chip_sw_coremark | 3.210s | 0 | 1 | 0.00 | |
| V3 | chip_sw_power_max_load | chip_sw_power_virus | 30.715m | 8.822ms | 3 | 3 | 100.00 |
| V3 | rom_e2e_debug | rom_e2e_jtag_debug_test_unlocked0 | 29.851m | 10.387ms | 1 | 1 | 100.00 |
| rom_e2e_jtag_debug_dev | 31.800m | 10.956ms | 1 | 1 | 100.00 | ||
| rom_e2e_jtag_debug_rma | 35.403m | 10.697ms | 1 | 1 | 100.00 | ||
| V3 | rom_e2e_jtag_inject | rom_e2e_jtag_inject_test_unlocked0 | 54.274m | 39.854ms | 1 | 1 | 100.00 |
| rom_e2e_jtag_inject_dev | 46.468m | 33.268ms | 1 | 1 | 100.00 | ||
| rom_e2e_jtag_inject_rma | 49.206m | 32.293ms | 1 | 1 | 100.00 | ||
| V3 | rom_bootstrap_rma | rom_bootstrap_rma | 0 | 0 | -- | ||
| V3 | rom_e2e_weak_straps | rom_e2e_weak_straps | 0 | 0 | -- | ||
| V3 | TOTAL | 17 | 18 | 94.44 | |||
| Unmapped tests | chip_sw_rstmgr_rst_cnsty_escalation | 10.941m | 4.160ms | 3 | 3 | 100.00 | |
| TOTAL | 2884 | 2901 | 99.41 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 1 | 1 | 1 | 100.00 |
| V1 | 19 | 19 | 19 | 100.00 |
| V2 | 270 | 270 | 264 | 97.78 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 26 | 12 | 11 | 42.31 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 96.78 | 95.71 | 94.41 | 97.92 | -- | 95.04 | 97.93 | 99.67 |
UVM_ERROR @ * us: (chip_sw_rom_e2e_asm_init_vseq.sv:176) [chip_sw_rom_e2e_asm_init_vseq] Check failed cfg.chip_vif.pmp_addr[*] == epmp_addr_tor(FLASH_TEXT_START_ADDRESS) (* [*] vs * [*]) has 15 failures:
0.rom_e2e_asm_init_test_unlocked0.2414113513
Line 1101, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_asm_init_test_unlocked0/latest/run.log
UVM_ERROR @ 77513.566428 us: (chip_sw_rom_e2e_asm_init_vseq.sv:176) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_asm_init_vseq] Check failed cfg.chip_vif.pmp_addr[3] == epmp_addr_tor(FLASH_TEXT_START_ADDRESS) (134217984 [0x8000100] vs 134219968 [0x80008c0])
UVM_INFO @ 77513.566428 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rom_e2e_asm_init_test_unlocked0.1423497703
Line 1103, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_asm_init_test_unlocked0/latest/run.log
UVM_ERROR @ 78020.519428 us: (chip_sw_rom_e2e_asm_init_vseq.sv:176) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_asm_init_vseq] Check failed cfg.chip_vif.pmp_addr[3] == epmp_addr_tor(FLASH_TEXT_START_ADDRESS) (134217984 [0x8000100] vs 134219968 [0x80008c0])
UVM_INFO @ 78020.519428 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
0.rom_e2e_asm_init_dev.2722403724
Line 1106, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_asm_init_dev/latest/run.log
UVM_ERROR @ 8629.067340 us: (chip_sw_rom_e2e_asm_init_vseq.sv:176) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_asm_init_vseq] Check failed cfg.chip_vif.pmp_addr[3] == epmp_addr_tor(FLASH_TEXT_START_ADDRESS) (134217984 [0x8000100] vs 134219968 [0x80008c0])
UVM_INFO @ 8629.067340 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rom_e2e_asm_init_dev.246024344
Line 1098, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_asm_init_dev/latest/run.log
UVM_ERROR @ 9180.807680 us: (chip_sw_rom_e2e_asm_init_vseq.sv:176) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_asm_init_vseq] Check failed cfg.chip_vif.pmp_addr[3] == epmp_addr_tor(FLASH_TEXT_START_ADDRESS) (134217984 [0x8000100] vs 134219968 [0x80008c0])
UVM_INFO @ 9180.807680 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
0.rom_e2e_asm_init_prod.1340762739
Line 1095, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_asm_init_prod/latest/run.log
UVM_ERROR @ 8558.523232 us: (chip_sw_rom_e2e_asm_init_vseq.sv:176) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_asm_init_vseq] Check failed cfg.chip_vif.pmp_addr[3] == epmp_addr_tor(FLASH_TEXT_START_ADDRESS) (134217984 [0x8000100] vs 134219968 [0x80008c0])
UVM_INFO @ 8558.523232 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rom_e2e_asm_init_prod.2254496096
Line 1094, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_asm_init_prod/latest/run.log
UVM_ERROR @ 8803.522720 us: (chip_sw_rom_e2e_asm_init_vseq.sv:176) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_asm_init_vseq] Check failed cfg.chip_vif.pmp_addr[3] == epmp_addr_tor(FLASH_TEXT_START_ADDRESS) (134217984 [0x8000100] vs 134219968 [0x80008c0])
UVM_INFO @ 8803.522720 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
0.rom_e2e_asm_init_prod_end.1622528428
Line 1101, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_asm_init_prod_end/latest/run.log
UVM_ERROR @ 8420.121130 us: (chip_sw_rom_e2e_asm_init_vseq.sv:176) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_asm_init_vseq] Check failed cfg.chip_vif.pmp_addr[3] == epmp_addr_tor(FLASH_TEXT_START_ADDRESS) (134217984 [0x8000100] vs 134219968 [0x80008c0])
UVM_INFO @ 8420.121130 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rom_e2e_asm_init_prod_end.2247962174
Line 1091, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_asm_init_prod_end/latest/run.log
UVM_ERROR @ 7967.418072 us: (chip_sw_rom_e2e_asm_init_vseq.sv:176) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_asm_init_vseq] Check failed cfg.chip_vif.pmp_addr[3] == epmp_addr_tor(FLASH_TEXT_START_ADDRESS) (134217984 [0x8000100] vs 134219968 [0x80008c0])
UVM_INFO @ 7967.418072 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
0.rom_e2e_asm_init_rma.1467370607
Line 1106, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_asm_init_rma/latest/run.log
UVM_ERROR @ 8546.569080 us: (chip_sw_rom_e2e_asm_init_vseq.sv:176) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_asm_init_vseq] Check failed cfg.chip_vif.pmp_addr[3] == epmp_addr_tor(FLASH_TEXT_START_ADDRESS) (134217984 [0x8000100] vs 134219968 [0x80008c0])
UVM_INFO @ 8546.569080 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rom_e2e_asm_init_rma.681239087
Line 1096, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_asm_init_rma/latest/run.log
UVM_ERROR @ 8396.059326 us: (chip_sw_rom_e2e_asm_init_vseq.sv:176) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_asm_init_vseq] Check failed cfg.chip_vif.pmp_addr[3] == epmp_addr_tor(FLASH_TEXT_START_ADDRESS) (134217984 [0x8000100] vs 134219968 [0x80008c0])
UVM_INFO @ 8396.059326 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL @ * us: (uart_logger.sv:25) [m_logger] Check failed (!logs_output_fd) Failed to open log for writing has 1 failures:
0.chip_sw_coremark.902575304
Line 1046, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_coremark/latest/run.log
UVM_FATAL @ 0.000000 us: (uart_logger.sv:25) [uvm_test_top.env.m_uart_agent0.m_logger] Check failed (!logs_output_fd) Failed to open uvm_test_top.env.m_uart_agent0.m_logger.log for writing
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:523) [data_integrity_escalation_reset_test_prog_sim_dv(sw/device/tests/sim_dv/data_integrity_escalation_reset_test.c:360)] CHECK-STATUS-fail: FLA:* = Unavailable has 1 failures:
1.chip_sw_data_integrity_escalation.1411128844
Line 1100, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_data_integrity_escalation/latest/run.log
UVM_ERROR @ 3289.323200 us: (sw_logger_if.sv:523) [data_integrity_escalation_reset_test_prog_sim_dv(sw/device/tests/sim_dv/data_integrity_escalation_reset_test.c:360)] CHECK-STATUS-fail: FLA:209 = Unavailable
UVM_INFO @ 3289.323200 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---