Design Module List
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Total Module Definition Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.79 95.85 91.35 93.33 94.81 93.59


Total modules in report: 108
modlist.html | modlist1.html
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_mubi4_dec 0.00 0.00
padring 50.44 50.44
pinmux_wkup 64.07 68.42 69.23 54.55
prim_packer_fifo 68.93 100.00 90.00 85.71 0.00
rv_plic_gateway 69.17 100.00 20.00 87.50
pinmux 79.32 77.30 85.01 65.13 80.72 88.46
tlul_err_resp 79.42 92.31 68.18 77.78
prim_generic_usb_diff_rx 81.48 83.33 77.78 83.33
top_earlgrey 83.95 92.47 59.36 100.00
prim_generic_clock_mux2 85.19 100.00 55.56 100.00
ast 85.21 85.21
spi_device 88.43 88.43
chip_earlgrey_asic 89.03 72.73 100.00 94.37
tlul_adapter_host 89.09 91.11 75.79 89.44 100.00
tlul_adapter_host 100.00 100.00
tlul_adapter_host ( parameter MAX_REQS=2,EnableDataIntgGen=1,EnableRspDataIntgCheck=0,WordSize=2,OutstandingReqCntW=2,g_multiple_reqs.ReqNumW=1 + MAX_REQS=2,EnableDataIntgGen=0,EnableRspDataIntgCheck=0,WordSize=2,OutstandingReqCntW=2,g_multiple_reqs.ReqNumW=1 ) 87.89 91.30 82.35 90.00
tlul_adapter_host ( parameter MAX_REQS=8,EnableDataIntgGen=0,EnableRspDataIntgCheck=0,WordSize=2,OutstandingReqCntW=4,g_multiple_reqs.ReqNumW=3 ) 83.01 90.91 69.23 88.89
usbdev 90.24 90.24
lc_ctrl 90.51 90.51
prim_max_tree 91.43 89.00 76.72 100.00 100.00
tlul_rsp_intg_gen 91.67 83.33 100.00
tlul_rsp_intg_gen 100.00 100.00
tlul_rsp_intg_gen ( parameter EnableRspIntgGen=0,EnableDataIntgGen=0 ) 66.67 66.67
tlul_rsp_intg_gen ( parameter EnableRspIntgGen=1,EnableDataIntgGen=1 ) 100.00 100.00
prim_sync_reqack 91.67 100.00 66.67 100.00 100.00
prim_reg_cdc_arb 92.33 96.00 90.70 82.61 100.00
prim_reg_cdc_arb 91.30 82.61 100.00
prim_reg_cdc_arb ( parameter DataWidth=10,ResetVal=0,DstWrReq=1 + DataWidth=4,ResetVal,DstWrReq=1 + DataWidth=1,ResetVal=0,DstWrReq=1 + DataWidth=14,ResetVal=0,DstWrReq=1 + DataWidth=28,ResetVal=0,DstWrReq=1 + DataWidth=8,ResetVal=0,DstWrReq=1 + DataWidth=32,ResetVal=0,DstWrReq=1 ) 86.70 92.00 81.40
prim_reg_cdc_arb ( parameter DataWidth=2,ResetVal=0,DstWrReq=0 + DataWidth=20,ResetVal,DstWrReq=0 + DataWidth=18,ResetVal=118010,DstWrReq=0 + DataWidth=16,ResetVal,DstWrReq=0 + DataWidth=1,ResetVal=0,DstWrReq=0 + DataWidth=12,ResetVal=0,DstWrReq=0 + DataWidth=8,ResetVal,DstWrReq=0 + DataWidth=14,ResetVal=0,DstWrReq=0 + DataWidth=17,ResetVal=2000,DstWrReq=0 + DataWidth=7,ResetVal=0,DstWrReq=0 + DataWidth=5,ResetVal=0,DstWrReq=0 + DataWidth=32,ResetVal,DstWrReq=0 + DataWidth=4,ResetVal=0,DstWrReq=0 + DataWidth=6,ResetVal=0,DstWrReq=0 + DataWidth=13,ResetVal=0,DstWrReq=0 ) 100.00 100.00 100.00
rv_core_ibex 92.69 96.47 89.29 98.77 100.00 78.95
otp_ctrl 92.76 92.76
rv_plic 93.26 99.65 66.67 100.00 100.00 100.00
tlul_rsp_intg_chk 93.33 100.00 80.00 100.00
usbdev_aon_wake 94.02 97.14 84.21 94.74 100.00
ibex_top 94.28 94.28
entropy_src 94.40 94.40
prim_arbiter_fixed 94.88 100.00 86.67 100.00 92.86
tlul_socket_1n 95.64 94.64 93.18 94.74 100.00
prim_edn_req 96.15 100.00 84.62 100.00 100.00
sensor_ctrl 96.97 95.89 88.98 100.00 100.00 100.00
spi_host 97.21 97.21
prim_reg_cdc 97.25 100.00 89.01 100.00 100.00
prim_reg_cdc 100.00 100.00 100.00 100.00
prim_reg_cdc ( parameter DataWidth=1,ResetVal=0,BitMask=1,DstWrReq=0,TxnWidth=3 + DataWidth=1,ResetVal=0,BitMask=1,DstWrReq=1,TxnWidth=3 ) 92.31 92.31
prim_reg_cdc ( parameter DataWidth=2,ResetVal=0,BitMask=3,DstWrReq=0,TxnWidth=3 + DataWidth=10,ResetVal=0,BitMask=769,DstWrReq=1,TxnWidth=3 + DataWidth=4,ResetVal,BitMask=15,DstWrReq=1,TxnWidth=3 + DataWidth=20,ResetVal,BitMask=1048575,DstWrReq=0,TxnWidth=3 + DataWidth=18,ResetVal=118010,BitMask=262143,DstWrReq=0,TxnWidth=3 + DataWidth=16,ResetVal,BitMask=65535,DstWrReq=0,TxnWidth=3 + DataWidth=12,ResetVal=0,BitMask=4095,DstWrReq=0,TxnWidth=3 + DataWidth=8,ResetVal,BitMask=255,DstWrReq=0,TxnWidth=3 + DataWidth=14,ResetVal=0,BitMask=16383,DstWrReq=0,TxnWidth=3 + DataWidth=17,ResetVal=2000,BitMask=131071,DstWrReq=0,TxnWidth=3 + DataWidth=7,ResetVal=0,BitMask=119,DstWrReq=0,TxnWidth=3 + DataWidth=5,ResetVal=0,BitMask=31,DstWrReq=0,TxnWidth=3 + DataWidth=32,ResetVal,BitMask,DstWrReq=0,TxnWidth=3 + DataWidth=4,ResetVal=0,BitMask=15,DstWrReq=0,TxnWidth=3 + DataWidth=14,ResetVal=0,BitMask=16383,DstWrReq=1,TxnWidth=3 + DataWidth=28,ResetVal=0,BitMask=268374015,DstWrReq=1,TxnWidth=3 + DataWidth=8,ResetVal=0,BitMask=255,DstWrReq=1,TxnWidth=3 + DataWidth=6,ResetVal=0,BitMask=63,DstWrReq=0,TxnWidth=3 + DataWidth=13,ResetVal=0,BitMask=8191,DstWrReq=0,TxnWidth=3 + DataWidth=32,ResetVal=0,BitMask=-1,DstWrReq=1,TxnWidth=3 ) 85.71 85.71
rom_ctrl 97.26 97.26
sram_ctrl 98.27 98.27
flash_ctrl 98.79 98.79
kmac 98.92 98.92
otbn 99.18 99.18
pinmux_reg_top 99.25 99.77 97.23 100.00 100.00
edn 99.42 99.42
tlul_adapter_reg 99.49 100.00 97.96 100.00 100.00
csrng 99.61 99.61
sensor_ctrl_reg_top 99.79 100.00 99.17 100.00 100.00
pinmux_strap_sampling 99.83 99.34 100.00 100.00 100.00
rv_core_ibex_cfg_reg_top 99.84 100.00 99.36 100.00 100.00
alert_handler 99.92 99.92
aes 99.93 99.93
rv_plic_reg_top 99.98 100.00 99.90 100.00 100.00
keymgr 99.99 99.99
gpio 100.00 100.00
rstmgr 100.00 100.00
adc_ctrl 100.00 100.00
pwm 100.00 100.00
prim_lc_sync 100.00 100.00 100.00
prim_lc_sync 100.00 100.00
prim_lc_sync ( parameter NumCopies=1,AsyncOn=1,ResetValueIsOn=0,LcResetValue=10 ) 100.00 100.00
prim_lc_sync ( parameter NumCopies=2,AsyncOn=1,ResetValueIsOn=0,LcResetValue=10 ) 100.00 100.00
prim_lc_sync ( parameter NumCopies=3,AsyncOn=0,ResetValueIsOn=0,LcResetValue=10 ) 100.00 100.00
prim_lc_sync ( parameter NumCopies=4,AsyncOn=0,ResetValueIsOn=0,LcResetValue=10 ) 100.00 100.00
prim_lc_sender 100.00 100.00
tlul_data_integ_dec 100.00 100.00
tlul_cmd_intg_chk 100.00 100.00 100.00
hmac 100.00 100.00
prim_alert_sender 100.00 100.00
i2c 100.00 100.00
tlul_cmd_intg_gen 100.00 100.00 100.00
tlul_fifo_sync 100.00 100.00 100.00
prim_edge_detector 100.00 100.00 100.00 100.00
clk_ctrl_and_main_pd_sva_if 100.00 100.00
rv_dm 100.00 100.00
prim_subreg 100.00 100.00 100.00 100.00
prim_subreg 100.00 100.00 100.00
prim_subreg ( parameter DW=1,SwAccess=3,RESVAL + DW=1,SwAccess,RESVAL + DW=1,SwAccess=1,RESVAL + DW=1,SwAccess=5,RESVAL + DW=1,SwAccess=4,RESVAL=0 ) 100.00 100.00
prim_subreg ( parameter DW=2,SwAccess,RESVAL + DW=2,SwAccess=1,RESVAL=0 + DW=2,SwAccess=3,RESVAL=0 ) 100.00 100.00
prim_subreg ( parameter DW=3,SwAccess,RESVAL + DW=3,SwAccess=1,RESVAL + DW=3,SwAccess=3,RESVAL=0 ) 100.00 100.00
prim_subreg ( parameter DW=32,SwAccess=1,RESVAL + DW=32,SwAccess,RESVAL + DW=32,SwAccess=3,RESVAL=0 + DW=32,SwAccess=6,RESVAL=0 ) 100.00 100.00
prim_subreg ( parameter DW=4,SwAccess=0,RESVAL + DW=4,SwAccess=1,RESVAL=0 + DW=4,SwAccess=5,RESVAL=9 ) 100.00 100.00
prim_subreg ( parameter DW=6,SwAccess,RESVAL + DW=6,SwAccess=1,RESVAL=0 ) 100.00 100.00
prim_subreg ( parameter DW=7,SwAccess=1,RESVAL=0 + DW=7,SwAccess=0,RESVAL ) 100.00 100.00
prim_subreg ( parameter DW=8,SwAccess,RESVAL + DW=8,SwAccess=1,RESVAL + DW=8,SwAccess=3,RESVAL=0 ) 100.00 100.00
prim_filter 100.00 100.00 100.00 100.00
pinmux_jtag_breakout 100.00 100.00 100.00
prim_lc_or_hardened 100.00 100.00 100.00 100.00
prim_generic_buf 100.00 100.00
prim_intr_hw 100.00 100.00 100.00 100.00 100.00
prim_pulse_sync 100.00 100.00 100.00 100.00 100.00
prim_fifo_sync 100.00 100.00 100.00
prim_subreg_arb 100.00 100.00 100.00 100.00
prim_subreg_arb 100.00 100.00
prim_subreg_arb ( parameter DW=1,SwAccess=0 ) 100.00 100.00
prim_subreg_arb ( parameter DW=1,SwAccess=3 ) 100.00 100.00
prim_subreg_arb ( parameter DW=1,SwAccess=3 + DW=32,SwAccess=3 + DW=3,SwAccess=3 + DW=10,SwAccess=3 + DW=5,SwAccess=3 + DW=8,SwAccess=3 + DW=2,SwAccess=3 ) 100.00 100.00
prim_subreg_arb ( parameter DW=1,SwAccess=4 ) 100.00 100.00 100.00
prim_subreg_arb ( parameter DW=1,SwAccess=5 ) 100.00 100.00
prim_subreg_arb ( parameter DW=1,SwAccess=5 + DW=4,SwAccess=5 + DW=16,SwAccess=5 ) 100.00 100.00
prim_subreg_arb ( parameter DW=2,SwAccess=0 ) 100.00 100.00
prim_subreg_arb ( parameter DW=3,SwAccess=0 ) 100.00 100.00
prim_subreg_arb ( parameter DW=32,SwAccess=0 ) 100.00 100.00
prim_subreg_arb ( parameter DW=32,SwAccess=0 + DW=1,SwAccess=0 + DW=2,SwAccess=0 + DW=16,SwAccess=0 + DW=8,SwAccess=0 + DW=3,SwAccess=0 + DW=24,SwAccess=0 + DW=10,SwAccess=0 + DW=4,SwAccess=0 + DW=31,SwAccess=0 + DW=7,SwAccess=0 + DW=6,SwAccess=0 + DW=12,SwAccess=0 + DW=11,SwAccess=0 + DW=5,SwAccess=0 + DW=9,SwAccess=0 + DW=27,SwAccess=0 + DW=20,SwAccess=0 ) 100.00 100.00
prim_subreg_arb ( parameter DW=32,SwAccess=1 + DW=1,SwAccess=1 + DW=16,SwAccess=1 + DW=5,SwAccess=1 + DW=9,SwAccess=1 + DW=8,SwAccess=1 + DW=3,SwAccess=1 + DW=7,SwAccess=1 + DW=6,SwAccess=1 + DW=4,SwAccess=1 + DW=2,SwAccess=1 + DW=10,SwAccess=1 + DW=20,SwAccess=1 ) 100.00 100.00
prim_subreg_arb ( parameter DW=4,SwAccess=0 ) 100.00 100.00
prim_subreg_arb ( parameter DW=4,SwAccess=5 + DW=16,SwAccess=5 ) 100.00 100.00
prim_subreg_arb ( parameter DW=6,SwAccess=0 ) 100.00 100.00
prim_subreg_arb ( parameter DW=7,SwAccess=0 ) 100.00 100.00
prim_subreg_arb ( parameter DW=8,SwAccess=0 ) 100.00 100.00
clkmgr 100.00 100.00
aon_timer 100.00 100.00
pattgen 100.00 100.00
sysrst_ctrl 100.00 100.00
uart 100.00 100.00
prim_subreg_ext 100.00 100.00
prim_secded_inv_39_32_enc 100.00 100.00
xbar_main 100.00 100.00
tlul_err 100.00 100.00 100.00 100.00 100.00
pwrmgr 100.00 100.00
prim_esc_receiver 100.00 100.00
prim_secded_inv_64_57_enc 100.00 100.00
prim_generic_pad_wrapper 100.00 100.00 100.00 100.00 100.00
prim_generic_pad_wrapper 100.00 100.00
prim_generic_pad_wrapper ( parameter PadType=0,ScanRole=0 ) 100.00 100.00 100.00 100.00
prim_generic_pad_wrapper ( parameter PadType=3,ScanRole=0 ) 100.00 100.00 100.00 100.00
prim_generic_pad_wrapper ( parameter PadType=4,ScanRole=0 ) 100.00 100.00
xbar_peri 100.00 100.00
rv_timer 100.00 100.00
prim_sync_reqack_data 100.00 100.00 100.00
rv_core_addr_trans 100.00 100.00 100.00 100.00
prim_generic_flop 100.00 100.00 100.00
rv_plic_target 100.00 100.00 100.00 100.00
prim_mubi4_sync 100.00 100.00
prim_generic_clock_buf 100.00 100.00
pinmux_jtag_buf
prim_usb_diff_rx
prim_clock_buf
tlul_data_integ_enc
prim_reg_we_check
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