Total Coverage Summary 

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.85	95.74	94.51	98.09		95.15	97.93	99.67

Total tests in report: 2896

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Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
27.71	27.71	43.39	43.39	40.37	40.37	34.75	34.75			24.26	24.26	7.25	7.25	16.27	16.27	/workspace/coverage/cover_reg_top/15.xbar_stress_all.357305213
54.82	27.10	71.04	27.66	61.50	21.13	56.47	21.72			68.77	44.52	51.67	44.42	19.44	3.16	/workspace/coverage/cover_reg_top/2.chip_csr_rw.1513987566
68.37	13.56	75.52	4.48	73.23	11.72	67.65	11.18			82.72	13.95	91.64	39.96	19.48	0.05	/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2477082000
73.32	4.94	75.60	0.08	73.65	0.42	67.65	0.00			82.84	0.12	91.64	0.00	48.53	29.05	/workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.2805205688
76.92	3.61	83.00	7.40	79.62	5.98	73.00	5.34			85.57	2.73	91.82	0.19	48.53	0.00	/workspace/coverage/default/7.chip_padctrl_attributes.61943061
79.76	2.84	83.00	0.00	80.11	0.49	73.00	0.00			85.70	0.13	91.82	0.00	64.93	16.40	/workspace/coverage/cover_reg_top/69.xbar_stress_all_with_rand_reset.3033682522
82.45	2.70	90.62	7.62	83.73	3.62	73.75	0.75			89.88	4.18	91.82	0.00	64.93	0.00	/workspace/coverage/default/0.chip_plic_all_irqs.461187414
84.19	1.73	90.62	0.00	83.73	0.00	73.75	0.00			89.88	0.00	91.82	0.00	75.32	10.38	/workspace/coverage/cover_reg_top/92.xbar_access_same_device_slow_rsp.1187254036
85.50	1.32	90.76	0.14	84.62	0.89	74.51	0.77			90.06	0.18	91.82	0.00	81.23	5.91	/workspace/coverage/cover_reg_top/49.xbar_stress_all_with_error.3379560455
86.80	1.30	90.85	0.09	84.70	0.07	81.98	7.47			90.23	0.17	91.82	0.00	81.23	0.00	/workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.980234724
87.81	1.01	90.85	0.00	84.70	0.00	81.98	0.00			90.23	0.00	91.82	0.00	87.29	6.06	/workspace/coverage/cover_reg_top/72.xbar_stress_all_with_error.1635968916
88.76	0.95	91.76	0.92	87.04	2.35	82.01	0.03			92.64	2.41	91.82	0.00	87.29	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.2302633541
89.69	0.93	92.54	0.78	87.23	0.19	82.30	0.29			92.88	0.24	95.91	4.09	87.29	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.2120602041
90.48	0.79	92.57	0.03	87.28	0.04	86.92	4.63			92.91	0.02	95.91	0.00	87.29	0.00	/workspace/coverage/default/1.chip_sw_entropy_src_csrng.3464057888
91.26	0.78	92.57	0.00	87.28	0.00	91.58	4.65			92.91	0.00	95.91	0.00	87.29	0.00	/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.1516762476
91.89	0.63	92.57	0.00	87.28	0.00	91.58	0.00			92.91	0.00	95.91	0.00	91.10	3.81	/workspace/coverage/cover_reg_top/84.xbar_access_same_device.872551506
92.38	0.49	93.42	0.85	88.20	0.92	91.67	0.10			93.92	1.01	95.91	0.00	91.15	0.05	/workspace/coverage/default/0.chip_jtag_csr_rw.961199602
92.84	0.47	93.44	0.01	89.89	1.70	92.35	0.67			93.92	0.00	95.91	0.00	91.56	0.41	/workspace/coverage/cover_reg_top/25.chip_tl_errors.3646967919
93.20	0.36	93.44	0.00	89.89	0.00	92.35	0.00			93.92	0.00	95.91	0.00	93.72	2.16	/workspace/coverage/cover_reg_top/59.xbar_access_same_device_slow_rsp.3208435097
93.49	0.28	93.44	0.00	89.92	0.03	92.35	0.00			93.92	0.00	95.91	0.00	95.38	1.66	/workspace/coverage/cover_reg_top/78.xbar_stress_all_with_reset_error.1270801458
93.72	0.23	93.72	0.28	90.10	0.18	92.52	0.17			94.12	0.20	96.47	0.56	95.38	0.00	/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.4188156300
93.92	0.20	94.05	0.33	90.61	0.51	92.82	0.30			94.19	0.07	96.47	0.00	95.38	0.00	/workspace/coverage/cover_reg_top/3.chip_csr_hw_reset.2517892051
94.11	0.19	94.05	0.00	90.61	0.00	93.80	0.97			94.19	0.00	96.65	0.19	95.38	0.00	/workspace/coverage/default/4.chip_sw_lc_ctrl_transition.1795698211
94.29	0.17	94.06	0.02	90.61	0.00	94.58	0.78			94.19	0.00	96.65	0.00	95.61	0.24	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.4179618504
94.43	0.15	94.07	0.01	91.23	0.62	94.83	0.25			94.20	0.01	96.65	0.00	95.61	0.00	/workspace/coverage/cover_reg_top/19.chip_tl_errors.1159940824
94.58	0.14	94.07	0.00	91.27	0.04	94.83	0.00			94.20	0.00	96.65	0.00	96.43	0.81	/workspace/coverage/cover_reg_top/56.xbar_access_same_device_slow_rsp.39060444
94.70	0.12	94.28	0.22	91.48	0.21	95.06	0.22			94.28	0.08	96.65	0.00	96.43	0.00	/workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.4268635414
94.81	0.11	94.28	0.00	91.48	0.01	95.08	0.02			94.28	0.00	96.65	0.00	97.08	0.66	/workspace/coverage/cover_reg_top/73.xbar_smoke_large_delays.3102173239
94.92	0.11	94.28	0.00	91.80	0.32	95.08	0.00			94.65	0.36	96.65	0.00	97.08	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.2178837401
95.01	0.09	94.29	0.01	91.80	0.01	95.59	0.51			94.65	0.00	96.65	0.00	97.08	0.00	/workspace/coverage/default/91.chip_sw_all_escalation_resets.1814814480
95.09	0.08	94.29	0.00	92.27	0.47	95.59	0.00			94.65	0.00	96.65	0.00	97.11	0.02	/workspace/coverage/cover_reg_top/18.chip_tl_errors.2811728126
95.17	0.08	94.33	0.05	92.30	0.03	95.74	0.15			94.68	0.03	96.84	0.19	97.12	0.01	/workspace/coverage/default/79.chip_sw_all_escalation_resets.1795315752
95.24	0.07	94.33	0.00	92.30	0.00	96.15	0.41			94.68	0.00	96.84	0.00	97.12	0.00	/workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.2414183367
95.31	0.07	94.51	0.17	92.53	0.22	96.16	0.01			94.68	0.00	96.84	0.00	97.12	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.799455173
95.37	0.07	94.51	0.00	92.55	0.02	96.19	0.02			94.68	0.00	96.84	0.00	97.48	0.36	/workspace/coverage/cover_reg_top/19.xbar_access_same_device_slow_rsp.3196144830
95.44	0.07	94.63	0.13	92.57	0.02	96.44	0.26			94.68	0.00	96.84	0.00	97.48	0.00	/workspace/coverage/default/0.chip_sw_power_virus.1941092131
95.50	0.06	94.72	0.09	92.60	0.04	96.66	0.22			94.70	0.02	96.84	0.00	97.48	0.00	/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.1186641768
95.56	0.06	94.72	0.00	92.94	0.34	96.66	0.00			94.70	0.00	96.84	0.00	97.48	0.00	/workspace/coverage/default/2.chip_plic_all_irqs.4292997760
95.61	0.05	94.78	0.05	93.18	0.23	96.69	0.02			94.72	0.02	96.84	0.00	97.48	0.00	/workspace/coverage/cover_reg_top/15.chip_same_csr_outstanding.1943366886
95.67	0.05	94.81	0.03	93.21	0.03	96.70	0.01			94.75	0.03	97.03	0.19	97.50	0.01	/workspace/coverage/default/73.chip_sw_all_escalation_resets.976852690
95.72	0.05	94.90	0.09	93.34	0.13	96.70	0.00			94.84	0.09	97.03	0.00	97.50	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_retention.875415086
95.76	0.05	94.90	0.00	93.47	0.13	96.70	0.00			94.99	0.15	97.03	0.00	97.50	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.3701777634
95.81	0.05	94.90	0.00	93.47	0.00	96.97	0.27			94.99	0.00	97.03	0.00	97.50	0.00	/workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.3942759590
95.85	0.04	94.92	0.03	93.49	0.02	96.97	0.01			95.01	0.02	97.21	0.19	97.50	0.00	/workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.2998076639
95.89	0.04	94.94	0.01	93.50	0.01	96.98	0.01			95.03	0.02	97.40	0.19	97.51	0.01	/workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.4197787521
95.93	0.04	95.10	0.17	93.55	0.05	96.99	0.01			95.03	0.00	97.40	0.00	97.51	0.00	/workspace/coverage/default/0.chip_sw_gpio.3400933273
95.97	0.04	95.10	0.00	93.55	0.00	96.99	0.00			95.03	0.00	97.40	0.00	97.74	0.24	/workspace/coverage/cover_reg_top/39.xbar_access_same_device_slow_rsp.607966302
96.01	0.04	95.10	0.00	93.79	0.23	96.99	0.00			95.03	0.00	97.40	0.00	97.74	0.00	/workspace/coverage/cover_reg_top/9.chip_tl_errors.2452479301
96.05	0.04	95.11	0.01	93.80	0.01	97.00	0.01			95.03	0.01	97.58	0.19	97.75	0.01	/workspace/coverage/default/21.chip_sw_all_escalation_resets.666672101
96.08	0.04	95.23	0.12	93.85	0.05	97.01	0.01			95.07	0.03	97.58	0.00	97.75	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_wake.3657146353
96.12	0.03	95.23	0.01	93.85	0.01	97.02	0.01			95.07	0.00	97.77	0.19	97.75	0.00	/workspace/coverage/default/0.chip_sw_data_integrity_escalation.2364068697
96.15	0.03	95.23	0.00	93.88	0.03	97.02	0.00			95.08	0.01	97.77	0.00	97.91	0.15	/workspace/coverage/cover_reg_top/36.xbar_access_same_device_slow_rsp.2575108965
96.18	0.03	95.23	0.00	93.88	0.00	97.02	0.00			95.08	0.00	97.96	0.19	97.91	0.00	/workspace/coverage/default/2.chip_sw_data_integrity_escalation.4204672615
96.21	0.03	95.23	0.00	93.91	0.03	97.03	0.01			95.08	0.00	97.96	0.00	98.05	0.14	/workspace/coverage/default/0.chip_sw_alert_test.1262214569
96.24	0.03	95.23	0.00	93.91	0.00	97.19	0.16			95.08	0.00	97.96	0.00	98.05	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.862978479
96.26	0.03	95.23	0.00	93.93	0.02	97.19	0.00			95.08	0.00	97.96	0.00	98.19	0.14	/workspace/coverage/cover_reg_top/86.xbar_stress_all.1765756941
96.28	0.02	95.23	0.00	93.93	0.00	97.33	0.14			95.08	0.00	97.96	0.00	98.19	0.00	/workspace/coverage/default/0.chip_sw_flash_rma_unlocked.2533933074
96.31	0.02	95.31	0.07	93.93	0.00	97.37	0.04			95.08	0.01	97.96	0.00	98.19	0.00	/workspace/coverage/default/1.chip_tap_straps_rma.3347052830
96.33	0.02	95.31	0.00	93.93	0.00	97.50	0.12			95.08	0.00	97.96	0.00	98.19	0.00	/workspace/coverage/default/1.rom_e2e_asm_init_prod.4284709970
96.35	0.02	95.31	0.00	93.93	0.00	97.50	0.00			95.08	0.00	97.96	0.00	98.31	0.12	/workspace/coverage/cover_reg_top/30.xbar_access_same_device.2872818751
96.36	0.02	95.34	0.04	93.98	0.05	97.50	0.01			95.10	0.02	97.96	0.00	98.31	0.00	/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.1350512868
96.38	0.02	95.34	0.00	93.98	0.00	97.50	0.00			95.10	0.00	97.96	0.00	98.41	0.11	/workspace/coverage/cover_reg_top/82.xbar_stress_all_with_reset_error.2662873834
96.40	0.02	95.34	0.00	94.08	0.10	97.50	0.00			95.10	0.00	97.96	0.00	98.41	0.00	/workspace/coverage/cover_reg_top/0.chip_tl_errors.3299355376
96.42	0.02	95.34	0.00	94.18	0.10	97.50	0.00			95.10	0.00	97.96	0.00	98.41	0.00	/workspace/coverage/default/1.chip_plic_all_irqs.1653101648
96.43	0.01	95.35	0.01	94.18	0.01	97.57	0.07			95.10	0.00	97.96	0.00	98.41	0.00	/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.1246326125
96.44	0.01	95.35	0.00	94.18	0.00	97.57	0.00			95.10	0.00	97.96	0.00	98.49	0.08	/workspace/coverage/cover_reg_top/75.xbar_stress_all_with_reset_error.1556415048
96.46	0.01	95.39	0.04	94.21	0.03	97.57	0.00			95.11	0.01	97.96	0.00	98.49	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_wake.3480392048
96.47	0.01	95.42	0.02	94.23	0.01	97.60	0.03			95.11	0.00	97.96	0.00	98.49	0.00	/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.819031324
96.48	0.01	95.42	0.00	94.23	0.00	97.60	0.00			95.11	0.00	97.96	0.00	98.55	0.06	/workspace/coverage/cover_reg_top/35.xbar_stress_all_with_reset_error.2343205959
96.49	0.01	95.42	0.00	94.23	0.00	97.60	0.00			95.11	0.00	97.96	0.00	98.61	0.06	/workspace/coverage/cover_reg_top/77.xbar_stress_all_with_rand_reset.2214495038
96.50	0.01	95.42	0.00	94.23	0.00	97.66	0.06			95.11	0.00	97.96	0.00	98.61	0.00	/workspace/coverage/default/1.chip_sw_flash_rma_unlocked.632582007
96.51	0.01	95.45	0.03	94.23	0.01	97.66	0.01			95.13	0.02	97.96	0.00	98.61	0.00	/workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.2874887263
96.51	0.01	95.45	0.00	94.24	0.01	97.71	0.04			95.13	0.00	97.96	0.00	98.61	0.00	/workspace/coverage/cover_reg_top/14.chip_csr_rw.923317942
96.52	0.01	95.45	0.00	94.24	0.00	97.71	0.00			95.13	0.00	97.96	0.00	98.66	0.05	/workspace/coverage/cover_reg_top/35.xbar_stress_all_with_rand_reset.762782092
96.53	0.01	95.45	0.00	94.24	0.00	97.75	0.05			95.13	0.00	97.96	0.00	98.66	0.00	/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.2008162921
96.54	0.01	95.45	0.01	94.26	0.01	97.77	0.02			95.13	0.01	97.96	0.00	98.66	0.00	/workspace/coverage/default/0.chip_sw_usbdev_dpi.292444134
96.54	0.01	95.45	0.00	94.26	0.01	97.77	0.00			95.13	0.00	97.96	0.00	98.69	0.04	/workspace/coverage/cover_reg_top/98.xbar_stress_all_with_rand_reset.3617434442
96.55	0.01	95.45	0.00	94.30	0.04	97.77	0.00			95.13	0.00	97.96	0.00	98.69	0.00	/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.2550234028
96.56	0.01	95.45	0.00	94.30	0.01	97.78	0.01			95.14	0.01	97.96	0.00	98.71	0.01	/workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.1588391131
96.56	0.01	95.46	0.01	94.33	0.03	97.78	0.00			95.14	0.00	97.96	0.00	98.71	0.00	/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.2378201330
96.57	0.01	95.46	0.00	94.33	0.00	97.78	0.00			95.14	0.00	97.96	0.00	98.74	0.04	/workspace/coverage/cover_reg_top/38.xbar_stress_all_with_error.3765238901
96.57	0.01	95.46	0.00	94.33	0.00	97.78	0.00			95.14	0.00	97.96	0.00	98.78	0.04	/workspace/coverage/cover_reg_top/87.xbar_stress_all_with_reset_error.3153542753
96.58	0.01	95.46	0.00	94.33	0.00	97.81	0.03			95.14	0.00	97.96	0.00	98.78	0.00	/workspace/coverage/default/0.chip_sw_flash_init.3023554993
96.58	0.01	95.46	0.00	94.33	0.00	97.84	0.03			95.14	0.00	97.96	0.00	98.78	0.00	/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2383037771
96.59	0.01	95.46	0.00	94.33	0.00	97.87	0.03			95.14	0.00	97.96	0.00	98.78	0.00	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.1454730212
96.59	0.01	95.46	0.00	94.36	0.03	97.87	0.00			95.14	0.00	97.96	0.00	98.78	0.00	/workspace/coverage/cover_reg_top/12.chip_tl_errors.2227754598
96.60	0.01	95.46	0.00	94.36	0.00	97.87	0.00			95.14	0.00	97.96	0.00	98.80	0.02	/workspace/coverage/cover_reg_top/20.xbar_stress_all_with_error.704313789
96.60	0.01	95.46	0.00	94.36	0.00	97.87	0.00			95.14	0.00	97.96	0.00	98.82	0.02	/workspace/coverage/cover_reg_top/20.xbar_stress_all_with_rand_reset.1134639931
96.61	0.01	95.47	0.01	94.36	0.00	97.88	0.01			95.14	0.00	97.96	0.00	98.84	0.01	/workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.853942336
96.61	0.01	95.47	0.00	94.36	0.00	97.90	0.02			95.14	0.00	97.96	0.00	98.84	0.00	/workspace/coverage/cover_reg_top/4.chip_csr_hw_reset.3174031737
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96.79	0.01	95.48	0.00	94.44	0.00	98.06	0.01			95.14	0.00	97.96	0.00	99.67	0.00	/workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.2621270652
96.79	0.01	95.48	0.00	94.45	0.01	98.06	0.01			95.14	0.00	97.96	0.00	99.67	0.00	/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.159522529
96.80	0.01	95.49	0.01	94.45	0.01	98.06	0.01			95.14	0.00	97.96	0.00	99.67	0.00	/workspace/coverage/default/0.chip_sw_spi_host_tx_rx.3168650067
96.80	0.01	95.49	0.00	94.45	0.00	98.06	0.00			95.15	0.01	97.96	0.00	99.67	0.00	/workspace/coverage/default/2.chip_tap_straps_dev.2585822827
96.80	0.01	95.49	0.00	94.46	0.01	98.06	0.00			95.15	0.00	97.96	0.00	99.67	0.00	/workspace/coverage/cover_reg_top/3.chip_tl_errors.2473997298
96.80	0.01	95.49	0.00	94.47	0.01	98.06	0.00			95.15	0.00	97.96	0.00	99.67	0.00	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops.153114784
96.80	0.01	95.49	0.00	94.47	0.00	98.07	0.01			95.15	0.00	97.96	0.00	99.67	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.1287994432
96.80	0.01	95.49	0.00	94.47	0.00	98.07	0.01			95.15	0.00	97.96	0.00	99.67	0.00	/workspace/coverage/default/0.chip_tap_straps_rma.3345517491
96.80	0.01	95.49	0.00	94.47	0.01	98.07	0.00			95.15	0.00	97.96	0.00	99.67	0.00	/workspace/coverage/cover_reg_top/1.chip_tl_errors.1833249474
96.80	0.01	95.49	0.00	94.48	0.01	98.07	0.00			95.15	0.00	97.96	0.00	99.67	0.00	/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.4000925198
96.80	0.01	95.49	0.00	94.48	0.01	98.07	0.00			95.15	0.00	97.96	0.00	99.67	0.00	/workspace/coverage/cover_reg_top/24.xbar_stress_all_with_reset_error.1557652356
96.80	0.01	95.49	0.00	94.48	0.01	98.07	0.00			95.15	0.00	97.96	0.00	99.67	0.00	/workspace/coverage/cover_reg_top/25.xbar_stress_all_with_reset_error.3739319741
96.80	0.01	95.49	0.00	94.49	0.01	98.07	0.00			95.15	0.00	97.96	0.00	99.67	0.00	/workspace/coverage/cover_reg_top/32.xbar_stress_all_with_reset_error.727191193
96.80	0.01	95.49	0.00	94.49	0.01	98.07	0.00			95.15	0.00	97.96	0.00	99.67	0.00	/workspace/coverage/cover_reg_top/4.xbar_stress_all_with_reset_error.3482314679
96.80	0.01	95.49	0.00	94.49	0.01	98.07	0.00			95.15	0.00	97.96	0.00	99.67	0.00	/workspace/coverage/cover_reg_top/50.xbar_stress_all_with_reset_error.4075699156
96.81	0.01	95.49	0.00	94.50	0.01	98.07	0.00			95.15	0.00	97.96	0.00	99.67	0.00	/workspace/coverage/cover_reg_top/61.xbar_stress_all_with_error.3378464035
96.81	0.01	95.49	0.00	94.50	0.01	98.07	0.00			95.15	0.00	97.96	0.00	99.67	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.3202219820
96.81	0.01	95.49	0.00	94.50	0.01	98.07	0.00			95.15	0.00	97.96	0.00	99.67	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.2437594765
96.81	0.01	95.49	0.00	94.51	0.01	98.07	0.00			95.15	0.00	97.96	0.00	99.67	0.00	/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.741353912
96.81	0.01	95.49	0.00	94.51	0.01	98.07	0.00			95.15	0.00	97.96	0.00	99.67	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.2293075902
96.81	0.01	95.49	0.01	94.51	0.00	98.07	0.00			95.15	0.00	97.96	0.00	99.67	0.00	/workspace/coverage/default/0.chip_sw_plic_sw_irq.34830550
96.81	0.01	95.49	0.00	94.51	0.00	98.07	0.01			95.15	0.00	97.96	0.00	99.67	0.00	/workspace/coverage/cover_reg_top/2.chip_csr_hw_reset.498090376
96.81	0.01	95.49	0.00	94.51	0.00	98.08	0.01			95.15	0.00	97.96	0.00	99.67	0.00	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs.3918210386
96.81	0.01	95.49	0.00	94.51	0.00	98.08	0.01			95.15	0.00	97.96	0.00	99.67	0.00	/workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.418102170
96.81	0.01	95.49	0.00	94.51	0.00	98.08	0.01			95.15	0.00	97.96	0.00	99.67	0.00	/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.4018263458
96.81	0.01	95.49	0.00	94.51	0.00	98.08	0.01			95.15	0.00	97.96	0.00	99.67	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.1185514008
96.81	0.01	95.49	0.00	94.51	0.00	98.09	0.01			95.15	0.00	97.96	0.00	99.67	0.00	/workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.235010765
96.81	0.01	95.49	0.00	94.51	0.00	98.09	0.01			95.15	0.00	97.96	0.00	99.67	0.00	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.1217001176

---

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.chip_csr_aliasing.404214509
/workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.156184949
/workspace/coverage/cover_reg_top/0.chip_csr_mem_rw_with_rand_reset.2326944281
/workspace/coverage/cover_reg_top/0.chip_csr_rw.199930016
/workspace/coverage/cover_reg_top/0.chip_prim_tl_access.3454846436
/workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.2815063483
/workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.3139125641
/workspace/coverage/cover_reg_top/0.xbar_access_same_device.2977195357
/workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.3312580931
/workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.1198589222
/workspace/coverage/cover_reg_top/0.xbar_error_random.937851836
/workspace/coverage/cover_reg_top/0.xbar_random.3375916657
/workspace/coverage/cover_reg_top/0.xbar_random_large_delays.2386419116
/workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.280140674
/workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.1919156197
/workspace/coverage/cover_reg_top/0.xbar_same_source.3903923534
/workspace/coverage/cover_reg_top/0.xbar_smoke.2632249905
/workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.2724385416
/workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.2331441864
/workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.3633871411
/workspace/coverage/cover_reg_top/0.xbar_stress_all.107826975
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.2539614791
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.3063349145
/workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.2891407179
/workspace/coverage/cover_reg_top/1.chip_csr_aliasing.1760116560
/workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.243685896
/workspace/coverage/cover_reg_top/1.chip_csr_mem_rw_with_rand_reset.1294150637
/workspace/coverage/cover_reg_top/1.chip_csr_rw.2548387650
/workspace/coverage/cover_reg_top/1.chip_prim_tl_access.1581906679
/workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.3758484924
/workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.1435006123
/workspace/coverage/cover_reg_top/1.xbar_access_same_device.2006996216
/workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.282121775
/workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.3902009125
/workspace/coverage/cover_reg_top/1.xbar_error_random.636690736
/workspace/coverage/cover_reg_top/1.xbar_random.288070678
/workspace/coverage/cover_reg_top/1.xbar_random_large_delays.4103583947
/workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.3285221715
/workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.107638157
/workspace/coverage/cover_reg_top/1.xbar_same_source.580147461
/workspace/coverage/cover_reg_top/1.xbar_smoke.1454446598
/workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.1851650804
/workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.1076537086
/workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.3366224862
/workspace/coverage/cover_reg_top/1.xbar_stress_all.2694891037
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.172231981
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.2364416859
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.2421516898
/workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.2588287546
/workspace/coverage/cover_reg_top/10.chip_csr_mem_rw_with_rand_reset.375208685
/workspace/coverage/cover_reg_top/10.chip_csr_rw.1138858252
/workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.2897291744
/workspace/coverage/cover_reg_top/10.chip_tl_errors.2614149117
/workspace/coverage/cover_reg_top/10.xbar_access_same_device.3305883054
/workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.2333923472
/workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.2419417010
/workspace/coverage/cover_reg_top/10.xbar_error_random.2079902947
/workspace/coverage/cover_reg_top/10.xbar_random.2937380804
/workspace/coverage/cover_reg_top/10.xbar_random_large_delays.1109791990
/workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.1174460854
/workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.3159998864
/workspace/coverage/cover_reg_top/10.xbar_same_source.3195850563
/workspace/coverage/cover_reg_top/10.xbar_smoke.861857767
/workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.3914096668
/workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.548088206
/workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.2188148774
/workspace/coverage/cover_reg_top/10.xbar_stress_all.2709231597
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.433427290
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.3848703925
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.2565084362
/workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.788317035
/workspace/coverage/cover_reg_top/11.chip_csr_mem_rw_with_rand_reset.3192469713
/workspace/coverage/cover_reg_top/11.chip_csr_rw.743613728
/workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.1772182090
/workspace/coverage/cover_reg_top/11.chip_tl_errors.730961614
/workspace/coverage/cover_reg_top/11.xbar_access_same_device.1214602447
/workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.265919738
/workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.1531698745
/workspace/coverage/cover_reg_top/11.xbar_error_random.42243345
/workspace/coverage/cover_reg_top/11.xbar_random.3202760150
/workspace/coverage/cover_reg_top/11.xbar_random_large_delays.944548660
/workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.2226876054
/workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.61973936
/workspace/coverage/cover_reg_top/11.xbar_same_source.1293351324
/workspace/coverage/cover_reg_top/11.xbar_smoke.876593431
/workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.859915207
/workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.691924394
/workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.1807341184
/workspace/coverage/cover_reg_top/11.xbar_stress_all.3151456180
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.4243855179
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.2881051320
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.2349335756
/workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.1619516268
/workspace/coverage/cover_reg_top/12.chip_csr_mem_rw_with_rand_reset.4055306401
/workspace/coverage/cover_reg_top/12.chip_csr_rw.970041517
/workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.2784808360
/workspace/coverage/cover_reg_top/12.xbar_access_same_device.149176369
/workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.1151548979
/workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.213379443
/workspace/coverage/cover_reg_top/12.xbar_error_random.2210375295
/workspace/coverage/cover_reg_top/12.xbar_random.2512416827
/workspace/coverage/cover_reg_top/12.xbar_random_large_delays.3577474584
/workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.3277739431
/workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.588647133
/workspace/coverage/cover_reg_top/12.xbar_same_source.3198613250
/workspace/coverage/cover_reg_top/12.xbar_smoke.1071032611
/workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.685476197
/workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.505330532
/workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.2628206084
/workspace/coverage/cover_reg_top/12.xbar_stress_all.2214763929
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.778214202
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.1917953170
/workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.60742089
/workspace/coverage/cover_reg_top/13.chip_csr_mem_rw_with_rand_reset.308271640
/workspace/coverage/cover_reg_top/13.chip_csr_rw.2356601487
/workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.2886368481
/workspace/coverage/cover_reg_top/13.chip_tl_errors.1770716295
/workspace/coverage/cover_reg_top/13.xbar_access_same_device.3790299985
/workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.2114297470
/workspace/coverage/cover_reg_top/13.xbar_error_random.257997591
/workspace/coverage/cover_reg_top/13.xbar_random.1381873274
/workspace/coverage/cover_reg_top/13.xbar_random_large_delays.3556653962
/workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.274318498
/workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.3402544432
/workspace/coverage/cover_reg_top/13.xbar_same_source.3383311026
/workspace/coverage/cover_reg_top/13.xbar_smoke.2351903750
/workspace/coverage/cover_reg_top/13.xbar_smoke_large_delays.1554699779
/workspace/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.3598040276
/workspace/coverage/cover_reg_top/13.xbar_smoke_zero_delays.2150310150
/workspace/coverage/cover_reg_top/13.xbar_stress_all.2836515484
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_error.3388816121
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.3877358336
/workspace/coverage/cover_reg_top/13.xbar_unmapped_addr.823117697
/workspace/coverage/cover_reg_top/14.chip_csr_mem_rw_with_rand_reset.3536559850
/workspace/coverage/cover_reg_top/14.chip_tl_errors.3938319395
/workspace/coverage/cover_reg_top/14.xbar_access_same_device.3258691646
/workspace/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.3583998639
/workspace/coverage/cover_reg_top/14.xbar_error_and_unmapped_addr.3820982931
/workspace/coverage/cover_reg_top/14.xbar_error_random.4050492003
/workspace/coverage/cover_reg_top/14.xbar_random.2510271306
/workspace/coverage/cover_reg_top/14.xbar_random_large_delays.669999397
/workspace/coverage/cover_reg_top/14.xbar_random_slow_rsp.2107248104
/workspace/coverage/cover_reg_top/14.xbar_random_zero_delays.1480940695
/workspace/coverage/cover_reg_top/14.xbar_same_source.2711396048
/workspace/coverage/cover_reg_top/14.xbar_smoke.306772466
/workspace/coverage/cover_reg_top/14.xbar_smoke_large_delays.1214964350
/workspace/coverage/cover_reg_top/14.xbar_smoke_slow_rsp.1823256851
/workspace/coverage/cover_reg_top/14.xbar_smoke_zero_delays.74962568
/workspace/coverage/cover_reg_top/14.xbar_stress_all.1438155503
/workspace/coverage/cover_reg_top/14.xbar_stress_all_with_error.2979945046
/workspace/coverage/cover_reg_top/14.xbar_stress_all_with_rand_reset.3456373937
/workspace/coverage/cover_reg_top/14.xbar_stress_all_with_reset_error.2856566880
/workspace/coverage/cover_reg_top/14.xbar_unmapped_addr.1734805918
/workspace/coverage/cover_reg_top/15.chip_csr_mem_rw_with_rand_reset.104943568
/workspace/coverage/cover_reg_top/15.chip_csr_rw.2108419588
/workspace/coverage/cover_reg_top/15.chip_tl_errors.717665429
/workspace/coverage/cover_reg_top/15.xbar_access_same_device.3598634724
/workspace/coverage/cover_reg_top/15.xbar_access_same_device_slow_rsp.3721342581
/workspace/coverage/cover_reg_top/15.xbar_error_and_unmapped_addr.853707030
/workspace/coverage/cover_reg_top/15.xbar_error_random.2119204208
/workspace/coverage/cover_reg_top/15.xbar_random.3576064865
/workspace/coverage/cover_reg_top/15.xbar_random_large_delays.1555585921
/workspace/coverage/cover_reg_top/15.xbar_random_slow_rsp.4294853572
/workspace/coverage/cover_reg_top/15.xbar_random_zero_delays.2041918205
/workspace/coverage/cover_reg_top/15.xbar_same_source.4088237493
/workspace/coverage/cover_reg_top/15.xbar_smoke.1809315766
/workspace/coverage/cover_reg_top/15.xbar_smoke_large_delays.2873331736
/workspace/coverage/cover_reg_top/15.xbar_smoke_slow_rsp.2814138936
/workspace/coverage/cover_reg_top/15.xbar_smoke_zero_delays.1476025981
/workspace/coverage/cover_reg_top/15.xbar_stress_all_with_error.993881952
/workspace/coverage/cover_reg_top/15.xbar_stress_all_with_rand_reset.3851229769
/workspace/coverage/cover_reg_top/15.xbar_stress_all_with_reset_error.3451328024
/workspace/coverage/cover_reg_top/15.xbar_unmapped_addr.3471812425
/workspace/coverage/cover_reg_top/16.chip_csr_mem_rw_with_rand_reset.402188866
/workspace/coverage/cover_reg_top/16.chip_csr_rw.1266266121
/workspace/coverage/cover_reg_top/16.chip_same_csr_outstanding.1521324328
/workspace/coverage/cover_reg_top/16.xbar_access_same_device.3860320017
/workspace/coverage/cover_reg_top/16.xbar_access_same_device_slow_rsp.2925075470
/workspace/coverage/cover_reg_top/16.xbar_error_and_unmapped_addr.1893711328
/workspace/coverage/cover_reg_top/16.xbar_error_random.1518581600
/workspace/coverage/cover_reg_top/16.xbar_random.3985194848
/workspace/coverage/cover_reg_top/16.xbar_random_large_delays.725399650
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/workspace/coverage/default/2.rom_e2e_sigverify_mod_exp_prod_end_otbn.863406532
/workspace/coverage/default/2.rom_e2e_sigverify_mod_exp_prod_end_sw.1987005130
/workspace/coverage/default/2.rom_e2e_sigverify_mod_exp_prod_otbn.1199357045
/workspace/coverage/default/2.rom_e2e_sigverify_mod_exp_prod_sw.378797536
/workspace/coverage/default/2.rom_e2e_sigverify_mod_exp_rma_otbn.2089523737
/workspace/coverage/default/2.rom_e2e_sigverify_mod_exp_rma_sw.296748091
/workspace/coverage/default/2.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn.3529493493
/workspace/coverage/default/2.rom_e2e_sigverify_mod_exp_test_unlocked0_sw.1435758421
/workspace/coverage/default/2.rom_e2e_smoke.1260846282
/workspace/coverage/default/2.rom_e2e_static_critical.3051717547
/workspace/coverage/default/2.rom_keymgr_functest.2510064582
/workspace/coverage/default/2.rom_volatile_raw_unlock.4245295177
/workspace/coverage/default/20.chip_sw_all_escalation_resets.2650794316
/workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.2197749368
/workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.101458870
/workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.3763551731
/workspace/coverage/default/23.chip_sw_all_escalation_resets.3037203085
/workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.1679406555
/workspace/coverage/default/26.chip_sw_all_escalation_resets.2962447800
/workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.4225636629
/workspace/coverage/default/27.chip_sw_all_escalation_resets.4185934258
/workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.3593033091
/workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.2828494337
/workspace/coverage/default/29.chip_sw_all_escalation_resets.1440869098
/workspace/coverage/default/3.chip_padctrl_attributes.2031158029
/workspace/coverage/default/3.chip_sw_all_escalation_resets.1993106458
/workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.2968136843
/workspace/coverage/default/3.chip_sw_data_integrity_escalation.1055242981
/workspace/coverage/default/3.chip_sw_lc_ctrl_transition.1535858934
/workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.2637114181
/workspace/coverage/default/3.chip_sw_uart_rand_baudrate.222275757
/workspace/coverage/default/3.chip_sw_uart_tx_rx.764402506
/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.1815991124
/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1358261777
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.1061802389
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.2232527342
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.1803640289
/workspace/coverage/default/3.chip_tap_straps_dev.4153331154
/workspace/coverage/default/3.chip_tap_straps_prod.2419934424
/workspace/coverage/default/3.chip_tap_straps_rma.596689586
/workspace/coverage/default/3.chip_tap_straps_testunlock0.703364039
/workspace/coverage/default/30.chip_sw_all_escalation_resets.3623177517
/workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.2380244232
/workspace/coverage/default/32.chip_sw_all_escalation_resets.3919258037
/workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.375769100
/workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.3888521222
/workspace/coverage/default/35.chip_sw_all_escalation_resets.3997966942
/workspace/coverage/default/36.chip_sw_all_escalation_resets.2267831603
/workspace/coverage/default/38.chip_sw_all_escalation_resets.856317581
/workspace/coverage/default/39.chip_sw_all_escalation_resets.80193610
/workspace/coverage/default/4.chip_padctrl_attributes.1901088821
/workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.1551709761
/workspace/coverage/default/4.chip_sw_all_escalation_resets.899083745
/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.3600257316
/workspace/coverage/default/4.chip_sw_data_integrity_escalation.729149140
/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.3922827861
/workspace/coverage/default/4.chip_sw_uart_rand_baudrate.1487058902
/workspace/coverage/default/4.chip_sw_uart_tx_rx.2666943472
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.576959777
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1442492665
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.870236048
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.865533517
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.3738161349
/workspace/coverage/default/4.chip_tap_straps_dev.971943238
/workspace/coverage/default/4.chip_tap_straps_prod.1250542417
/workspace/coverage/default/4.chip_tap_straps_rma.4186048907
/workspace/coverage/default/4.chip_tap_straps_testunlock0.3619252251
/workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.152464880
/workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.1789237803
/workspace/coverage/default/42.chip_sw_all_escalation_resets.1254197033
/workspace/coverage/default/43.chip_sw_all_escalation_resets.3725135688
/workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.1006731197
/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.3068032518
/workspace/coverage/default/45.chip_sw_all_escalation_resets.1642669660
/workspace/coverage/default/46.chip_sw_all_escalation_resets.3475290732
/workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.4219016205
/workspace/coverage/default/48.chip_sw_all_escalation_resets.2160504341
/workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.1377046936
/workspace/coverage/default/49.chip_sw_all_escalation_resets.4046647779
/workspace/coverage/default/5.chip_padctrl_attributes.171191101
/workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.1645662807
/workspace/coverage/default/5.chip_sw_all_escalation_resets.2001329392
/workspace/coverage/default/5.chip_sw_data_integrity_escalation.1489495383
/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.468525111
/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.4012811903
/workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.3532717041
/workspace/coverage/default/50.chip_sw_all_escalation_resets.1369391988
/workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.2054331270
/workspace/coverage/default/51.chip_sw_all_escalation_resets.335393499
/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.2245711582
/workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.1043069104
/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.3210244444
/workspace/coverage/default/57.chip_sw_all_escalation_resets.1641965234
/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.3767021592
/workspace/coverage/default/59.chip_sw_all_escalation_resets.3133296855
/workspace/coverage/default/6.chip_padctrl_attributes.3557570027
/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.3177258444
/workspace/coverage/default/6.chip_sw_all_escalation_resets.3444405647
/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.5815652
/workspace/coverage/default/60.chip_sw_all_escalation_resets.1111119326
/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.10699915
/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.4047439459
/workspace/coverage/default/62.chip_sw_all_escalation_resets.1750224016
/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.275340123
/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.2622975167
/workspace/coverage/default/64.chip_sw_all_escalation_resets.1107390706
/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.3021435275
/workspace/coverage/default/65.chip_sw_all_escalation_resets.946492981
/workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.2160577528
/workspace/coverage/default/67.chip_sw_all_escalation_resets.223065844
/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.878792037
/workspace/coverage/default/69.chip_sw_all_escalation_resets.454934999
/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.3016284914
/workspace/coverage/default/7.chip_sw_all_escalation_resets.441308872
/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.2055734388
/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.3476273281
/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.3939649317
/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.3981547896
/workspace/coverage/default/71.chip_sw_all_escalation_resets.3648320448
/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.200261271
/workspace/coverage/default/72.chip_sw_all_escalation_resets.3599809157
/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.484389219
/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.1369322918
/workspace/coverage/default/74.chip_sw_all_escalation_resets.1893162376
/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.1324513570
/workspace/coverage/default/75.chip_sw_all_escalation_resets.4230196175
/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.1665785984
/workspace/coverage/default/76.chip_sw_all_escalation_resets.4091819677
/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.2860462094
/workspace/coverage/default/77.chip_sw_all_escalation_resets.925172829
/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.2185243839
/workspace/coverage/default/78.chip_sw_all_escalation_resets.1385123175
/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.1868224292
/workspace/coverage/default/8.chip_padctrl_attributes.1877234278
/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.1772876427
/workspace/coverage/default/8.chip_sw_all_escalation_resets.484058764
/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.1040679769
/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.3939288626
/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.3590183642
/workspace/coverage/default/80.chip_sw_all_escalation_resets.3769711576
/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.2999359286
/workspace/coverage/default/81.chip_sw_all_escalation_resets.1904802411
/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.802414913
/workspace/coverage/default/83.chip_sw_all_escalation_resets.3812548660
/workspace/coverage/default/84.chip_sw_all_escalation_resets.1046623273
/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.529156685
/workspace/coverage/default/85.chip_sw_all_escalation_resets.3754398114
/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.215230286
/workspace/coverage/default/86.chip_sw_all_escalation_resets.417571955
/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.1009269991
/workspace/coverage/default/87.chip_sw_all_escalation_resets.2340436070
/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.3168447972
/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.2352061687
/workspace/coverage/default/89.chip_sw_all_escalation_resets.3246102937
/workspace/coverage/default/9.chip_padctrl_attributes.2684556180
/workspace/coverage/default/9.chip_sw_all_escalation_resets.1729318981
/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.384087564
/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.1036309075
/workspace/coverage/default/90.chip_sw_all_escalation_resets.1551705669
/workspace/coverage/default/92.chip_sw_all_escalation_resets.2171609000
/workspace/coverage/default/93.chip_sw_all_escalation_resets.881278889
/workspace/coverage/default/94.chip_sw_all_escalation_resets.1986890900
/workspace/coverage/default/95.chip_sw_all_escalation_resets.3107383500
/workspace/coverage/default/97.chip_sw_all_escalation_resets.1650146728
/workspace/coverage/default/98.chip_sw_all_escalation_resets.2410294249
/workspace/coverage/default/99.chip_sw_all_escalation_resets.2051059637

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Total test records in report: 2896

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TEST NO	TEST LOCATION	TEST NAME	STATUS	STARTED	FINISHED	SIMULATION TIME
T47	/workspace/coverage/cover_reg_top/11.xbar_random.3202760150			May 27 03:51:55 AM PDT 23	May 27 03:52:34 AM PDT 23	1015467324 ps
T48	/workspace/coverage/cover_reg_top/78.xbar_access_same_device_slow_rsp.2908346572			May 27 04:02:57 AM PDT 23	May 27 04:24:10 AM PDT 23	67518977073 ps
T49	/workspace/coverage/cover_reg_top/15.xbar_stress_all.357305213			May 27 03:53:09 AM PDT 23	May 27 03:57:04 AM PDT 23	2745136141 ps
T66	/workspace/coverage/cover_reg_top/73.xbar_smoke_large_delays.3102173239			May 27 04:01:53 AM PDT 23	May 27 04:03:28 AM PDT 23	9498760831 ps
T67	/workspace/coverage/cover_reg_top/66.xbar_unmapped_addr.3450077769			May 27 04:00:54 AM PDT 23	May 27 04:01:03 AM PDT 23	56494593 ps
T134	/workspace/coverage/cover_reg_top/41.xbar_stress_all_with_reset_error.4064852696			May 27 03:57:23 AM PDT 23	May 27 04:00:54 AM PDT 23	495317981 ps
T231	/workspace/coverage/cover_reg_top/57.xbar_smoke.1901870497			May 27 03:59:34 AM PDT 23	May 27 03:59:43 AM PDT 23	199611128 ps
T232	/workspace/coverage/cover_reg_top/94.xbar_smoke_large_delays.1237269636			May 27 04:05:10 AM PDT 23	May 27 04:06:20 AM PDT 23	6517762730 ps
T233	/workspace/coverage/cover_reg_top/27.xbar_error_random.2337367178			May 27 03:55:23 AM PDT 23	May 27 03:56:04 AM PDT 23	504050581 ps
T234	/workspace/coverage/cover_reg_top/93.xbar_error_random.861856154			May 27 04:05:09 AM PDT 23	May 27 04:06:01 AM PDT 23	1511661518 ps
T413	/workspace/coverage/cover_reg_top/15.xbar_random.3576064865			May 27 03:52:59 AM PDT 23	May 27 03:53:09 AM PDT 23	81729233 ps
T585	/workspace/coverage/cover_reg_top/19.xbar_access_same_device_slow_rsp.3196144830			May 27 03:53:39 AM PDT 23	May 27 04:11:02 AM PDT 23	60912244741 ps
T389	/workspace/coverage/cover_reg_top/16.xbar_random_zero_delays.1963892379			May 27 03:53:10 AM PDT 23	May 27 03:53:24 AM PDT 23	117016756 ps
T115	/workspace/coverage/cover_reg_top/28.xbar_stress_all_with_reset_error.2208181147			May 27 03:55:13 AM PDT 23	May 27 03:56:47 AM PDT 23	974876156 ps
T415	/workspace/coverage/cover_reg_top/64.xbar_stress_all_with_reset_error.2224981811			May 27 04:00:56 AM PDT 23	May 27 04:01:05 AM PDT 23	92176180 ps
T412	/workspace/coverage/cover_reg_top/71.xbar_stress_all_with_error.1629300528			May 27 04:01:44 AM PDT 23	May 27 04:03:04 AM PDT 23	916212583 ps
T398	/workspace/coverage/cover_reg_top/67.xbar_unmapped_addr.1691357627			May 27 04:01:09 AM PDT 23	May 27 04:01:32 AM PDT 23	549969251 ps
T414	/workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.2805205688			May 27 03:52:46 AM PDT 23	May 27 04:24:13 AM PDT 23	115363397069 ps
T350	/workspace/coverage/cover_reg_top/40.xbar_unmapped_addr.1386535865			May 27 03:57:25 AM PDT 23	May 27 03:58:07 AM PDT 23	996272105 ps
T418	/workspace/coverage/cover_reg_top/38.xbar_error_and_unmapped_addr.1244283054			May 27 03:57:24 AM PDT 23	May 27 03:57:56 AM PDT 23	903332118 ps
T416	/workspace/coverage/cover_reg_top/40.xbar_error_random.3742464933			May 27 03:57:09 AM PDT 23	May 27 03:58:30 AM PDT 23	2408447107 ps
T419	/workspace/coverage/cover_reg_top/8.xbar_smoke_zero_delays.2231516280			May 27 03:51:04 AM PDT 23	May 27 03:51:11 AM PDT 23	45683582 ps
T113	/workspace/coverage/cover_reg_top/49.xbar_stress_all_with_error.3379560455			May 27 03:58:49 AM PDT 23	May 27 04:09:23 AM PDT 23	17113428627 ps
T410	/workspace/coverage/cover_reg_top/25.xbar_smoke.3963985825			May 27 03:55:04 AM PDT 23	May 27 03:55:13 AM PDT 23	198734257 ps
T114	/workspace/coverage/cover_reg_top/38.xbar_stress_all_with_error.3765238901			May 27 03:57:07 AM PDT 23	May 27 04:04:44 AM PDT 23	12833088644 ps
T393	/workspace/coverage/cover_reg_top/6.xbar_smoke_slow_rsp.3831103994			May 27 03:50:34 AM PDT 23	May 27 03:51:38 AM PDT 23	3884489817 ps
T425	/workspace/coverage/cover_reg_top/71.xbar_error_and_unmapped_addr.3458824943			May 27 04:01:44 AM PDT 23	May 27 04:02:38 AM PDT 23	1283751273 ps
T420	/workspace/coverage/cover_reg_top/48.xbar_access_same_device.3869641286			May 27 03:58:40 AM PDT 23	May 27 03:59:39 AM PDT 23	1490560713 ps
T404	/workspace/coverage/cover_reg_top/59.xbar_smoke_zero_delays.833215585			May 27 04:00:01 AM PDT 23	May 27 04:00:08 AM PDT 23	53515311 ps
T401	/workspace/coverage/cover_reg_top/79.xbar_smoke_zero_delays.2143283562			May 27 04:03:29 AM PDT 23	May 27 04:03:35 AM PDT 23	44027358 ps
T44	/workspace/coverage/cover_reg_top/14.chip_csr_rw.923317942			May 27 03:52:54 AM PDT 23	May 27 03:57:22 AM PDT 23	3298898658 ps
T391	/workspace/coverage/cover_reg_top/58.xbar_random_slow_rsp.673357463			May 27 03:59:56 AM PDT 23	May 27 04:06:41 AM PDT 23	24057957538 ps
T423	/workspace/coverage/cover_reg_top/36.xbar_error_random.1103887116			May 27 03:56:37 AM PDT 23	May 27 03:57:00 AM PDT 23	235195679 ps
T600	/workspace/coverage/cover_reg_top/15.xbar_smoke_zero_delays.1476025981			May 27 03:53:04 AM PDT 23	May 27 03:53:10 AM PDT 23	48463955 ps
T361	/workspace/coverage/cover_reg_top/86.xbar_stress_all.1765756941			May 27 04:03:48 AM PDT 23	May 27 04:08:18 AM PDT 23	7832531353 ps
T390	/workspace/coverage/cover_reg_top/32.xbar_stress_all_with_rand_reset.41862458			May 27 03:56:10 AM PDT 23	May 27 03:58:36 AM PDT 23	505764231 ps
T552	/workspace/coverage/cover_reg_top/53.xbar_smoke.3925089414			May 27 03:59:12 AM PDT 23	May 27 03:59:18 AM PDT 23	32494649 ps
T417	/workspace/coverage/cover_reg_top/57.xbar_stress_all_with_error.1988349942			May 27 03:59:57 AM PDT 23	May 27 04:06:21 AM PDT 23	4254089685 ps
T362	/workspace/coverage/cover_reg_top/40.xbar_stress_all.4109745406			May 27 03:57:03 AM PDT 23	May 27 04:00:38 AM PDT 23	6895596840 ps
T407	/workspace/coverage/cover_reg_top/21.xbar_unmapped_addr.2511177352			May 27 03:55:00 AM PDT 23	May 27 03:55:18 AM PDT 23	150371818 ps
T395	/workspace/coverage/cover_reg_top/93.xbar_random_large_delays.2844507420			May 27 04:04:22 AM PDT 23	May 27 04:21:46 AM PDT 23	84208589830 ps
T351	/workspace/coverage/cover_reg_top/98.xbar_same_source.2662145766			May 27 04:05:26 AM PDT 23	May 27 04:05:58 AM PDT 23	431190496 ps
T352	/workspace/coverage/cover_reg_top/42.xbar_stress_all_with_rand_reset.1459577886			May 27 03:58:18 AM PDT 23	May 27 04:01:14 AM PDT 23	859952048 ps
T400	/workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.2891407179			May 27 03:50:04 AM PDT 23	May 27 03:50:41 AM PDT 23	261717899 ps
T386	/workspace/coverage/cover_reg_top/83.xbar_smoke_zero_delays.1618867179			May 27 04:03:36 AM PDT 23	May 27 04:03:42 AM PDT 23	37503205 ps
T399	/workspace/coverage/cover_reg_top/24.xbar_smoke_large_delays.2713998312			May 27 03:54:49 AM PDT 23	May 27 03:56:28 AM PDT 23	10224317500 ps
T623	/workspace/coverage/cover_reg_top/61.xbar_smoke_slow_rsp.1050394950			May 27 03:59:59 AM PDT 23	May 27 04:01:28 AM PDT 23	5272032004 ps
T469	/workspace/coverage/cover_reg_top/87.xbar_smoke.3700817884			May 27 04:03:51 AM PDT 23	May 27 04:04:00 AM PDT 23	211006138 ps
T405	/workspace/coverage/cover_reg_top/87.xbar_random_slow_rsp.4111774250			May 27 04:03:51 AM PDT 23	May 27 04:11:49 AM PDT 23	25087505319 ps
T45	/workspace/coverage/cover_reg_top/19.chip_tl_errors.1159940824			May 27 03:53:38 AM PDT 23	May 27 03:56:51 AM PDT 23	3186654310 ps
T816	/workspace/coverage/cover_reg_top/88.xbar_stress_all_with_reset_error.184386211			May 27 04:03:44 AM PDT 23	May 27 04:03:54 AM PDT 23	27730515 ps
T496	/workspace/coverage/cover_reg_top/90.xbar_random_large_delays.3133405599			May 27 04:04:19 AM PDT 23	May 27 04:07:35 AM PDT 23	19091366957 ps
T534	/workspace/coverage/cover_reg_top/80.xbar_smoke_large_delays.1874892493			May 27 04:03:22 AM PDT 23	May 27 04:04:18 AM PDT 23	5287780198 ps
T817	/workspace/coverage/cover_reg_top/88.xbar_error_and_unmapped_addr.2625388706			May 27 04:04:03 AM PDT 23	May 27 04:04:14 AM PDT 23	80132320 ps
T818	/workspace/coverage/cover_reg_top/7.xbar_smoke_slow_rsp.544201054			May 27 03:50:33 AM PDT 23	May 27 03:52:11 AM PDT 23	6428276713 ps
T426	/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.778214202			May 27 03:52:38 AM PDT 23	May 27 03:54:58 AM PDT 23	3817319918 ps
T789	/workspace/coverage/cover_reg_top/82.xbar_stress_all_with_reset_error.2662873834			May 27 04:03:36 AM PDT 23	May 27 04:07:01 AM PDT 23	606661239 ps
T598	/workspace/coverage/cover_reg_top/28.xbar_smoke_zero_delays.3323659961			May 27 03:55:16 AM PDT 23	May 27 03:55:22 AM PDT 23	42798042 ps
T772	/workspace/coverage/cover_reg_top/99.xbar_access_same_device.445961397			May 27 04:05:59 AM PDT 23	May 27 04:06:39 AM PDT 23	1099684648 ps
T599	/workspace/coverage/cover_reg_top/36.xbar_access_same_device_slow_rsp.2575108965			May 27 03:56:41 AM PDT 23	May 27 04:37:56 AM PDT 23	136208714910 ps
T579	/workspace/coverage/cover_reg_top/23.xbar_stress_all_with_error.1572107857			May 27 03:55:00 AM PDT 23	May 27 03:55:56 AM PDT 23	1563135571 ps
T819	/workspace/coverage/cover_reg_top/1.xbar_smoke.1454446598			May 27 03:50:10 AM PDT 23	May 27 03:50:20 AM PDT 23	221020533 ps
T806	/workspace/coverage/cover_reg_top/43.xbar_stress_all_with_reset_error.3700894083			May 27 03:58:08 AM PDT 23	May 27 03:58:47 AM PDT 23	150921548 ps
T421	/workspace/coverage/cover_reg_top/62.xbar_stress_all_with_reset_error.3567752615			May 27 04:00:36 AM PDT 23	May 27 04:00:53 AM PDT 23	74882392 ps
T424	/workspace/coverage/cover_reg_top/18.xbar_error_and_unmapped_addr.387924572			May 27 03:53:34 AM PDT 23	May 27 03:54:27 AM PDT 23	1384605252 ps
T754	/workspace/coverage/cover_reg_top/27.xbar_access_same_device.3989818832			May 27 03:55:21 AM PDT 23	May 27 03:57:20 AM PDT 23	2526438386 ps
T406	/workspace/coverage/cover_reg_top/64.xbar_random_slow_rsp.3393984399			May 27 04:00:47 AM PDT 23	May 27 04:03:06 AM PDT 23	8577607842 ps
T388	/workspace/coverage/cover_reg_top/22.xbar_random_zero_delays.2875536058			May 27 03:54:21 AM PDT 23	May 27 03:54:52 AM PDT 23	309713313 ps
T408	/workspace/coverage/cover_reg_top/29.xbar_unmapped_addr.3891476515			May 27 03:55:38 AM PDT 23	May 27 03:55:57 AM PDT 23	354197868 ps
T525	/workspace/coverage/cover_reg_top/93.xbar_random.1544993411			May 27 04:04:25 AM PDT 23	May 27 04:04:37 AM PDT 23	254689714 ps
T758	/workspace/coverage/cover_reg_top/63.xbar_access_same_device_slow_rsp.1037826474			May 27 04:00:38 AM PDT 23	May 27 04:24:33 AM PDT 23	83665586184 ps
T820	/workspace/coverage/cover_reg_top/62.xbar_error_and_unmapped_addr.1779579862			May 27 04:00:36 AM PDT 23	May 27 04:01:15 AM PDT 23	899484041 ps
T422	/workspace/coverage/cover_reg_top/78.xbar_stress_all_with_reset_error.1270801458			May 27 04:03:29 AM PDT 23	May 27 04:15:33 AM PDT 23	6705157156 ps
T387	/workspace/coverage/cover_reg_top/92.xbar_random_large_delays.2051896015			May 27 04:04:34 AM PDT 23	May 27 04:26:19 AM PDT 23	98012904720 ps
T402	/workspace/coverage/cover_reg_top/30.xbar_random_slow_rsp.3777011586			May 27 03:55:38 AM PDT 23	May 27 04:08:55 AM PDT 23	48975840088 ps
T821	/workspace/coverage/cover_reg_top/20.xbar_error_and_unmapped_addr.1279937712			May 27 03:54:19 AM PDT 23	May 27 03:54:26 AM PDT 23	28978875 ps
T822	/workspace/coverage/cover_reg_top/94.xbar_error_and_unmapped_addr.3477510404			May 27 04:05:10 AM PDT 23	May 27 04:05:28 AM PDT 23	407532563 ps
T46	/workspace/coverage/cover_reg_top/25.chip_tl_errors.3646967919			May 27 03:54:52 AM PDT 23	May 27 03:58:10 AM PDT 23	3008978799 ps
T823	/workspace/coverage/cover_reg_top/28.xbar_error_random.886040598			May 27 03:55:21 AM PDT 23	May 27 03:56:03 AM PDT 23	524005293 ps
T762	/workspace/coverage/cover_reg_top/46.xbar_stress_all_with_reset_error.3267112419			May 27 03:58:32 AM PDT 23	May 27 03:59:54 AM PDT 23	118218341 ps
T68	/workspace/coverage/cover_reg_top/4.chip_csr_bit_bash.3895026058			May 27 03:50:07 AM PDT 23	May 27 04:03:46 AM PDT 23	7935964866 ps
T824	/workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.1198589222			May 27 03:50:05 AM PDT 23	May 27 03:50:22 AM PDT 23	124763388 ps
T359	/workspace/coverage/cover_reg_top/94.xbar_access_same_device.2516180987			May 27 04:05:11 AM PDT 23	May 27 04:05:56 AM PDT 23	488150144 ps
T761	/workspace/coverage/cover_reg_top/83.xbar_stress_all_with_reset_error.2343736638			May 27 04:03:37 AM PDT 23	May 27 04:06:21 AM PDT 23	569712868 ps
T825	/workspace/coverage/cover_reg_top/3.xbar_smoke_slow_rsp.2880565469			May 27 03:50:03 AM PDT 23	May 27 03:51:20 AM PDT 23	4599681311 ps
T629	/workspace/coverage/cover_reg_top/30.xbar_error_random.749276614			May 27 03:55:47 AM PDT 23	May 27 03:56:23 AM PDT 23	423169509 ps
T799	/workspace/coverage/cover_reg_top/51.xbar_stress_all_with_reset_error.1008588773			May 27 03:59:13 AM PDT 23	May 27 03:59:25 AM PDT 23	7208292 ps
T409	/workspace/coverage/cover_reg_top/66.xbar_random_slow_rsp.3103359355			May 27 04:01:06 AM PDT 23	May 27 04:06:41 AM PDT 23	21414889522 ps
T826	/workspace/coverage/cover_reg_top/72.xbar_error_and_unmapped_addr.575832874			May 27 04:01:54 AM PDT 23	May 27 04:02:08 AM PDT 23	340147030 ps
T827	/workspace/coverage/cover_reg_top/53.xbar_error_and_unmapped_addr.3266885823			May 27 03:59:30 AM PDT 23	May 27 03:59:50 AM PDT 23	542758317 ps
T363	/workspace/coverage/cover_reg_top/79.xbar_same_source.3865562361			May 27 04:03:29 AM PDT 23	May 27 04:04:42 AM PDT 23	2687327280 ps
T394	/workspace/coverage/cover_reg_top/39.xbar_smoke.4284230946			May 27 03:57:06 AM PDT 23	May 27 03:57:12 AM PDT 23	41973264 ps
T397	/workspace/coverage/cover_reg_top/70.xbar_stress_all_with_rand_reset.3262628264			May 27 04:01:31 AM PDT 23	May 27 04:05:11 AM PDT 23	3066186898 ps
T64	/workspace/coverage/cover_reg_top/2.chip_csr_rw.1513987566			May 27 03:50:01 AM PDT 23	May 27 04:00:18 AM PDT 23	5588429488 ps
T396	/workspace/coverage/cover_reg_top/85.xbar_smoke_zero_delays.4168520604			May 27 04:03:42 AM PDT 23	May 27 04:03:49 AM PDT 23	47932108 ps
T743	/workspace/coverage/cover_reg_top/24.xbar_stress_all_with_error.2600320659			May 27 03:54:48 AM PDT 23	May 27 04:02:23 AM PDT 23	11650602013 ps
T1	/workspace/coverage/default/1.chip_sw_entropy_src_csrng.3464057888			May 27 04:19:40 AM PDT 23	May 27 04:35:04 AM PDT 23	5687241452 ps
T2	/workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.853942336			May 27 04:31:23 AM PDT 23	May 27 04:40:27 AM PDT 23	4251558884 ps
T3	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.4038780717			May 27 04:23:32 AM PDT 23	May 27 04:43:50 AM PDT 23	7126117150 ps
T20	/workspace/coverage/default/55.chip_sw_all_escalation_resets.779509792			May 27 04:34:36 AM PDT 23	May 27 04:48:52 AM PDT 23	5633114460 ps
T73	/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.3068032518			May 27 04:31:36 AM PDT 23	May 27 04:37:58 AM PDT 23	4404961812 ps
T21	/workspace/coverage/default/84.chip_sw_all_escalation_resets.1046623273			May 27 04:36:58 AM PDT 23	May 27 04:44:52 AM PDT 23	6153625960 ps
T4	/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2477082000			May 27 04:47:07 AM PDT 23	May 27 05:34:30 AM PDT 23	34372913184 ps
T74	/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.3981547896			May 27 04:38:12 AM PDT 23	May 27 04:45:30 AM PDT 23	3997503040 ps
T75	/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.1186641768			May 27 04:50:31 AM PDT 23	May 27 04:59:34 AM PDT 23	4653795192 ps
T76	/workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.3212707856			May 27 04:23:35 AM PDT 23	May 27 04:27:56 AM PDT 23	2894595438 ps
T133	/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.3021435275			May 27 05:01:45 AM PDT 23	May 27 05:08:01 AM PDT 23	4038178270 ps
T24	/workspace/coverage/default/1.rom_e2e_asm_init_prod.4284709970			May 27 04:36:54 AM PDT 23	May 27 05:10:55 AM PDT 23	9011964402 ps
T132	/workspace/coverage/default/68.chip_sw_all_escalation_resets.4226234254			May 27 04:37:55 AM PDT 23	May 27 04:48:38 AM PDT 23	5710308000 ps
T5	/workspace/coverage/default/4.chip_sw_lc_ctrl_transition.1795698211			May 27 04:36:39 AM PDT 23	May 27 04:45:29 AM PDT 23	6336503526 ps
T135	/workspace/coverage/default/14.chip_sw_uart_rand_baudrate.2233817758			May 27 04:29:42 AM PDT 23	May 27 04:41:32 AM PDT 23	5776226264 ps
T256	/workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.2444385768			May 27 04:26:35 AM PDT 23	May 27 04:29:12 AM PDT 23	2875700190 ps
T348	/workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.1529953103			May 27 04:30:33 AM PDT 23	May 27 04:36:51 AM PDT 23	3635958314 ps
T56	/workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.1588391131			May 27 04:39:37 AM PDT 23	May 27 04:48:42 AM PDT 23	6046246406 ps
T99	/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.595304424			May 27 04:38:42 AM PDT 23	May 27 04:42:21 AM PDT 23	2396005391 ps
T597	/workspace/coverage/default/0.chip_sw_hmac_smoketest.977586194			May 27 04:19:26 AM PDT 23	May 27 04:25:31 AM PDT 23	4028597660 ps
T100	/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.756885997			May 27 04:17:51 AM PDT 23	May 27 04:21:32 AM PDT 23	2257670276 ps
T101	/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.1425575493			May 27 04:30:49 AM PDT 23	May 27 04:35:25 AM PDT 23	2427520729 ps
T147	/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.1061802389			May 27 04:27:43 AM PDT 23	May 27 04:42:41 AM PDT 23	6082848900 ps
T605	/workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.1377046936			May 27 04:33:05 AM PDT 23	May 27 04:39:14 AM PDT 23	4270681376 ps
T25	/workspace/coverage/default/0.rom_e2e_sigverify_mod_exp_rma_otbn.3162445184			May 27 04:22:53 AM PDT 23	May 27 04:52:42 AM PDT 23	8785443240 ps
T69	/workspace/coverage/default/79.chip_sw_all_escalation_resets.1795315752			May 27 05:10:11 AM PDT 23	May 27 05:20:48 AM PDT 23	4302389906 ps
T16	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.3944208892			May 27 04:25:35 AM PDT 23	May 27 05:12:30 AM PDT 23	20773734826 ps
T82	/workspace/coverage/default/1.chip_sw_aes_smoketest.234260171			May 27 04:23:19 AM PDT 23	May 27 04:28:44 AM PDT 23	2470713416 ps
T83	/workspace/coverage/default/80.chip_sw_all_escalation_resets.3769711576			May 27 04:51:25 AM PDT 23	May 27 04:58:50 AM PDT 23	3949158140 ps
T84	/workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.3000858034			May 27 04:17:34 AM PDT 23	May 27 04:27:26 AM PDT 23	5090032940 ps
T85	/workspace/coverage/default/15.chip_sw_uart_rand_baudrate.448690884			May 27 04:30:02 AM PDT 23	May 27 05:27:26 AM PDT 23	23156490436 ps
T26	/workspace/coverage/default/1.chip_sw_sleep_pin_wake.3657146353			May 27 04:20:10 AM PDT 23	May 27 04:23:27 AM PDT 23	2393391144 ps
T6	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.2274499453			May 27 04:21:01 AM PDT 23	May 27 04:51:24 AM PDT 23	8431149432 ps
T86	/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.2708988590			May 27 04:25:39 AM PDT 23	May 27 04:29:46 AM PDT 23	3217581153 ps
T87	/workspace/coverage/default/3.chip_sw_uart_tx_rx.764402506			May 27 04:28:44 AM PDT 23	May 27 04:42:51 AM PDT 23	5963670814 ps
T88	/workspace/coverage/default/2.chip_sw_kmac_entropy.929767430			May 27 04:23:11 AM PDT 23	May 27 04:27:04 AM PDT 23	2741281610 ps
T10	/workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.1163853242			May 27 04:17:49 AM PDT 23	May 27 04:27:01 AM PDT 23	4330083836 ps
T89	/workspace/coverage/default/32.chip_sw_all_escalation_resets.3919258037			May 27 04:32:29 AM PDT 23	May 27 04:43:51 AM PDT 23	4520083430 ps
T90	/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.2120602041			May 27 04:19:13 AM PDT 23	May 27 04:24:12 AM PDT 23	3638737922 ps
T55	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2688861529			May 27 04:18:42 AM PDT 23	May 27 04:28:37 AM PDT 23	4624232790 ps
T11	/workspace/coverage/default/7.chip_padctrl_attributes.61943061			May 27 04:19:10 AM PDT 23	May 27 04:24:22 AM PDT 23	4323080479 ps
T102	/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.1516762476			May 27 04:21:16 AM PDT 23	May 27 04:28:32 AM PDT 23	4310207991 ps
T269	/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.1772876427			May 27 04:29:29 AM PDT 23	May 27 04:37:26 AM PDT 23	4104690480 ps
T636	/workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.2380244232			May 27 04:31:46 AM PDT 23	May 27 04:37:38 AM PDT 23	3682034320 ps
T167	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.1092140748			May 27 04:19:29 AM PDT 23	May 27 04:33:45 AM PDT 23	7947138596 ps
T103	/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.2638686758			May 27 04:26:43 AM PDT 23	May 27 04:35:20 AM PDT 23	5024892223 ps
T828	/workspace/coverage/default/2.rom_e2e_asm_init_rma.2289414575			May 27 04:26:05 AM PDT 23	May 27 04:50:03 AM PDT 23	8664555487 ps
T166	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.3748685733			May 27 04:23:00 AM PDT 23	May 27 08:06:30 AM PDT 23	75401315088 ps
T108	/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1190734498			May 27 04:24:24 AM PDT 23	May 27 05:08:43 AM PDT 23	29471447047 ps
T57	/workspace/coverage/default/3.chip_tap_straps_rma.596689586			May 27 04:31:02 AM PDT 23	May 27 04:36:39 AM PDT 23	4090636832 ps
T13	/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3521341213			May 27 04:15:29 AM PDT 23	May 27 04:27:21 AM PDT 23	5708870767 ps
T111	/workspace/coverage/default/2.chip_sw_otbn_smoketest.2069055117			May 27 04:28:55 AM PDT 23	May 27 04:54:28 AM PDT 23	8118479172 ps
T41	/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.1512246705			May 27 04:19:14 AM PDT 23	May 27 04:24:25 AM PDT 23	4838877619 ps
T591	/workspace/coverage/default/0.rom_e2e_sigverify_mod_exp_prod_end_sw.828224382			May 27 04:19:25 AM PDT 23	May 27 04:52:46 AM PDT 23	8671400366 ps
T42	/workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.2006836375			May 27 04:26:00 AM PDT 23	May 27 04:30:37 AM PDT 23	4024786690 ps
T23	/workspace/coverage/default/0.rom_e2e_shutdown_output.2406394982			May 27 04:18:13 AM PDT 23	May 27 05:02:59 AM PDT 23	23283814184 ps
T206	/workspace/coverage/default/0.chip_sw_aon_timer_irq.434518489			May 27 04:19:04 AM PDT 23	May 27 04:25:36 AM PDT 23	3586576014 ps
T695	/workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.1551709761			May 27 04:50:30 AM PDT 23	May 27 04:56:30 AM PDT 23	4135650386 ps
T109	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1293233698			May 27 04:23:25 AM PDT 23	May 27 04:29:32 AM PDT 23	5259095220 ps
T829	/workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.319906954			May 27 04:26:19 AM PDT 23	May 27 04:29:51 AM PDT 23	2682634208 ps
T148	/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.788504409			May 27 04:27:53 AM PDT 23	May 27 04:43:43 AM PDT 23	5666539944 ps
T124	/workspace/coverage/default/2.chip_sw_sensor_ctrl_status.721201815			May 27 04:47:13 AM PDT 23	May 27 04:50:42 AM PDT 23	3365241154 ps
T112	/workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.4017125052			May 27 04:19:44 AM PDT 23	May 27 04:23:41 AM PDT 23	2712579440 ps
T586	/workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.1679406555			May 27 04:52:20 AM PDT 23	May 27 04:59:08 AM PDT 23	3962730400 ps
T587	/workspace/coverage/default/18.chip_sw_uart_rand_baudrate.4245212585			May 27 04:28:56 AM PDT 23	May 27 04:39:52 AM PDT 23	5377527750 ps
T187	/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.751433254			May 27 04:25:06 AM PDT 23	May 27 04:30:02 AM PDT 23	2528680653 ps
T14	/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.3738161349			May 27 04:45:13 AM PDT 23	May 27 05:01:24 AM PDT 23	5470059272 ps
T276	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.4075199914			May 27 04:23:17 AM PDT 23	May 27 05:14:31 AM PDT 23	12171731738 ps
T218	/workspace/coverage/default/2.chip_sw_aon_timer_irq.1955172239			May 27 04:24:41 AM PDT 23	May 27 04:31:00 AM PDT 23	3147428888 ps
T830	/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.1951544201			May 27 04:35:10 AM PDT 23	May 27 04:59:52 AM PDT 23	8346390072 ps
T596	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.109016991			May 27 04:18:18 AM PDT 23	May 27 04:47:17 AM PDT 23	8308948696 ps
T831	/workspace/coverage/default/2.chip_sw_clkmgr_jitter.936469482			May 27 04:44:23 AM PDT 23	May 27 04:48:01 AM PDT 23	2857193558 ps
T832	/workspace/coverage/default/2.chip_sw_rstmgr_sw_req.2974332312			May 27 04:23:58 AM PDT 23	May 27 04:31:05 AM PDT 23	4240960026 ps
T251	/workspace/coverage/default/0.chip_sw_data_integrity_escalation.2364068697			May 27 04:17:22 AM PDT 23	May 27 04:26:21 AM PDT 23	5131702472 ps
T296	/workspace/coverage/default/2.chip_sw_kmac_mode_kmac.25163741			May 27 04:23:29 AM PDT 23	May 27 04:27:51 AM PDT 23	2996835700 ps
T207	/workspace/coverage/default/1.chip_sw_aon_timer_irq.1426679869			May 27 04:22:12 AM PDT 23	May 27 04:29:58 AM PDT 23	4037728680 ps
T116	/workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.908748890			May 27 04:22:33 AM PDT 23	May 27 04:29:37 AM PDT 23	7789471844 ps
T117	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1224748819			May 27 04:52:38 AM PDT 23	May 27 04:59:35 AM PDT 23	4780069106 ps
T297	/workspace/coverage/default/2.chip_sw_csrng_kat_test.2243367877			May 27 04:23:37 AM PDT 23	May 27 04:27:24 AM PDT 23	2599113048 ps
T298	/workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.1054094358			May 27 04:18:22 AM PDT 23	May 27 04:23:42 AM PDT 23	5102918720 ps
T153	/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.741353912			May 27 04:17:55 AM PDT 23	May 27 04:49:12 AM PDT 23	15945245430 ps
T149	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3357541285			May 27 04:23:10 AM PDT 23	May 27 04:30:07 AM PDT 23	4893906094 ps
T833	/workspace/coverage/default/2.chip_sw_hmac_smoketest.2618943064			May 27 04:27:22 AM PDT 23	May 27 04:32:41 AM PDT 23	2796019744 ps
T592	/workspace/coverage/default/0.rom_e2e_sigverify_mod_exp_prod_end_otbn.71690739			May 27 04:21:52 AM PDT 23	May 27 04:49:47 AM PDT 23	8980154560 ps
T382	/workspace/coverage/default/1.chip_sw_keymgr_key_derivation.1769391835			May 27 04:20:07 AM PDT 23	May 27 04:27:47 AM PDT 23	4680437220 ps
T152	/workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.3386919302			May 27 04:19:03 AM PDT 23	May 27 04:58:32 AM PDT 23	26412375544 ps
T19	/workspace/coverage/default/1.chip_sw_gpio.586565684			May 27 04:24:27 AM PDT 23	May 27 04:32:43 AM PDT 23	3976648232 ps
T260	/workspace/coverage/default/1.chip_sw_rv_timer_irq.857637150			May 27 04:18:57 AM PDT 23	May 27 04:22:26 AM PDT 23	2292425600 ps
T17	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_outputs.4027497016			May 27 04:35:34 AM PDT 23	May 27 04:40:24 AM PDT 23	2784840200 ps
T257	/workspace/coverage/default/99.chip_sw_all_escalation_resets.2051059637			May 27 04:37:14 AM PDT 23	May 27 04:49:58 AM PDT 23	5103851960 ps
T301	/workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.3483280757			May 27 04:25:17 AM PDT 23	May 27 04:32:16 AM PDT 23	4572944600 ps
T302	/workspace/coverage/default/3.chip_sw_all_escalation_resets.1993106458			May 27 04:27:50 AM PDT 23	May 27 04:38:33 AM PDT 23	5384909684 ps
T303	/workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.859644957			May 27 04:28:57 AM PDT 23	May 27 04:35:37 AM PDT 23	3880238236 ps
T304	/workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.2344448803			May 27 04:21:16 AM PDT 23	May 27 04:30:02 AM PDT 23	4643943614 ps
T279	/workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.282696999			May 27 04:19:35 AM PDT 23	May 27 04:28:47 AM PDT 23	9640769365 ps
T305	/workspace/coverage/default/1.chip_sw_entropy_src_kat_test.4293627701			May 27 04:18:46 AM PDT 23	May 27 04:23:05 AM PDT 23	2806417888 ps
T96	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.947520434			May 27 04:20:45 AM PDT 23	May 27 04:32:43 AM PDT 23	4582552768 ps
T306	/workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.198113975			May 27 04:33:05 AM PDT 23	May 27 04:39:03 AM PDT 23	4127389112 ps
T125	/workspace/coverage/default/0.chip_sw_sensor_ctrl_status.3222471315			May 27 04:17:27 AM PDT 23	May 27 04:22:24 AM PDT 23	3621458313 ps
T50	/workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.2516160496			May 27 04:19:10 AM PDT 23	May 27 04:21:55 AM PDT 23	3076439225 ps
T261	/workspace/coverage/default/2.chip_sw_rv_timer_irq.2566896485			May 27 04:23:15 AM PDT 23	May 27 04:27:03 AM PDT 23	2632957288 ps
T834	/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.201026516			May 27 04:23:12 AM PDT 23	May 27 04:40:19 AM PDT 23	6838325338 ps
T381	/workspace/coverage/default/2.chip_sw_flash_crash_alert.3807327202			May 27 04:26:57 AM PDT 23	May 27 04:38:36 AM PDT 23	5074148624 ps
T202	/workspace/coverage/default/1.chip_sw_rv_plic_smoketest.4097251344			May 27 04:22:15 AM PDT 23	May 27 04:26:29 AM PDT 23	3028648600 ps
T15	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.4197974595			May 27 04:55:51 AM PDT 23	May 27 05:19:01 AM PDT 23	18544920822 ps
T249	/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.865533517			May 27 04:43:21 AM PDT 23	May 27 04:55:43 AM PDT 23	5680522364 ps
T344	/workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.4197787521			May 27 04:34:11 AM PDT 23	May 27 04:40:33 AM PDT 23	3882392680 ps
T277	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.2271064712			May 27 04:22:00 AM PDT 23	May 27 05:11:20 AM PDT 23	12392666875 ps
T60	/workspace/coverage/default/4.chip_tap_straps_dev.971943238			May 27 04:31:36 AM PDT 23	May 27 04:57:29 AM PDT 23	17206838037 ps
T346	/workspace/coverage/default/2.chip_sw_entropy_src_smoketest.3092171744			May 27 04:28:14 AM PDT 23	May 27 04:34:34 AM PDT 23	3002679800 ps
T253	/workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.2998076639			May 27 04:26:38 AM PDT 23	May 27 04:36:32 AM PDT 23	7518725622 ps
T191	/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.4222504751			May 27 04:22:07 AM PDT 23	May 27 04:37:07 AM PDT 23	5779273650 ps
T272	/workspace/coverage/default/1.rom_e2e_sigverify_mod_exp_prod_otbn.145440686			May 27 04:34:23 AM PDT 23	May 27 04:59:49 AM PDT 23	8766877632 ps
T273	/workspace/coverage/default/1.rom_e2e_smoke.339760041			May 27 04:33:03 AM PDT 23	May 27 04:57:31 AM PDT 23	8591982144 ps
T274	/workspace/coverage/default/2.chip_sw_aon_timer_smoketest.2890358126			May 27 04:26:23 AM PDT 23	May 27 04:29:41 AM PDT 23	2501914280 ps
T51	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.4141589354			May 27 04:18:32 AM PDT 23	May 27 04:24:31 AM PDT 23	7110408267 ps
T150	/workspace/coverage/default/2.rom_e2e_shutdown_output.2725953339			May 27 04:27:30 AM PDT 23	May 27 05:05:33 AM PDT 23	22486838032 ps
T105	/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.819031324			May 27 04:23:13 AM PDT 23	May 27 04:55:51 AM PDT 23	13851131192 ps
T131	/workspace/coverage/default/2.chip_sw_rv_dm_access_after_wakeup.1046783497			May 27 04:56:04 AM PDT 23	May 27 05:04:17 AM PDT 23	4866262450 ps
T275	/workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.1337458178			May 27 04:43:07 AM PDT 23	May 27 04:51:56 AM PDT 23	4976660984 ps
T835	/workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.1836651177			May 27 04:18:05 AM PDT 23	May 27 04:21:06 AM PDT 23	2039495466 ps
T836	/workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.4133668390			May 27 05:01:07 AM PDT 23	May 27 05:03:58 AM PDT 23	2389922972 ps
T12	/workspace/coverage/default/4.chip_padctrl_attributes.1901088821			May 27 04:28:54 AM PDT 23	May 27 04:34:47 AM PDT 23	5244553904 ps
T618	/workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.1210105803			May 27 04:16:12 AM PDT 23	May 27 04:37:06 AM PDT 23	8505032264 ps
T278	/workspace/coverage/default/1.rom_e2e_shutdown_exception_c.4045814352			May 27 04:34:10 AM PDT 23	May 27 04:59:26 AM PDT 23	8677194322 ps
T97	/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3399846140			May 27 04:26:10 AM PDT 23	May 27 05:19:51 AM PDT 23	28949799454 ps
T837	/workspace/coverage/default/1.chip_sw_clkmgr_smoketest.489051959			May 27 04:20:40 AM PDT 23	May 27 04:23:23 AM PDT 23	2761530990 ps
T838	/workspace/coverage/default/2.rom_e2e_sigverify_mod_exp_rma_otbn.2089523737			May 27 04:27:30 AM PDT 23	May 27 04:57:59 AM PDT 23	8640954108 ps
T839	/workspace/coverage/default/1.rom_e2e_static_critical.2615604299			May 27 04:26:50 AM PDT 23	May 27 05:04:57 AM PDT 23	10593481742 ps
T380	/workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.935289520			May 27 04:27:52 AM PDT 23	May 27 04:42:53 AM PDT 23	7603901541 ps
T840	/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2696457237			May 27 04:17:05 AM PDT 23	May 27 04:25:46 AM PDT 23	3614207320 ps
T841	/workspace/coverage/default/0.rom_e2e_sigverify_mod_exp_dev_sw.983759426			May 27 04:21:55 AM PDT 23	May 27 04:50:11 AM PDT 23	8771878258 ps
T842	/workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.3059552965			May 27 04:34:21 AM PDT 23	May 27 04:43:06 AM PDT 23	4688357344 ps
T215	/workspace/coverage/default/5.chip_sw_all_escalation_resets.2001329392			May 27 04:48:23 AM PDT 23	May 27 04:57:54 AM PDT 23	5800454440 ps
T92	/workspace/coverage/default/2.chip_sw_power_sleep_load.3394274265			May 27 04:27:19 AM PDT 23	May 27 04:32:07 AM PDT 23	4301604540 ps
T162	/workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.980234724			May 27 04:23:20 AM PDT 23	May 27 05:40:40 AM PDT 23	50649204820 ps
T843	/workspace/coverage/default/0.chip_sw_kmac_mode_kmac.2139569930			May 27 04:19:23 AM PDT 23	May 27 04:25:27 AM PDT 23	3307005198 ps
T844	/workspace/coverage/default/0.chip_sw_example_flash.873668045			May 27 04:17:40 AM PDT 23	May 27 04:22:23 AM PDT 23	2765082172 ps
T27	/workspace/coverage/default/0.chip_sw_sleep_pin_retention.1921623131			May 27 04:15:47 AM PDT 23	May 27 04:19:30 AM PDT 23	2729178524 ps
T357	/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1760834558			May 27 04:28:08 AM PDT 23	May 27 04:45:21 AM PDT 23	7543140417 ps
T178	/workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.4059899129			May 27 04:21:38 AM PDT 23	May 27 04:29:55 AM PDT 23	5004124632 ps
T845	/workspace/coverage/default/1.chip_sw_hmac_smoketest.1699959527			May 27 04:22:11 AM PDT 23	May 27 04:28:15 AM PDT 23	3023185400 ps
T846	/workspace/coverage/default/1.chip_sw_kmac_app_rom.1647911110			May 27 04:24:40 AM PDT 23	May 27 04:28:56 AM PDT 23	2740575042 ps
T155	/workspace/coverage/default/1.chip_jtag_csr_rw.2952999039			May 27 04:28:17 AM PDT 23	May 27 04:50:25 AM PDT 23	10256550970 ps
T847	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.2079632495			May 27 04:19:35 AM PDT 23	May 27 04:49:31 AM PDT 23	8011899816 ps
T98	/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.3559089511			May 27 04:29:20 AM PDT 23	May 27 05:19:42 AM PDT 23	21222991847 ps
T734	/workspace/coverage/default/90.chip_sw_all_escalation_resets.1551705669			May 27 04:34:46 AM PDT 23	May 27 04:43:05 AM PDT 23	5241709008 ps
T848	/workspace/coverage/default/0.chip_sw_uart_smoketest_signed.1741267954			May 27 04:20:47 AM PDT 23	May 27 04:49:46 AM PDT 23	9225242920 ps
T849	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.1563106747			May 27 04:18:55 AM PDT 23	May 27 04:28:35 AM PDT 23	3719891510 ps
T171	/workspace/coverage/default/2.chip_sw_flash_init.244405105			May 27 04:20:16 AM PDT 23	May 27 04:54:50 AM PDT 23	20648523352 ps
T252	/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.3799207431			May 27 04:24:35 AM PDT 23	May 27 04:32:42 AM PDT 23	5103050082 ps
T154	/workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.3727513607			May 27 04:22:38 AM PDT 23	May 27 04:35:57 AM PDT 23	7879244324 ps
T268	/workspace/coverage/default/57.chip_sw_all_escalation_resets.1641965234			May 27 04:33:41 AM PDT 23	May 27 04:44:54 AM PDT 23	5417345400 ps
T309	/workspace/coverage/default/2.chip_sw_kmac_mode_cshake.457717638			May 27 04:23:16 AM PDT 23	May 27 04:26:04 AM PDT 23	2382269882 ps