Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo	40.00	0.00					80.00
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo	52.50	25.00					80.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo	65.00	50.00					80.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo	65.00	50.00					80.00
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	748042294	271892	0	0
DepthKnown_A	748042294	747917186	0	0
RvalidKnown_A	748042294	747917186	0	0
WreadyKnown_A	748042294	747917186	0	0
gen_passthru_fifo.paramCheckPass	11626	11626	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	748042294	271892	0	0
T1	468512	132	0	0
T2	1610512	450	0	0
T3	468512	132	0	0
T7	2842448	8748	0	0
T8	1610512	450	0	0
T13	314774	14582	0	0
T14	314774	14582	0	0
T15	314774	14582	0	0
T29	314774	14582	0	0
T30	314774	14582	0	0
T31	314774	14582	0	0
T32	314774	14582	0	0
T33	314774	14582	0	0
T34	314774	14582	0	0
T35	314774	14582	0	0
T42	753700	200	0	0
T43	753700	200	0	0
T45	468512	132	0	0
T55	468512	132	0	0
T56	468512	132	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	748042294	747917186	0	0
T1	702768	702090	0	0
T2	2415768	2415090	0	0
T3	702768	702090	0	0
T7	4263672	4263606	0	0
T8	2415768	2415090	0	0
T13	629548	628892	0	0
T14	629548	628892	0	0
T15	629548	628892	0	0
T22	3633768	3633090	0	0
T29	629548	628892	0	0
T30	629548	628892	0	0
T31	629548	628892	0	0
T32	629548	628892	0	0
T33	629548	628892	0	0
T34	629548	628892	0	0
T35	629548	628892	0	0
T42	1130550	1129236	0	0
T43	1130550	1129236	0	0
T45	702768	702090	0	0
T55	702768	702090	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	748042294	747917186	0	0
T1	702768	702090	0	0
T2	2415768	2415090	0	0
T3	702768	702090	0	0
T7	4263672	4263606	0	0
T8	2415768	2415090	0	0
T13	629548	628892	0	0
T14	629548	628892	0	0
T15	629548	628892	0	0
T22	3633768	3633090	0	0
T29	629548	628892	0	0
T30	629548	628892	0	0
T31	629548	628892	0	0
T32	629548	628892	0	0
T33	629548	628892	0	0
T34	629548	628892	0	0
T35	629548	628892	0	0
T42	1130550	1129236	0	0
T43	1130550	1129236	0	0
T45	702768	702090	0	0
T55	702768	702090	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	748042294	747917186	0	0
T1	702768	702090	0	0
T2	2415768	2415090	0	0
T3	702768	702090	0	0
T7	4263672	4263606	0	0
T8	2415768	2415090	0	0
T13	629548	628892	0	0
T14	629548	628892	0	0
T15	629548	628892	0	0
T22	3633768	3633090	0	0
T29	629548	628892	0	0
T30	629548	628892	0	0
T31	629548	628892	0	0
T32	629548	628892	0	0
T33	629548	628892	0	0
T34	629548	628892	0	0
T35	629548	628892	0	0
T42	1130550	1129236	0	0
T43	1130550	1129236	0	0
T45	702768	702090	0	0
T55	702768	702090	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	11626	11626	0	0
T1	6	6	0	0
T4	6	6	0	0
T5	6	6	0	0
T6	6	6	0	0
T13	4	4	0	0
T14	4	4	0	0
T15	4	4	0	0
T21	6	6	0	0
T29	4	4	0	0
T30	4	4	0	0
T31	4	4	0	0
T32	4	4	0	0
T33	4	4	0	0
T34	4	4	0	0
T35	4	4	0	0
T46	6	6	0	0
T47	6	6	0	0
T49	6	6	0	0
T50	6	6	0	0
T51	6	6	0	0