Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	0.00					80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	0.00					80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
52.50	25.00					80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
52.50	25.00					80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
65.00	50.00					80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
65.00	50.00					80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
65.00	50.00					80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
65.00	50.00					80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	0	0.00
CONT_ASSIGN	44	1	0	0.00
CONT_ASSIGN	45	1	0	0.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	0	1
45	0	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	4	80.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	4	80.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	10255138	0	0	0
DepthKnown_A	10255138	10252820	0	0
RvalidKnown_A	10255138	10252820	0	0
WreadyKnown_A	10255138	10252820	0	0
gen_passthru_fifo.paramCheckPass	16	16	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10255138	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10255138	10252820	0	0
T13	157387	157223	0	0
T14	157387	157223	0	0
T15	157387	157223	0	0
T29	157387	157223	0	0
T30	157387	157223	0	0
T31	157387	157223	0	0
T32	157387	157223	0	0
T33	157387	157223	0	0
T34	157387	157223	0	0
T35	157387	157223	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10255138	10252820	0	0
T13	157387	157223	0	0
T14	157387	157223	0	0
T15	157387	157223	0	0
T29	157387	157223	0	0
T30	157387	157223	0	0
T31	157387	157223	0	0
T32	157387	157223	0	0
T33	157387	157223	0	0
T34	157387	157223	0	0
T35	157387	157223	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10255138	10252820	0	0
T13	157387	157223	0	0
T14	157387	157223	0	0
T15	157387	157223	0	0
T29	157387	157223	0	0
T30	157387	157223	0	0
T31	157387	157223	0	0
T32	157387	157223	0	0
T33	157387	157223	0	0
T34	157387	157223	0	0
T35	157387	157223	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	16	16	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T35	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	1	25.00
CONT_ASSIGN	44	1	0	0.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	0	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	4	80.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	4	80.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	10255138	0	0	0
DepthKnown_A	10255138	10252820	0	0
RvalidKnown_A	10255138	10252820	0	0
WreadyKnown_A	10255138	10252820	0	0
gen_passthru_fifo.paramCheckPass	16	16	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10255138	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10255138	10252820	0	0
T13	157387	157223	0	0
T14	157387	157223	0	0
T15	157387	157223	0	0
T29	157387	157223	0	0
T30	157387	157223	0	0
T31	157387	157223	0	0
T32	157387	157223	0	0
T33	157387	157223	0	0
T34	157387	157223	0	0
T35	157387	157223	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10255138	10252820	0	0
T13	157387	157223	0	0
T14	157387	157223	0	0
T15	157387	157223	0	0
T29	157387	157223	0	0
T30	157387	157223	0	0
T31	157387	157223	0	0
T32	157387	157223	0	0
T33	157387	157223	0	0
T34	157387	157223	0	0
T35	157387	157223	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10255138	10252820	0	0
T13	157387	157223	0	0
T14	157387	157223	0	0
T15	157387	157223	0	0
T29	157387	157223	0	0
T30	157387	157223	0	0
T31	157387	157223	0	0
T32	157387	157223	0	0
T33	157387	157223	0	0
T34	157387	157223	0	0
T35	157387	157223	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	16	16	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T35	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	10255138	32214	0	0
DepthKnown_A	10255138	10252820	0	0
RvalidKnown_A	10255138	10252820	0	0
WreadyKnown_A	10255138	10252820	0	0
gen_passthru_fifo.paramCheckPass	16	16	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10255138	32214	0	0
T13	157387	3198	0	0
T14	157387	3198	0	0
T15	157387	3198	0	0
T29	157387	3198	0	0
T30	157387	3198	0	0
T31	157387	3198	0	0
T32	157387	3198	0	0
T33	157387	3198	0	0
T34	157387	3198	0	0
T35	157387	3198	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10255138	10252820	0	0
T13	157387	157223	0	0
T14	157387	157223	0	0
T15	157387	157223	0	0
T29	157387	157223	0	0
T30	157387	157223	0	0
T31	157387	157223	0	0
T32	157387	157223	0	0
T33	157387	157223	0	0
T34	157387	157223	0	0
T35	157387	157223	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10255138	10252820	0	0
T13	157387	157223	0	0
T14	157387	157223	0	0
T15	157387	157223	0	0
T29	157387	157223	0	0
T30	157387	157223	0	0
T31	157387	157223	0	0
T32	157387	157223	0	0
T33	157387	157223	0	0
T34	157387	157223	0	0
T35	157387	157223	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10255138	10252820	0	0
T13	157387	157223	0	0
T14	157387	157223	0	0
T15	157387	157223	0	0
T29	157387	157223	0	0
T30	157387	157223	0	0
T31	157387	157223	0	0
T32	157387	157223	0	0
T33	157387	157223	0	0
T34	157387	157223	0	0
T35	157387	157223	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	16	16	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T35	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	10255138	114986	0	0
DepthKnown_A	10255138	10252820	0	0
RvalidKnown_A	10255138	10252820	0	0
WreadyKnown_A	10255138	10252820	0	0
gen_passthru_fifo.paramCheckPass	16	16	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10255138	114986	0	0
T13	157387	11384	0	0
T14	157387	11384	0	0
T15	157387	11384	0	0
T29	157387	11384	0	0
T30	157387	11384	0	0
T31	157387	11384	0	0
T32	157387	11384	0	0
T33	157387	11384	0	0
T34	157387	11384	0	0
T35	157387	11384	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10255138	10252820	0	0
T13	157387	157223	0	0
T14	157387	157223	0	0
T15	157387	157223	0	0
T29	157387	157223	0	0
T30	157387	157223	0	0
T31	157387	157223	0	0
T32	157387	157223	0	0
T33	157387	157223	0	0
T34	157387	157223	0	0
T35	157387	157223	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10255138	10252820	0	0
T13	157387	157223	0	0
T14	157387	157223	0	0
T15	157387	157223	0	0
T29	157387	157223	0	0
T30	157387	157223	0	0
T31	157387	157223	0	0
T32	157387	157223	0	0
T33	157387	157223	0	0
T34	157387	157223	0	0
T35	157387	157223	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10255138	10252820	0	0
T13	157387	157223	0	0
T14	157387	157223	0	0
T15	157387	157223	0	0
T29	157387	157223	0	0
T30	157387	157223	0	0
T31	157387	157223	0	0
T32	157387	157223	0	0
T33	157387	157223	0	0
T34	157387	157223	0	0
T35	157387	157223	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	16	16	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T35	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	117836957	28433	0	0
DepthKnown_A	117836957	117817651	0	0
RvalidKnown_A	117836957	117817651	0	0
WreadyKnown_A	117836957	117817651	0	0
gen_passthru_fifo.paramCheckPass	1927	1927	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117836957	28433	0	0
T1	117128	33	0	0
T2	402628	104	0	0
T3	117128	33	0	0
T7	710612	2187	0	0
T8	402628	104	0	0
T42	188425	50	0	0
T43	188425	50	0	0
T45	117128	33	0	0
T55	117128	33	0	0
T56	117128	33	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117836957	117817651	0	0
T1	117128	117015	0	0
T2	402628	402515	0	0
T3	117128	117015	0	0
T7	710612	710601	0	0
T8	402628	402515	0	0
T22	605628	605515	0	0
T42	188425	188206	0	0
T43	188425	188206	0	0
T45	117128	117015	0	0
T55	117128	117015	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117836957	117817651	0	0
T1	117128	117015	0	0
T2	402628	402515	0	0
T3	117128	117015	0	0
T7	710612	710601	0	0
T8	402628	402515	0	0
T22	605628	605515	0	0
T42	188425	188206	0	0
T43	188425	188206	0	0
T45	117128	117015	0	0
T55	117128	117015	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117836957	117817651	0	0
T1	117128	117015	0	0
T2	402628	402515	0	0
T3	117128	117015	0	0
T7	710612	710601	0	0
T8	402628	402515	0	0
T22	605628	605515	0	0
T42	188425	188206	0	0
T43	188425	188206	0	0
T45	117128	117015	0	0
T55	117128	117015	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1927	1927	0	0
T1	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T21	1	1	0	0
T46	1	1	0	0
T47	1	1	0	0
T49	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	117836957	33913	0	0
DepthKnown_A	117836957	117817651	0	0
RvalidKnown_A	117836957	117817651	0	0
WreadyKnown_A	117836957	117817651	0	0
gen_passthru_fifo.paramCheckPass	1927	1927	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117836957	33913	0	0
T1	117128	33	0	0
T2	402628	121	0	0
T3	117128	33	0	0
T7	710612	2187	0	0
T8	402628	121	0	0
T42	188425	50	0	0
T43	188425	50	0	0
T45	117128	33	0	0
T55	117128	33	0	0
T56	117128	33	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117836957	117817651	0	0
T1	117128	117015	0	0
T2	402628	402515	0	0
T3	117128	117015	0	0
T7	710612	710601	0	0
T8	402628	402515	0	0
T22	605628	605515	0	0
T42	188425	188206	0	0
T43	188425	188206	0	0
T45	117128	117015	0	0
T55	117128	117015	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117836957	117817651	0	0
T1	117128	117015	0	0
T2	402628	402515	0	0
T3	117128	117015	0	0
T7	710612	710601	0	0
T8	402628	402515	0	0
T22	605628	605515	0	0
T42	188425	188206	0	0
T43	188425	188206	0	0
T45	117128	117015	0	0
T55	117128	117015	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117836957	117817651	0	0
T1	117128	117015	0	0
T2	402628	402515	0	0
T3	117128	117015	0	0
T7	710612	710601	0	0
T8	402628	402515	0	0
T22	605628	605515	0	0
T42	188425	188206	0	0
T43	188425	188206	0	0
T45	117128	117015	0	0
T55	117128	117015	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1927	1927	0	0
T1	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T21	1	1	0	0
T46	1	1	0	0
T47	1	1	0	0
T49	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	4	80.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	4	80.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	117836957	0	0	0
DepthKnown_A	117836957	117817651	0	0
RvalidKnown_A	117836957	117817651	0	0
WreadyKnown_A	117836957	117817651	0	0
gen_passthru_fifo.paramCheckPass	1927	1927	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117836957	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117836957	117817651	0	0
T1	117128	117015	0	0
T2	402628	402515	0	0
T3	117128	117015	0	0
T7	710612	710601	0	0
T8	402628	402515	0	0
T22	605628	605515	0	0
T42	188425	188206	0	0
T43	188425	188206	0	0
T45	117128	117015	0	0
T55	117128	117015	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117836957	117817651	0	0
T1	117128	117015	0	0
T2	402628	402515	0	0
T3	117128	117015	0	0
T7	710612	710601	0	0
T8	402628	402515	0	0
T22	605628	605515	0	0
T42	188425	188206	0	0
T43	188425	188206	0	0
T45	117128	117015	0	0
T55	117128	117015	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117836957	117817651	0	0
T1	117128	117015	0	0
T2	402628	402515	0	0
T3	117128	117015	0	0
T7	710612	710601	0	0
T8	402628	402515	0	0
T22	605628	605515	0	0
T42	188425	188206	0	0
T43	188425	188206	0	0
T45	117128	117015	0	0
T55	117128	117015	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1927	1927	0	0
T1	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T21	1	1	0	0
T46	1	1	0	0
T47	1	1	0	0
T49	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	0	0.00
CONT_ASSIGN	45	1	0	0.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	0	1
45	0	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	4	80.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	4	80.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	117836957	0	0	0
DepthKnown_A	117836957	117817651	0	0
RvalidKnown_A	117836957	117817651	0	0
WreadyKnown_A	117836957	117817651	0	0
gen_passthru_fifo.paramCheckPass	1927	1927	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117836957	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117836957	117817651	0	0
T1	117128	117015	0	0
T2	402628	402515	0	0
T3	117128	117015	0	0
T7	710612	710601	0	0
T8	402628	402515	0	0
T22	605628	605515	0	0
T42	188425	188206	0	0
T43	188425	188206	0	0
T45	117128	117015	0	0
T55	117128	117015	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117836957	117817651	0	0
T1	117128	117015	0	0
T2	402628	402515	0	0
T3	117128	117015	0	0
T7	710612	710601	0	0
T8	402628	402515	0	0
T22	605628	605515	0	0
T42	188425	188206	0	0
T43	188425	188206	0	0
T45	117128	117015	0	0
T55	117128	117015	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117836957	117817651	0	0
T1	117128	117015	0	0
T2	402628	402515	0	0
T3	117128	117015	0	0
T7	710612	710601	0	0
T8	402628	402515	0	0
T22	605628	605515	0	0
T42	188425	188206	0	0
T43	188425	188206	0	0
T45	117128	117015	0	0
T55	117128	117015	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1927	1927	0	0
T1	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T21	1	1	0	0
T46	1	1	0	0
T47	1	1	0	0
T49	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	117836957	28433	0	0
DepthKnown_A	117836957	117817651	0	0
RvalidKnown_A	117836957	117817651	0	0
WreadyKnown_A	117836957	117817651	0	0
gen_passthru_fifo.paramCheckPass	1927	1927	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117836957	28433	0	0
T1	117128	33	0	0
T2	402628	104	0	0
T3	117128	33	0	0
T7	710612	2187	0	0
T8	402628	104	0	0
T42	188425	50	0	0
T43	188425	50	0	0
T45	117128	33	0	0
T55	117128	33	0	0
T56	117128	33	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117836957	117817651	0	0
T1	117128	117015	0	0
T2	402628	402515	0	0
T3	117128	117015	0	0
T7	710612	710601	0	0
T8	402628	402515	0	0
T22	605628	605515	0	0
T42	188425	188206	0	0
T43	188425	188206	0	0
T45	117128	117015	0	0
T55	117128	117015	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117836957	117817651	0	0
T1	117128	117015	0	0
T2	402628	402515	0	0
T3	117128	117015	0	0
T7	710612	710601	0	0
T8	402628	402515	0	0
T22	605628	605515	0	0
T42	188425	188206	0	0
T43	188425	188206	0	0
T45	117128	117015	0	0
T55	117128	117015	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117836957	117817651	0	0
T1	117128	117015	0	0
T2	402628	402515	0	0
T3	117128	117015	0	0
T7	710612	710601	0	0
T8	402628	402515	0	0
T22	605628	605515	0	0
T42	188425	188206	0	0
T43	188425	188206	0	0
T45	117128	117015	0	0
T55	117128	117015	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1927	1927	0	0
T1	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T21	1	1	0	0
T46	1	1	0	0
T47	1	1	0	0
T49	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	117836957	33913	0	0
DepthKnown_A	117836957	117817651	0	0
RvalidKnown_A	117836957	117817651	0	0
WreadyKnown_A	117836957	117817651	0	0
gen_passthru_fifo.paramCheckPass	1927	1927	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117836957	33913	0	0
T1	117128	33	0	0
T2	402628	121	0	0
T3	117128	33	0	0
T7	710612	2187	0	0
T8	402628	121	0	0
T42	188425	50	0	0
T43	188425	50	0	0
T45	117128	33	0	0
T55	117128	33	0	0
T56	117128	33	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117836957	117817651	0	0
T1	117128	117015	0	0
T2	402628	402515	0	0
T3	117128	117015	0	0
T7	710612	710601	0	0
T8	402628	402515	0	0
T22	605628	605515	0	0
T42	188425	188206	0	0
T43	188425	188206	0	0
T45	117128	117015	0	0
T55	117128	117015	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117836957	117817651	0	0
T1	117128	117015	0	0
T2	402628	402515	0	0
T3	117128	117015	0	0
T7	710612	710601	0	0
T8	402628	402515	0	0
T22	605628	605515	0	0
T42	188425	188206	0	0
T43	188425	188206	0	0
T45	117128	117015	0	0
T55	117128	117015	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117836957	117817651	0	0
T1	117128	117015	0	0
T2	402628	402515	0	0
T3	117128	117015	0	0
T7	710612	710601	0	0
T8	402628	402515	0	0
T22	605628	605515	0	0
T42	188425	188206	0	0
T43	188425	188206	0	0
T45	117128	117015	0	0
T55	117128	117015	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1927	1927	0	0
T1	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T21	1	1	0	0
T46	1	1	0	0
T47	1	1	0	0
T49	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0