Unified Coverage Report :: Module :: prim_lc_sender

Module : prim_lc_sender

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sender_0.1/rtl/prim_lc_sender.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_lc_sender	0.00	0.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sender_pinmux_hw_debug_en	100.00	100.00

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_lc_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	60.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
57.89	58.82	46.43	61.85		75.00	47.37	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sender_pinmux_hw_debug_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.93	96.37	100.00			93.22	94.12	u_pinmux_strap_sampling

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

Line Coverage for Module : prim_lc_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	66	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sender_0.1/rtl/prim_lc_sender.sv' or '../src/lowrisc_prim_lc_sender_0.1/rtl/prim_lc_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
32	1	1
66	1	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_lc_sender

	Line No.	Total	Covered	Percent
TOTAL		2	0	0.00
CONT_ASSIGN	32	1	0	0.00
CONT_ASSIGN	66	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sender_0.1/rtl/prim_lc_sender.sv' or '../src/lowrisc_prim_lc_sender_0.1/rtl/prim_lc_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
32	0	1
66	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sender_pinmux_hw_debug_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	66	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sender_0.1/rtl/prim_lc_sender.sv' or '../src/lowrisc_prim_lc_sender_0.1/rtl/prim_lc_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
32	1	1
66	1	1