Unified Coverage Report :: Module :: rv_core_ibex

Module : rv_core_ibex

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
57.74	58.82	46.43	61.08		75.00	47.37

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex	57.89	58.82	46.43	61.85		75.00	47.37

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
57.89	58.82	46.43	61.85		75.00	47.37

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
73.17	83.03	84.69	48.49		89.07	60.58

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.70	68.10		83.00			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
fifo_d	100.00	100.00	100.00			100.00	100.00
fifo_i	73.12	12.50	100.00			100.00	80.00
gen_alert_senders[0].u_alert_sender	58.33			58.33
gen_alert_senders[1].u_alert_sender	75.00			75.00
gen_alert_senders[2].u_alert_sender	58.33			58.33
gen_alert_senders[3].u_alert_sender	33.33			33.33
tl_adapter_host_d_ibex	62.24	81.40	40.91			60.00	66.67
tl_adapter_host_i_ibex	47.42	28.57	38.89			55.56	66.67
u_alert_nmi_sync	100.00	100.00				100.00
u_core	21.20			21.20
u_core_sleeping_buf	100.00	100.00
u_dbus_trans	70.43	93.10	81.48			100.00	7.14
u_edn_if	48.85	75.32	50.85			69.23	0.00
u_ibus_trans	44.39	90.80	29.63			50.00	7.14
u_intr_timer_sync	100.00	100.00				100.00
u_lc_sync	100.00	100.00				100.00	100.00
u_prim_buf_irq	0.00	0.00
u_prim_esc_receiver	28.57			28.57
u_prim_lc_sender	80.00	60.00				100.00
u_prim_sync_reqack_data	26.22	44.90	0.00			60.00	0.00
u_pwrmgr_sync	100.00	100.00				100.00	100.00
u_reg_cfg	96.55	95.90	96.09			98.74	95.45
u_sim_win_rsp	55.63	30.61	36.36			55.56	100.00
u_tlul_req_buf	100.00	100.00
u_tlul_rsp_buf	0.00	0.00
u_wdog_nmi_sync	100.00	100.00				100.00

Line Coverage for Module : rv_core_ibex

	Line No.	Total	Covered	Percent
TOTAL		85	50	58.82
CONT_ASSIGN	202	1	1	100.00
CONT_ASSIGN	203	1	1	100.00
CONT_ASSIGN	216	1	1	100.00
CONT_ASSIGN	217	1	0	0.00
CONT_ASSIGN	218	1	0	0.00
CONT_ASSIGN	225	1	1	100.00
CONT_ASSIGN	263	1	0	0.00
CONT_ASSIGN	265	1	0	0.00
CONT_ASSIGN	268	1	0	0.00
CONT_ASSIGN	342	1	0	0.00
CONT_ASSIGN	348	1	0	0.00
CONT_ASSIGN	363	1	1	100.00
ALWAYS	488	3	3	100.00
CONT_ASSIGN	508	1	0	0.00
CONT_ASSIGN	509	1	0	0.00
CONT_ASSIGN	510	1	0	0.00
CONT_ASSIGN	511	1	0	0.00
ALWAYS	514	8	5	62.50
CONT_ASSIGN	699	1	0	0.00
CONT_ASSIGN	699	1	0	0.00
CONT_ASSIGN	700	1	1	100.00
CONT_ASSIGN	700	1	1	100.00
CONT_ASSIGN	701	1	1	100.00
CONT_ASSIGN	701	1	1	100.00
CONT_ASSIGN	705	1	1	100.00
CONT_ASSIGN	705	1	1	100.00
CONT_ASSIGN	706	1	1	100.00
CONT_ASSIGN	706	1	1	100.00
CONT_ASSIGN	707	1	1	100.00
CONT_ASSIGN	707	1	1	100.00
CONT_ASSIGN	714	1	1	100.00
CONT_ASSIGN	715	1	0	0.00
CONT_ASSIGN	716	1	0	0.00
CONT_ASSIGN	719	1	1	100.00
CONT_ASSIGN	721	1	1	100.00
CONT_ASSIGN	723	1	0	0.00
CONT_ASSIGN	725	1	0	0.00
CONT_ASSIGN	732	1	1	100.00
CONT_ASSIGN	734	1	1	100.00
CONT_ASSIGN	736	1	1	100.00
CONT_ASSIGN	738	1	1	100.00
CONT_ASSIGN	748	1	0	0.00
CONT_ASSIGN	749	1	1	100.00
CONT_ASSIGN	750	1	1	100.00
CONT_ASSIGN	751	1	0	0.00
CONT_ASSIGN	754	1	1	100.00
CONT_ASSIGN	757	1	1	100.00
ALWAYS	789	11	8	72.73
ALWAYS	805	7	7	100.00
CONT_ASSIGN	816	1	0	0.00
CONT_ASSIGN	835	1	0	0.00
CONT_ASSIGN	836	1	0	0.00
CONT_ASSIGN	837	1	0	0.00
CONT_ASSIGN	840	1	0	0.00
CONT_ASSIGN	844	0	0
CONT_ASSIGN	883	1	0	0.00
ALWAYS	936	0	0
CONT_ASSIGN	977	1	0	0.00
CONT_ASSIGN	979	1	0	0.00
CONT_ASSIGN	981	1	1	100.00
CONT_ASSIGN	983	1	0	0.00
CONT_ASSIGN	985	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
202	1	1
203	1	1
216	1	1
217	0	1
218	0	1
225	1	1
263	0	1
265	0	1
268	0	1
342	0	1
348	0	1
363	1	1
488	1	1
489	1	1
491	1	1
508	0	1
509	0	1
510	0	1
511	0	1
514	1	1
515	1	1
516	1	1
517	1	1
518	1	1
519	0	1
520	0	1
521	0	1
			MISSING_ELSE
699	0	2
700	2	2
701	2	2
705	2	2
706	2	2
707	2	2
714	1	1
715	0	1
716	0	1
719	1	1
721	1	1
723	0	1
725	0	1
732	1	1
734	1	1
736	1	1
738	1	1
748	0	1
749	1	1
750	1	1
751	0	1
754	1	1
757	1	1
789	1	1
790	1	1
791	1	1
793	1	1
794	1	1
795	1	1
796	1	1
797	1	1
798	0	1
799	0	1
800	0	1
			MISSING_ELSE
805	1	1
806	1	1
807	1	1
808	1	1
810	1	1
811	1	1
812	1	1
816	0	1
835	0	1
836	0	1
837	0	1
840	0	1
844		unreachable
883	0	1
936		unreachable
937		unreachable
938		unreachable
939		unreachable
			==> MISSING_ELSE
977	0	1
979	0	1
981	1	1
983	0	1
985	0	1

---

Cond Coverage for Module : rv_core_ibex

	Total	Covered	Percent
Conditions	28	13	46.43
Logical	28	13	46.43
Non-Logical	0	0
Event	0	0

 LINE       216
 EXPRESSION (ibus_intg_err | dbus_intg_err | alert_major_bus)
             ------1------   ------2------   -------3-------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T13,T14,T15
0	0	1	Not Covered
0	1	0	Not Covered
1	0	0	Not Covered

 LINE       217
 EXPRESSION (alert_major_internal | double_fault)
             ----------1---------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T15
0	1	Not Covered
1	0	Not Covered

 LINE       348
 EXPRESSION (fatal_core_err ? Off : local_fetch_enable_q)
             -------1------

-1-	Status	Tests
0	Covered	T13,T14,T15
1	Not Covered

 LINE       732
 EXPRESSION (reg2hw.alert_test.fatal_sw_err.q & reg2hw.alert_test.fatal_sw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T19,T20,T36
1	1	Covered	T19,T20,T36

 LINE       734
 EXPRESSION (reg2hw.alert_test.recov_sw_err.q & reg2hw.alert_test.recov_sw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T19,T20,T36
1	0	Covered	T19,T20,T36
1	1	Not Covered

 LINE       736
 EXPRESSION (reg2hw.alert_test.fatal_hw_err.q & reg2hw.alert_test.fatal_hw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T19,T20,T36
1	1	Covered	T19,T20,T36

 LINE       738
 EXPRESSION (reg2hw.alert_test.recov_hw_err.q & reg2hw.alert_test.recov_hw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T19,T20,T36
1	0	Covered	T19,T20,T36
1	1	Not Covered

 LINE       750
 EXPRESSION (intg_err | fatal_intg_err | fatal_core_err)
             ----1---   -------2------   -------3------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T13,T14,T15
0	0	1	Not Covered
0	1	0	Not Covered
1	0	0	Not Covered

 LINE       797
 EXPRESSION (edn_req && edn_ack)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T19,T20,T36
1	1	Not Covered

---

Toggle Coverage for Module : rv_core_ibex

	Total	Covered	Percent
Totals	121	96	79.34
Total Bits	1624	992	61.08
Total Bits 0->1	812	496	61.08
Total Bits 1->0	812	496	61.08

Ports	121	96	79.34
Port Bits	1624	992	61.08
Port Bits 0->1	812	496	61.08
Port Bits 1->0	812	496	61.08

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_edn_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_edn_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_esc_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_esc_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_cpu_n_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ram_cfg_i.rf_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.rf_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg_en	No	No		No		INPUT
hart_id_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
boot_addr_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
corei_tl_h_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
corei_tl_h_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
corei_tl_h_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
corei_tl_h_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
corei_tl_h_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
corei_tl_h_o.a_address[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
corei_tl_h_o.a_source[5:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
corei_tl_h_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_size[1:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
corei_tl_h_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_opcode[2:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
corei_tl_h_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
corei_tl_h_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
corei_tl_h_i.d_error	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
corei_tl_h_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
corei_tl_h_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
corei_tl_h_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
corei_tl_h_i.d_sink	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
corei_tl_h_i.d_source[5:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
corei_tl_h_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_size[1:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
corei_tl_h_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
corei_tl_h_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cored_tl_h_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
cored_tl_h_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
cored_tl_h_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
cored_tl_h_o.a_user.instr_type[3:0]	Yes	Yes	T46,T1,T47	Yes	T46,T1,T47	OUTPUT
cored_tl_h_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
cored_tl_h_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
cored_tl_h_o.a_address[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
cored_tl_h_o.a_source[5:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
cored_tl_h_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_size[1:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
cored_tl_h_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_opcode[2:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
cored_tl_h_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
cored_tl_h_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cored_tl_h_i.d_error	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cored_tl_h_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cored_tl_h_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cored_tl_h_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cored_tl_h_i.d_sink	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cored_tl_h_i.d_source[5:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cored_tl_h_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_size[1:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cored_tl_h_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
cored_tl_h_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
irq_software_i	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	INPUT
irq_timer_i	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	INPUT
irq_external_i	Yes	Yes	T2,T8,T9	Yes	T2,T8,T9	INPUT
esc_tx_i.esc_n	No	No		No		INPUT
esc_tx_i.esc_p	No	No		No		INPUT
esc_rx_o.resp_n	No	No		No		OUTPUT
esc_rx_o.resp_p	No	No		No		OUTPUT
nmi_wdog_i	Yes	Yes	T2,T8,T9	Yes	T2,T8,T9	INPUT
debug_req_i	No	No		No		INPUT
crash_dump_o.current.exception_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.exception_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.last_data_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.next_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.current_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_exception_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_exception_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_valid	Unreachable	Unreachable		Unreachable		OUTPUT
lc_cpu_en_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
pwrmgr_cpu_en_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
pwrmgr_o.core_sleeping	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
scan_rst_ni	Unreachable	Unreachable		Unreachable		INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.d_ready	Yes	Yes	T4,T5,T21	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T21	Yes	T4,T5,T21	INPUT
cfg_tl_d_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T21	Yes	T4,T5,T21	INPUT
cfg_tl_d_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T21	Yes	T4,T5,T21	INPUT
cfg_tl_d_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_data[31:0]	Yes	Yes	T4,T5,T21	Yes	T4,T5,T21	INPUT
cfg_tl_d_i.a_mask[3:0]	Yes	Yes	T4,T5,T21	Yes	T4,T5,T21	INPUT
cfg_tl_d_i.a_address[7:0]	Yes	Yes	T4,T5,T21	Yes	T4,T5,T21	INPUT
cfg_tl_d_i.a_address[15:8]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[20:16]	Yes	Yes	T4,T5,T21	Yes	T4,T5,T21	INPUT
cfg_tl_d_i.a_address[23:21]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[24]	Yes	Yes	*T4,*T5,*T21	Yes	T4,T5,T21	INPUT
cfg_tl_d_i.a_address[29:25]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[30]	Yes	Yes	*T4,*T5,*T21	Yes	T4,T5,T21	INPUT
cfg_tl_d_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_source[5:0]	Yes	Yes	T4,T5,T21	Yes	T4,T5,T21	INPUT
cfg_tl_d_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_size[1:0]	Yes	Yes	T4,T5,T21	Yes	T4,T5,T21	INPUT
cfg_tl_d_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_opcode[2:0]	Yes	Yes	T4,T5,T21	Yes	T4,T5,T21	INPUT
cfg_tl_d_i.a_valid	Yes	Yes	T4,T5,T21	Yes	T4,T5,T21	INPUT
cfg_tl_d_o.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
cfg_tl_d_o.d_error	Yes	Yes	T4,T5,T21	Yes	T4,T5,T21	OUTPUT
cfg_tl_d_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T21	Yes	T4,T5,T21	OUTPUT
cfg_tl_d_o.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T21	Yes	T4,T5,T21	OUTPUT
cfg_tl_d_o.d_data[31:0]	Yes	Yes	T4,T5,T21	Yes	T4,T5,T21	OUTPUT
cfg_tl_d_o.d_sink	Yes	Yes	T4,T5,T21	Yes	T4,T5,T21	OUTPUT
cfg_tl_d_o.d_source[5:0]	Yes	Yes	T4,T5,T21	Yes	T4,T5,T21	OUTPUT
cfg_tl_d_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_size[1:0]	Yes	Yes	T4,T5,T21	Yes	T4,T5,T21	OUTPUT
cfg_tl_d_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T21	Yes	T4,T5,T21	OUTPUT
cfg_tl_d_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_valid	Yes	Yes	T4,T5,T21	Yes	T4,T5,T21	OUTPUT
edn_o.edn_req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i.edn_bus[31:0]	No	No		No		INPUT
edn_i.edn_fips	No	No		No		INPUT
edn_i.edn_ack	No	No		No		INPUT
clk_otp_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_otp_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
icache_otp_key_o.req	No	No		No		OUTPUT
icache_otp_key_i.seed_valid	No	No		No		INPUT
icache_otp_key_i.nonce[127:0]	No	No		No		INPUT
icache_otp_key_i.key[127:0]	No	No		No		INPUT
icache_otp_key_i.ack	No	No		No		INPUT
fpga_info_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	INPUT
alert_rx_i[0].ping_n	No	No		No		INPUT
alert_rx_i[0].ping_p	No	No		No		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	INPUT
alert_rx_i[1].ping_n	No	No		No		INPUT
alert_rx_i[1].ping_p	No	No		No		INPUT
alert_rx_i[2].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[2].ack_p	Yes	Yes	T2,T8,T9	Yes	T2,T8,T9	INPUT
alert_rx_i[2].ping_n	No	No		No		INPUT
alert_rx_i[2].ping_p	No	No		No		INPUT
alert_rx_i[3].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[3].ack_p	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	INPUT
alert_rx_i[3].ping_n	No	No		No		INPUT
alert_rx_i[3].ping_p	No	No		No		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	OUTPUT
alert_tx_o[2].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[2].alert_p	Yes	Yes	T2,T8,T9	Yes	T2,T8,T9	OUTPUT
alert_tx_o[3].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[3].alert_p	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : rv_core_ibex

	Line No.	Total	Covered	Percent
Branches		12	9	75.00
TERNARY	348	2	1	50.00
IF	488	2	2	100.00
IF	514	3	2	66.67
IF	793	3	2	66.67
IF	805	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	348	(fatal_core_err) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	488	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T15
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	514	if ((!rst_ni))
-2-:	518	if (double_fault)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T13,T14,T15
0	1	Not Covered
0	0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	793	if (reg2hw.rnd_data.re)
-2-:	797	if ((edn_req && edn_ack))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T19,T20,T36
0	1	Not Covered
0	0	Covered	T19,T20,T36

	LineNo.	Expression
-1-:	805	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T15
0	Covered	T13,T14,T15

---

Assert Coverage for Module : rv_core_ibex

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	9	47.37
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	9	47.37

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
FpvSecCmIbexFetchEnable0_A	10255138	0	0	0
FpvSecCmIbexFetchEnable1_A	10255138	253278	0	32
FpvSecCmIbexFetchEnable2_A	10255138	908038	0	32
FpvSecCmIbexFetchEnable3Rev_A	10255138	9344672	0	32
FpvSecCmIbexFetchEnable3_A	10255138	9344698	0	0
FpvSecCmIbexInstrIntgErrCheck_A	10255138	0	0	0
FpvSecCmIbexLoadRespIntgErrCheck_A	10255138	0	0	0
FpvSecCmIbexPcMismatchCheck_A	10255138	0	0	0
FpvSecCmIbexRfEccErrCheck_A	10255138	0	0	0
FpvSecCmIbexStoreRespIntgErrCheck_A	10255138	0	0	0
FpvSecCmRegWeOnehotCheck_A	10255138	0	0	0
FpvSecCmRvCoreRegWeOnehotCheck_A	10255138	0	0	0
g_instr_intg_err_assert_signals.AssertConnected_A	16	16	0	0
g_lsu_load_resp_intg_err_assert_signals.AssertConnected_A	16	16	0	0
g_lsu_store_resp_intg_err_assert_signals.AssertConnected_A	16	16	0	0
g_pc_mismatch_alert_o_assert_signals.AssertConnected_A	16	16	0	0
g_rf_ecc_err_comb_assert_signals.AssertConnected_A	16	16	0	0
gen_icache_scramble_asserts.IbexIcacheScrambleKeyForwardedToCore_A	10255138	0	0	0
gen_icache_scramble_asserts.IbexIcacheScrambleKeyRequestAfterFenceI_A	10255138	0	0	0

FpvSecCmIbexFetchEnable0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10255138	0	0	0

FpvSecCmIbexFetchEnable1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10255138	253278	0	32
T13	157387	19425	0	2
T14	157387	19425	0	2
T15	157387	19425	0	2
T29	157387	19425	0	2
T30	157387	19425	0	2
T31	157387	19425	0	2
T32	157387	19425	0	2
T33	157387	19425	0	2
T34	157387	19425	0	2
T35	157387	19425	0	2

FpvSecCmIbexFetchEnable2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10255138	908038	0	32
T13	157387	69793	0	2
T14	157387	69793	0	2
T15	157387	69793	0	2
T29	157387	69793	0	2
T30	157387	69793	0	2
T31	157387	69793	0	2
T32	157387	69793	0	2
T33	157387	69793	0	2
T34	157387	69793	0	2
T35	157387	69793	0	2

FpvSecCmIbexFetchEnable3Rev_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10255138	9344672	0	32
T13	157387	87422	0	2
T14	157387	87422	0	2
T15	157387	87422	0	2
T29	157387	87422	0	2
T30	157387	87422	0	2
T31	157387	87422	0	2
T32	157387	87422	0	2
T33	157387	87422	0	2
T34	157387	87422	0	2
T35	157387	87422	0	2

FpvSecCmIbexFetchEnable3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10255138	9344698	0	0
T13	157387	87424	0	0
T14	157387	87424	0	0
T15	157387	87424	0	0
T29	157387	87424	0	0
T30	157387	87424	0	0
T31	157387	87424	0	0
T32	157387	87424	0	0
T33	157387	87424	0	0
T34	157387	87424	0	0
T35	157387	87424	0	0

FpvSecCmIbexInstrIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10255138	0	0	0

FpvSecCmIbexLoadRespIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10255138	0	0	0

FpvSecCmIbexPcMismatchCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10255138	0	0	0

FpvSecCmIbexRfEccErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10255138	0	0	0

FpvSecCmIbexStoreRespIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10255138	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10255138	0	0	0

FpvSecCmRvCoreRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10255138	0	0	0

g_instr_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16	16	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T35	1	1	0	0

g_lsu_load_resp_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16	16	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T35	1	1	0	0

g_lsu_store_resp_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16	16	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T35	1	1	0	0

g_pc_mismatch_alert_o_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16	16	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T35	1	1	0	0

g_rf_ecc_err_comb_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16	16	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T35	1	1	0	0

gen_icache_scramble_asserts.IbexIcacheScrambleKeyForwardedToCore_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10255138	0	0	0

gen_icache_scramble_asserts.IbexIcacheScrambleKeyRequestAfterFenceI_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10255138	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex

	Line No.	Total	Covered	Percent
TOTAL		85	50	58.82
CONT_ASSIGN	202	1	1	100.00
CONT_ASSIGN	203	1	1	100.00
CONT_ASSIGN	216	1	1	100.00
CONT_ASSIGN	217	1	0	0.00
CONT_ASSIGN	218	1	0	0.00
CONT_ASSIGN	225	1	1	100.00
CONT_ASSIGN	263	1	0	0.00
CONT_ASSIGN	265	1	0	0.00
CONT_ASSIGN	268	1	0	0.00
CONT_ASSIGN	342	1	0	0.00
CONT_ASSIGN	348	1	0	0.00
CONT_ASSIGN	363	1	1	100.00
ALWAYS	488	3	3	100.00
CONT_ASSIGN	508	1	0	0.00
CONT_ASSIGN	509	1	0	0.00
CONT_ASSIGN	510	1	0	0.00
CONT_ASSIGN	511	1	0	0.00
ALWAYS	514	8	5	62.50
CONT_ASSIGN	699	1	0	0.00
CONT_ASSIGN	699	1	0	0.00
CONT_ASSIGN	700	1	1	100.00
CONT_ASSIGN	700	1	1	100.00
CONT_ASSIGN	701	1	1	100.00
CONT_ASSIGN	701	1	1	100.00
CONT_ASSIGN	705	1	1	100.00
CONT_ASSIGN	705	1	1	100.00
CONT_ASSIGN	706	1	1	100.00
CONT_ASSIGN	706	1	1	100.00
CONT_ASSIGN	707	1	1	100.00
CONT_ASSIGN	707	1	1	100.00
CONT_ASSIGN	714	1	1	100.00
CONT_ASSIGN	715	1	0	0.00
CONT_ASSIGN	716	1	0	0.00
CONT_ASSIGN	719	1	1	100.00
CONT_ASSIGN	721	1	1	100.00
CONT_ASSIGN	723	1	0	0.00
CONT_ASSIGN	725	1	0	0.00
CONT_ASSIGN	732	1	1	100.00
CONT_ASSIGN	734	1	1	100.00
CONT_ASSIGN	736	1	1	100.00
CONT_ASSIGN	738	1	1	100.00
CONT_ASSIGN	748	1	0	0.00
CONT_ASSIGN	749	1	1	100.00
CONT_ASSIGN	750	1	1	100.00
CONT_ASSIGN	751	1	0	0.00
CONT_ASSIGN	754	1	1	100.00
CONT_ASSIGN	757	1	1	100.00
ALWAYS	789	11	8	72.73
ALWAYS	805	7	7	100.00
CONT_ASSIGN	816	1	0	0.00
CONT_ASSIGN	835	1	0	0.00
CONT_ASSIGN	836	1	0	0.00
CONT_ASSIGN	837	1	0	0.00
CONT_ASSIGN	840	1	0	0.00
CONT_ASSIGN	844	0	0
CONT_ASSIGN	883	1	0	0.00
ALWAYS	936	0	0
CONT_ASSIGN	977	1	0	0.00
CONT_ASSIGN	979	1	0	0.00
CONT_ASSIGN	981	1	1	100.00
CONT_ASSIGN	983	1	0	0.00
CONT_ASSIGN	985	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
202	1	1
203	1	1
216	1	1
217	0	1
218	0	1
225	1	1
263	0	1
265	0	1
268	0	1
342	0	1
348	0	1
363	1	1
488	1	1
489	1	1
491	1	1
508	0	1
509	0	1
510	0	1
511	0	1
514	1	1
515	1	1
516	1	1
517	1	1
518	1	1
519	0	1
520	0	1
521	0	1
			MISSING_ELSE
699	0	2
700	2	2
701	2	2
705	2	2
706	2	2
707	2	2
714	1	1
715	0	1
716	0	1
719	1	1
721	1	1
723	0	1
725	0	1
732	1	1
734	1	1
736	1	1
738	1	1
748	0	1
749	1	1
750	1	1
751	0	1
754	1	1
757	1	1
789	1	1
790	1	1
791	1	1
793	1	1
794	1	1
795	1	1
796	1	1
797	1	1
798	0	1
799	0	1
800	0	1
			MISSING_ELSE
805	1	1
806	1	1
807	1	1
808	1	1
810	1	1
811	1	1
812	1	1
816	0	1
835	0	1
836	0	1
837	0	1
840	0	1
844		unreachable
883	0	1
936		unreachable
937		unreachable
938		unreachable
939		unreachable
			==> MISSING_ELSE
977	0	1
979	0	1
981	1	1
983	0	1
985	0	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex

	Total	Covered	Percent
Conditions	28	13	46.43
Logical	28	13	46.43
Non-Logical	0	0
Event	0	0

 LINE       216
 EXPRESSION (ibus_intg_err | dbus_intg_err | alert_major_bus)
             ------1------   ------2------   -------3-------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T13,T14,T15
0	0	1	Not Covered
0	1	0	Not Covered
1	0	0	Not Covered

 LINE       217
 EXPRESSION (alert_major_internal | double_fault)
             ----------1---------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T15
0	1	Not Covered
1	0	Not Covered

 LINE       348
 EXPRESSION (fatal_core_err ? Off : local_fetch_enable_q)
             -------1------

-1-	Status	Tests
0	Covered	T13,T14,T15
1	Not Covered

 LINE       732
 EXPRESSION (reg2hw.alert_test.fatal_sw_err.q & reg2hw.alert_test.fatal_sw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T19,T20,T36
1	1	Covered	T19,T20,T36

 LINE       734
 EXPRESSION (reg2hw.alert_test.recov_sw_err.q & reg2hw.alert_test.recov_sw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T19,T20,T36
1	0	Covered	T19,T20,T36
1	1	Not Covered

 LINE       736
 EXPRESSION (reg2hw.alert_test.fatal_hw_err.q & reg2hw.alert_test.fatal_hw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T19,T20,T36
1	1	Covered	T19,T20,T36

 LINE       738
 EXPRESSION (reg2hw.alert_test.recov_hw_err.q & reg2hw.alert_test.recov_hw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T19,T20,T36
1	0	Covered	T19,T20,T36
1	1	Not Covered

 LINE       750
 EXPRESSION (intg_err | fatal_intg_err | fatal_core_err)
             ----1---   -------2------   -------3------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T13,T14,T15
0	0	1	Not Covered
0	1	0	Not Covered
1	0	0	Not Covered

 LINE       797
 EXPRESSION (edn_req && edn_ack)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T19,T20,T36
1	1	Not Covered

---

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex

	Total	Covered	Percent
Totals	117	96	82.05
Total Bits	1604	992	61.85
Total Bits 0->1	802	496	61.85
Total Bits 1->0	802	496	61.85

Ports	117	96	82.05
Port Bits	1604	992	61.85
Port Bits 0->1	802	496	61.85
Port Bits 1->0	802	496	61.85

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_edn_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_edn_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_esc_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_esc_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_cpu_n_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ram_cfg_i.rf_cfg.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.rf_cfg.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.ram_cfg.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.ram_cfg.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
hart_id_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
boot_addr_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
corei_tl_h_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
corei_tl_h_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
corei_tl_h_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
corei_tl_h_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
corei_tl_h_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
corei_tl_h_o.a_address[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
corei_tl_h_o.a_source[5:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
corei_tl_h_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_size[1:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
corei_tl_h_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_opcode[2:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
corei_tl_h_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
corei_tl_h_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
corei_tl_h_i.d_error	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
corei_tl_h_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
corei_tl_h_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
corei_tl_h_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
corei_tl_h_i.d_sink	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
corei_tl_h_i.d_source[5:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
corei_tl_h_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_size[1:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
corei_tl_h_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
corei_tl_h_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cored_tl_h_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
cored_tl_h_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
cored_tl_h_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
cored_tl_h_o.a_user.instr_type[3:0]	Yes	Yes	T46,T1,T47	Yes	T46,T1,T47	OUTPUT
cored_tl_h_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
cored_tl_h_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
cored_tl_h_o.a_address[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
cored_tl_h_o.a_source[5:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
cored_tl_h_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_size[1:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
cored_tl_h_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_opcode[2:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
cored_tl_h_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
cored_tl_h_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cored_tl_h_i.d_error	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cored_tl_h_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cored_tl_h_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cored_tl_h_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cored_tl_h_i.d_sink	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cored_tl_h_i.d_source[5:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cored_tl_h_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_size[1:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cored_tl_h_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
cored_tl_h_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
irq_software_i	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	INPUT
irq_timer_i	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	INPUT
irq_external_i	Yes	Yes	T2,T8,T9	Yes	T2,T8,T9	INPUT
esc_tx_i.esc_n	No	No		No		INPUT
esc_tx_i.esc_p	No	No		No		INPUT
esc_rx_o.resp_n	No	No		No		OUTPUT
esc_rx_o.resp_p	No	No		No		OUTPUT
nmi_wdog_i	Yes	Yes	T2,T8,T9	Yes	T2,T8,T9	INPUT
debug_req_i	No	No		No		INPUT
crash_dump_o.current.exception_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.exception_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.last_data_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.next_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.current_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_exception_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_exception_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_valid	Unreachable	Unreachable		Unreachable		OUTPUT
lc_cpu_en_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
pwrmgr_cpu_en_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
pwrmgr_o.core_sleeping	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
scan_rst_ni	Unreachable	Unreachable		Unreachable		INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.d_ready	Yes	Yes	T4,T5,T21	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T21	Yes	T4,T5,T21	INPUT
cfg_tl_d_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T21	Yes	T4,T5,T21	INPUT
cfg_tl_d_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T21	Yes	T4,T5,T21	INPUT
cfg_tl_d_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_data[31:0]	Yes	Yes	T4,T5,T21	Yes	T4,T5,T21	INPUT
cfg_tl_d_i.a_mask[3:0]	Yes	Yes	T4,T5,T21	Yes	T4,T5,T21	INPUT
cfg_tl_d_i.a_address[7:0]	Yes	Yes	T4,T5,T21	Yes	T4,T5,T21	INPUT
cfg_tl_d_i.a_address[15:8]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[20:16]	Yes	Yes	T4,T5,T21	Yes	T4,T5,T21	INPUT
cfg_tl_d_i.a_address[23:21]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[24]	Yes	Yes	*T4,*T5,*T21	Yes	T4,T5,T21	INPUT
cfg_tl_d_i.a_address[29:25]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[30]	Yes	Yes	*T4,*T5,*T21	Yes	T4,T5,T21	INPUT
cfg_tl_d_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_source[5:0]	Yes	Yes	T4,T5,T21	Yes	T4,T5,T21	INPUT
cfg_tl_d_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_size[1:0]	Yes	Yes	T4,T5,T21	Yes	T4,T5,T21	INPUT
cfg_tl_d_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_opcode[2:0]	Yes	Yes	T4,T5,T21	Yes	T4,T5,T21	INPUT
cfg_tl_d_i.a_valid	Yes	Yes	T4,T5,T21	Yes	T4,T5,T21	INPUT
cfg_tl_d_o.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
cfg_tl_d_o.d_error	Yes	Yes	T4,T5,T21	Yes	T4,T5,T21	OUTPUT
cfg_tl_d_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T21	Yes	T4,T5,T21	OUTPUT
cfg_tl_d_o.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T21	Yes	T4,T5,T21	OUTPUT
cfg_tl_d_o.d_data[31:0]	Yes	Yes	T4,T5,T21	Yes	T4,T5,T21	OUTPUT
cfg_tl_d_o.d_sink	Yes	Yes	T4,T5,T21	Yes	T4,T5,T21	OUTPUT
cfg_tl_d_o.d_source[5:0]	Yes	Yes	T4,T5,T21	Yes	T4,T5,T21	OUTPUT
cfg_tl_d_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_size[1:0]	Yes	Yes	T4,T5,T21	Yes	T4,T5,T21	OUTPUT
cfg_tl_d_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T21	Yes	T4,T5,T21	OUTPUT
cfg_tl_d_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_valid	Yes	Yes	T4,T5,T21	Yes	T4,T5,T21	OUTPUT
edn_o.edn_req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i.edn_bus[31:0]	No	No		No		INPUT
edn_i.edn_fips	No	No		No		INPUT
edn_i.edn_ack	No	No		No		INPUT
clk_otp_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_otp_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
icache_otp_key_o.req	No	No		No		OUTPUT
icache_otp_key_i.seed_valid	No	No		No		INPUT
icache_otp_key_i.nonce[127:0]	No	No		No		INPUT
icache_otp_key_i.key[127:0]	No	No		No		INPUT
icache_otp_key_i.ack	No	No		No		INPUT
fpga_info_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	INPUT
alert_rx_i[0].ping_n	No	No		No		INPUT
alert_rx_i[0].ping_p	No	No		No		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	INPUT
alert_rx_i[1].ping_n	No	No		No		INPUT
alert_rx_i[1].ping_p	No	No		No		INPUT
alert_rx_i[2].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[2].ack_p	Yes	Yes	T2,T8,T9	Yes	T2,T8,T9	INPUT
alert_rx_i[2].ping_n	No	No		No		INPUT
alert_rx_i[2].ping_p	No	No		No		INPUT
alert_rx_i[3].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[3].ack_p	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	INPUT
alert_rx_i[3].ping_n	No	No		No		INPUT
alert_rx_i[3].ping_p	No	No		No		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	OUTPUT
alert_tx_o[2].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[2].alert_p	Yes	Yes	T2,T8,T9	Yes	T2,T8,T9	OUTPUT
alert_tx_o[3].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[3].alert_p	Yes	Yes	T2,T7,T8	Yes	T2,T7,T8	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex

	Line No.	Total	Covered	Percent
Branches		12	9	75.00
TERNARY	348	2	1	50.00
IF	488	2	2	100.00
IF	514	3	2	66.67
IF	793	3	2	66.67
IF	805	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	348	(fatal_core_err) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	488	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T15
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	514	if ((!rst_ni))
-2-:	518	if (double_fault)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T13,T14,T15
0	1	Not Covered
0	0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	793	if (reg2hw.rnd_data.re)
-2-:	797	if ((edn_req && edn_ack))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T19,T20,T36
0	1	Not Covered
0	0	Covered	T19,T20,T36

	LineNo.	Expression
-1-:	805	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T15
0	Covered	T13,T14,T15

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	9	47.37
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	9	47.37

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
FpvSecCmIbexFetchEnable0_A	10255138	0	0	0
FpvSecCmIbexFetchEnable1_A	10255138	253278	0	32
FpvSecCmIbexFetchEnable2_A	10255138	908038	0	32
FpvSecCmIbexFetchEnable3Rev_A	10255138	9344672	0	32
FpvSecCmIbexFetchEnable3_A	10255138	9344698	0	0
FpvSecCmIbexInstrIntgErrCheck_A	10255138	0	0	0
FpvSecCmIbexLoadRespIntgErrCheck_A	10255138	0	0	0
FpvSecCmIbexPcMismatchCheck_A	10255138	0	0	0
FpvSecCmIbexRfEccErrCheck_A	10255138	0	0	0
FpvSecCmIbexStoreRespIntgErrCheck_A	10255138	0	0	0
FpvSecCmRegWeOnehotCheck_A	10255138	0	0	0
FpvSecCmRvCoreRegWeOnehotCheck_A	10255138	0	0	0
g_instr_intg_err_assert_signals.AssertConnected_A	16	16	0	0
g_lsu_load_resp_intg_err_assert_signals.AssertConnected_A	16	16	0	0
g_lsu_store_resp_intg_err_assert_signals.AssertConnected_A	16	16	0	0
g_pc_mismatch_alert_o_assert_signals.AssertConnected_A	16	16	0	0
g_rf_ecc_err_comb_assert_signals.AssertConnected_A	16	16	0	0
gen_icache_scramble_asserts.IbexIcacheScrambleKeyForwardedToCore_A	10255138	0	0	0
gen_icache_scramble_asserts.IbexIcacheScrambleKeyRequestAfterFenceI_A	10255138	0	0	0

FpvSecCmIbexFetchEnable0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10255138	0	0	0

FpvSecCmIbexFetchEnable1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10255138	253278	0	32
T13	157387	19425	0	2
T14	157387	19425	0	2
T15	157387	19425	0	2
T29	157387	19425	0	2
T30	157387	19425	0	2
T31	157387	19425	0	2
T32	157387	19425	0	2
T33	157387	19425	0	2
T34	157387	19425	0	2
T35	157387	19425	0	2

FpvSecCmIbexFetchEnable2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10255138	908038	0	32
T13	157387	69793	0	2
T14	157387	69793	0	2
T15	157387	69793	0	2
T29	157387	69793	0	2
T30	157387	69793	0	2
T31	157387	69793	0	2
T32	157387	69793	0	2
T33	157387	69793	0	2
T34	157387	69793	0	2
T35	157387	69793	0	2

FpvSecCmIbexFetchEnable3Rev_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10255138	9344672	0	32
T13	157387	87422	0	2
T14	157387	87422	0	2
T15	157387	87422	0	2
T29	157387	87422	0	2
T30	157387	87422	0	2
T31	157387	87422	0	2
T32	157387	87422	0	2
T33	157387	87422	0	2
T34	157387	87422	0	2
T35	157387	87422	0	2

FpvSecCmIbexFetchEnable3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10255138	9344698	0	0
T13	157387	87424	0	0
T14	157387	87424	0	0
T15	157387	87424	0	0
T29	157387	87424	0	0
T30	157387	87424	0	0
T31	157387	87424	0	0
T32	157387	87424	0	0
T33	157387	87424	0	0
T34	157387	87424	0	0
T35	157387	87424	0	0

FpvSecCmIbexInstrIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10255138	0	0	0

FpvSecCmIbexLoadRespIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10255138	0	0	0

FpvSecCmIbexPcMismatchCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10255138	0	0	0

FpvSecCmIbexRfEccErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10255138	0	0	0

FpvSecCmIbexStoreRespIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10255138	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10255138	0	0	0

FpvSecCmRvCoreRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10255138	0	0	0

g_instr_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16	16	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T35	1	1	0	0

g_lsu_load_resp_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16	16	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T35	1	1	0	0

g_lsu_store_resp_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16	16	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T35	1	1	0	0

g_pc_mismatch_alert_o_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16	16	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T35	1	1	0	0

g_rf_ecc_err_comb_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16	16	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T35	1	1	0	0

gen_icache_scramble_asserts.IbexIcacheScrambleKeyForwardedToCore_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10255138	0	0	0

gen_icache_scramble_asserts.IbexIcacheScrambleKeyRequestAfterFenceI_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10255138	0	0	0