Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.12	95.12	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	95.12	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.12	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	1	37	97.37
Crosses	3	1	2	66.67

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	1	2	66.67	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	1	2	66.67	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	14683	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

16987

1

T1

39

T2

39

T3

39

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	1	2	66.67

User Defined Bins for cp_opcode

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
values[0x4]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

15947

1

T1

20

T2

24

T3

21

values[0x1]

15723

1

T1

19

T2

15

T3

18

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	9478	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

22192

1

T1

39

T2

39

T3

39

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	348	1			T9	1		T4	40		T5	71
valid_sources[0x01]	430	1			T4	52		T5	65		T7	40
valid_sources[0x02]	352	1			T4	40		T5	91		T7	50
valid_sources[0x03]	351	1			T9	4		T4	52		T5	16
valid_sources[0x04]	362	1			T9	1		T4	51		T5	69
valid_sources[0x05]	262	1			T10	1		T4	35		T5	28
valid_sources[0x06]	417	1			T4	47		T5	75		T7	51
valid_sources[0x07]	382	1			T4	60		T5	37		T6	64
valid_sources[0x08]	388	1			T4	51		T5	30		T7	36
valid_sources[0x09]	354	1			T2	39		T4	47		T5	36
valid_sources[0x0a]	283	1			T4	49		T5	27		T7	42
valid_sources[0x0b]	446	1			T4	53		T5	23		T6	110
valid_sources[0x0c]	412	1			T4	45		T5	83		T7	47
valid_sources[0x0d]	372	1			T3	1		T4	52		T5	79
valid_sources[0x0e]	3865	1			T4	55		T5	63		T6	3509
valid_sources[0x0f]	508	1			T9	7		T4	51		T5	62
valid_sources[0x10]	641	1			T4	73		T5	124		T7	47
valid_sources[0x11]	614	1			T9	1		T4	53		T5	27
valid_sources[0x12]	325	1			T4	47		T5	22		T7	63
valid_sources[0x13]	2809	1			T4	72		T5	52		T6	149
valid_sources[0x14]	362	1			T4	66		T5	50		T7	46
valid_sources[0x15]	332	1			T4	53		T5	82		T7	43
valid_sources[0x16]	429	1			T10	1		T4	45		T5	78
valid_sources[0x17]	609	1			T9	1		T4	60		T5	73
valid_sources[0x18]	313	1			T4	58		T5	33		T7	53
valid_sources[0x19]	362	1			T4	46		T5	57		T7	35
valid_sources[0x1a]	317	1			T9	1		T4	48		T5	18
valid_sources[0x1b]	949	1			T3	2		T9	2		T4	52
valid_sources[0x1c]	353	1			T10	1		T4	49		T5	48
valid_sources[0x1d]	371	1			T10	1		T4	45		T5	44
valid_sources[0x1e]	466	1			T4	40		T5	35		T7	39
valid_sources[0x1f]	291	1			T10	1		T4	39		T5	44
valid_sources[0x20]	429	1			T4	56		T5	78		T7	46

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	1	2	66.67	1

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Element holes

cp_opcode	cp_mask	cp_size	COUNT	AT LEAST	NUMBER	STATUS
[values[0x4]]	*	*	0	1	1

Covered bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

all_enables

biggest_size

11118

1

T1

20

T2

24

T3

21

values[0x1]

all_enables

biggest_size

5869

1

T1

19

T2

15

T3

18