Unified Coverage Report :: Module :: keymgr

Module : keymgr

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
25.13			25.13

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_keymgr	25.13			25.13

---

Module Instance : tb.dut.top_earlgrey.u_keymgr

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
25.13			25.13

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
25.13			25.13

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.37	55.20		73.92			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : keymgr

	Total	Covered	Percent
Totals	67	15	22.39
Total Bits	8938	2246	25.13
Total Bits 0->1	4469	1123	25.13
Total Bits 1->0	4469	1123	25.13

Ports	67	15	22.39
Port Bits	8938	2246	25.13
Port Bits 0->1	4469	1123	25.13
Port Bits 1->0	4469	1123	25.13

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_shadowed_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_edn_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_edn_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	No	No		No		INPUT
tl_i.a_user.cmd_intg[6:0]	No	No		No		INPUT
tl_i.a_user.instr_type[3:0]	No	No		No		INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	No	No		No		INPUT
tl_i.a_mask[3:0]	No	No		No		INPUT
tl_i.a_address[7:0]	No	No		No		INPUT
tl_i.a_address[17:8]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[18]	No	No		No		INPUT
tl_i.a_address[19]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[20]	No	No		No		INPUT
tl_i.a_address[23:21]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[24]	No	No		No		INPUT
tl_i.a_address[29:25]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	No	No		No		INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	No	No		No		INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	No	No		No		INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	No	No		No		INPUT
tl_i.a_valid	No	No		No		INPUT
tl_o.a_ready	No	No		No		OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[6:0]	No	No		No		OUTPUT
tl_o.d_data[31:0]	No	No		No		OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[5:0]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	No	No		No		OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	No	No		No		OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	No	No		No		OUTPUT
aes_key_o.key[1:0][255:0]	No	No		No		OUTPUT
aes_key_o.valid	No	No		No		OUTPUT
kmac_key_o.key[1:0][255:0]	No	No		No		OUTPUT
kmac_key_o.valid	No	No		No		OUTPUT
otbn_key_o.key[1:0][383:0]	No	No		No		OUTPUT
otbn_key_o.valid	No	No		No		OUTPUT
kmac_data_o.last	No	No		No		OUTPUT
kmac_data_o.strb[7:0]	No	No		No		OUTPUT
kmac_data_o.data[63:0]	No	No		No		OUTPUT
kmac_data_o.valid	No	No		No		OUTPUT
kmac_data_i.error	No	No		No		INPUT
kmac_data_i.digest_share1[383:0]	No	No		No		INPUT
kmac_data_i.digest_share0[383:0]	No	No		No		INPUT
kmac_data_i.done	No	No		No		INPUT
kmac_data_i.ready	No	No		No		INPUT
kmac_en_masking_i	Unreachable	Unreachable		Unreachable		INPUT
lc_keymgr_en_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
lc_keymgr_div_i[2:0]	Unreachable	Unreachable		Unreachable		INPUT
lc_keymgr_div_i[6:3]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
lc_keymgr_div_i[8:7]	Unreachable	Unreachable		Unreachable		INPUT
lc_keymgr_div_i[9]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
lc_keymgr_div_i[10]	Unreachable	Unreachable		Unreachable		INPUT
lc_keymgr_div_i[19:11]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
lc_keymgr_div_i[20]	Unreachable	Unreachable		Unreachable		INPUT
lc_keymgr_div_i[26:21]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
lc_keymgr_div_i[27]	Unreachable	Unreachable		Unreachable		INPUT
lc_keymgr_div_i[37:28]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
lc_keymgr_div_i[38]	Unreachable	Unreachable		Unreachable		INPUT
lc_keymgr_div_i[39]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
lc_keymgr_div_i[40]	Unreachable	Unreachable		Unreachable		INPUT
lc_keymgr_div_i[41]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
lc_keymgr_div_i[42]	Unreachable	Unreachable		Unreachable		INPUT
lc_keymgr_div_i[43]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
lc_keymgr_div_i[44]	Unreachable	Unreachable		Unreachable		INPUT
lc_keymgr_div_i[45]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
lc_keymgr_div_i[46]	Unreachable	Unreachable		Unreachable		INPUT
lc_keymgr_div_i[50:47]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
lc_keymgr_div_i[51]	Unreachable	Unreachable		Unreachable		INPUT
lc_keymgr_div_i[61:52]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
lc_keymgr_div_i[63:62]	Unreachable	Unreachable		Unreachable		INPUT
lc_keymgr_div_i[66:64]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
lc_keymgr_div_i[68:67]	Unreachable	Unreachable		Unreachable		INPUT
lc_keymgr_div_i[72:69]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
lc_keymgr_div_i[73]	Unreachable	Unreachable		Unreachable		INPUT
lc_keymgr_div_i[75:74]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
lc_keymgr_div_i[76]	Unreachable	Unreachable		Unreachable		INPUT
lc_keymgr_div_i[81:77]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
lc_keymgr_div_i[82]	Unreachable	Unreachable		Unreachable		INPUT
lc_keymgr_div_i[91:83]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
lc_keymgr_div_i[92]	Unreachable	Unreachable		Unreachable		INPUT
lc_keymgr_div_i[97:93]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
lc_keymgr_div_i[98]	Unreachable	Unreachable		Unreachable		INPUT
lc_keymgr_div_i[99]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
lc_keymgr_div_i[100]	Unreachable	Unreachable		Unreachable		INPUT
lc_keymgr_div_i[101]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
lc_keymgr_div_i[102]	Unreachable	Unreachable		Unreachable		INPUT
lc_keymgr_div_i[103]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
lc_keymgr_div_i[104]	Unreachable	Unreachable		Unreachable		INPUT
lc_keymgr_div_i[105]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
lc_keymgr_div_i[106]	Unreachable	Unreachable		Unreachable		INPUT
lc_keymgr_div_i[108:107]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
lc_keymgr_div_i[109]	Unreachable	Unreachable		Unreachable		INPUT
lc_keymgr_div_i[112:110]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
lc_keymgr_div_i[113]	Unreachable	Unreachable		Unreachable		INPUT
lc_keymgr_div_i[119:114]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
lc_keymgr_div_i[120]	Unreachable	Unreachable		Unreachable		INPUT
lc_keymgr_div_i[121]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
lc_keymgr_div_i[122]	Unreachable	Unreachable		Unreachable		INPUT
lc_keymgr_div_i[124:123]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
lc_keymgr_div_i[125]	Unreachable	Unreachable		Unreachable		INPUT
lc_keymgr_div_i[127:126]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
otp_key_i.key_share1[46:0]	Yes	Yes	*T1,*T9,*T3	Yes	T1,T9,T3	INPUT
otp_key_i.key_share1[47]	No	No		No		INPUT
otp_key_i.key_share1[64:48]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
otp_key_i.key_share1[65]	No	No		No		INPUT
otp_key_i.key_share1[188:66]	Yes	Yes	*T1,*T3,*T2	Yes	T1,T3,T2	INPUT
otp_key_i.key_share1[189]	No	No		No		INPUT
otp_key_i.key_share1[219:190]	Yes	Yes	*T9,*T11,*T1	Yes	T9,T11,T1	INPUT
otp_key_i.key_share1[220]	No	No		No		INPUT
otp_key_i.key_share1[255:221]	Yes	Yes	T1,T9,T11	Yes	T1,T9,T11	INPUT
otp_key_i.key_share0[3:0]	Yes	Yes	*T3,*T9,*T11	Yes	T3,T9,T11	INPUT
otp_key_i.key_share0[4]	No	No		No		INPUT
otp_key_i.key_share0[34:5]	Yes	Yes	*T1,*T2,*T9	Yes	T1,T2,T9	INPUT
otp_key_i.key_share0[35]	No	No		No		INPUT
otp_key_i.key_share0[53:36]	Yes	Yes	*T1,*T9,*T10	Yes	T1,T9,T10	INPUT
otp_key_i.key_share0[54]	No	No		No		INPUT
otp_key_i.key_share0[79:55]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
otp_key_i.key_share0[80]	No	No		No		INPUT
otp_key_i.key_share0[105:81]	Yes	Yes	*T1,*T3,*T11	Yes	T1,T3,T11	INPUT
otp_key_i.key_share0[106]	No	No		No		INPUT
otp_key_i.key_share0[178:107]	Yes	Yes	*T1,*T11,*T3	Yes	T1,T11,T3	INPUT
otp_key_i.key_share0[179]	No	No		No		INPUT
otp_key_i.key_share0[213:180]	Yes	Yes	*T1,*T2,*T9	Yes	T1,T2,T9	INPUT
otp_key_i.key_share0[214]	No	No		No		INPUT
otp_key_i.key_share0[236:215]	Yes	Yes	*T1,*T3,*T9	Yes	T1,T3,T9	INPUT
otp_key_i.key_share0[237]	No	No		No		INPUT
otp_key_i.key_share0[255:238]	Yes	Yes	T3,T9,T1	Yes	T3,T9,T1	INPUT
otp_key_i.valid	No	No		No		INPUT
otp_device_id_i[255:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
flash_i.seeds[1:0][255:0]	No	No		No		INPUT
edn_o.edn_req	No	No		No		OUTPUT
edn_i.edn_bus[31:0]	No	No		No		INPUT
edn_i.edn_fips	No	No		No		INPUT
edn_i.edn_ack	No	No		No		INPUT
rom_digest_i.valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rom_digest_i.data[255:0]	Yes	Yes	T3,T10,T11	Yes	T3,T10,T11	INPUT
intr_op_done_o	No	No		No		OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	No	No		No		INPUT
alert_rx_i[0].ping_n	No	No		No		INPUT
alert_rx_i[0].ping_p	No	No		No		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	No	No		No		INPUT
alert_rx_i[1].ping_n	No	No		No		INPUT
alert_rx_i[1].ping_p	No	No		No		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	No	No		No		OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	No	No		No		OUTPUT

*Tests covering at least one bit in the range