Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	0.00					80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	0.00					80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
52.50	25.00					80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
52.50	25.00					80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
52.50	25.00					80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
52.50	25.00					80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
50.00		50.00			50.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
65.00	50.00					80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
65.00	50.00					80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
50.00		50.00			50.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	0	0.00
CONT_ASSIGN	44	1	0	0.00
CONT_ASSIGN	45	1	0	0.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	0	1
45	0	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	4	80.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	4	80.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	8439605	0	0	0
DepthKnown_A	8439605	8437267	0	0
RvalidKnown_A	8439605	8437267	0	0
WreadyKnown_A	8439605	8437267	0	0
gen_passthru_fifo.paramCheckPass	16	16	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8439605	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8439605	8437267	0	0
T1	110239	110228	0	0
T2	196091	196080	0	0
T3	759412	759299	0	0
T4	178775	178615	0	0
T5	168213	168045	0	0
T6	171799	171639	0	0
T7	168610	168439	0	0
T9	110086	110074	0	0
T10	111558	111547	0	0
T11	756518	756405	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8439605	8437267	0	0
T1	110239	110228	0	0
T2	196091	196080	0	0
T3	759412	759299	0	0
T4	178775	178615	0	0
T5	168213	168045	0	0
T6	171799	171639	0	0
T7	168610	168439	0	0
T9	110086	110074	0	0
T10	111558	111547	0	0
T11	756518	756405	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8439605	8437267	0	0
T1	110239	110228	0	0
T2	196091	196080	0	0
T3	759412	759299	0	0
T4	178775	178615	0	0
T5	168213	168045	0	0
T6	171799	171639	0	0
T7	168610	168439	0	0
T9	110086	110074	0	0
T10	111558	111547	0	0
T11	756518	756405	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	16	16	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	1	25.00
CONT_ASSIGN	44	1	0	0.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	0	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	4	80.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	4	80.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	8439605	0	0	0
DepthKnown_A	8439605	8437267	0	0
RvalidKnown_A	8439605	8437267	0	0
WreadyKnown_A	8439605	8437267	0	0
gen_passthru_fifo.paramCheckPass	16	16	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8439605	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8439605	8437267	0	0
T1	110239	110228	0	0
T2	196091	196080	0	0
T3	759412	759299	0	0
T4	178775	178615	0	0
T5	168213	168045	0	0
T6	171799	171639	0	0
T7	168610	168439	0	0
T9	110086	110074	0	0
T10	111558	111547	0	0
T11	756518	756405	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8439605	8437267	0	0
T1	110239	110228	0	0
T2	196091	196080	0	0
T3	759412	759299	0	0
T4	178775	178615	0	0
T5	168213	168045	0	0
T6	171799	171639	0	0
T7	168610	168439	0	0
T9	110086	110074	0	0
T10	111558	111547	0	0
T11	756518	756405	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8439605	8437267	0	0
T1	110239	110228	0	0
T2	196091	196080	0	0
T3	759412	759299	0	0
T4	178775	178615	0	0
T5	168213	168045	0	0
T6	171799	171639	0	0
T7	168610	168439	0	0
T9	110086	110074	0	0
T10	111558	111547	0	0
T11	756518	756405	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	16	16	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	8439605	42493	0	0
DepthKnown_A	8439605	8437267	0	0
RvalidKnown_A	8439605	8437267	0	0
WreadyKnown_A	8439605	8437267	0	0
gen_passthru_fifo.paramCheckPass	16	16	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8439605	42493	0	0
T1	110239	39	0	0
T2	196091	39	0	0
T3	759412	39	0	0
T4	178775	3655	0	0
T5	168213	6565	0	0
T6	171799	5129	0	0
T7	168610	3111	0	0
T9	110086	39	0	0
T10	111558	39	0	0
T11	756518	39	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8439605	8437267	0	0
T1	110239	110228	0	0
T2	196091	196080	0	0
T3	759412	759299	0	0
T4	178775	178615	0	0
T5	168213	168045	0	0
T6	171799	171639	0	0
T7	168610	168439	0	0
T9	110086	110074	0	0
T10	111558	111547	0	0
T11	756518	756405	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8439605	8437267	0	0
T1	110239	110228	0	0
T2	196091	196080	0	0
T3	759412	759299	0	0
T4	178775	178615	0	0
T5	168213	168045	0	0
T6	171799	171639	0	0
T7	168610	168439	0	0
T9	110086	110074	0	0
T10	111558	111547	0	0
T11	756518	756405	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8439605	8437267	0	0
T1	110239	110228	0	0
T2	196091	196080	0	0
T3	759412	759299	0	0
T4	178775	178615	0	0
T5	168213	168045	0	0
T6	171799	171639	0	0
T7	168610	168439	0	0
T9	110086	110074	0	0
T10	111558	111547	0	0
T11	756518	756405	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	16	16	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	8439605	93330	0	0
DepthKnown_A	8439605	8437267	0	0
RvalidKnown_A	8439605	8437267	0	0
WreadyKnown_A	8439605	8437267	0	0
gen_passthru_fifo.paramCheckPass	16	16	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8439605	93330	0	0
T1	110239	166	0	0
T2	196091	39	0	0
T3	759412	39	0	0
T4	178775	14329	0	0
T5	168213	3926	0	0
T6	171799	3974	0	0
T7	168610	12719	0	0
T9	110086	184	0	0
T10	111558	184	0	0
T11	756518	169	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8439605	8437267	0	0
T1	110239	110228	0	0
T2	196091	196080	0	0
T3	759412	759299	0	0
T4	178775	178615	0	0
T5	168213	168045	0	0
T6	171799	171639	0	0
T7	168610	168439	0	0
T9	110086	110074	0	0
T10	111558	111547	0	0
T11	756518	756405	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8439605	8437267	0	0
T1	110239	110228	0	0
T2	196091	196080	0	0
T3	759412	759299	0	0
T4	178775	178615	0	0
T5	168213	168045	0	0
T6	171799	171639	0	0
T7	168610	168439	0	0
T9	110086	110074	0	0
T10	111558	111547	0	0
T11	756518	756405	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8439605	8437267	0	0
T1	110239	110228	0	0
T2	196091	196080	0	0
T3	759412	759299	0	0
T4	178775	178615	0	0
T5	168213	168045	0	0
T6	171799	171639	0	0
T7	168610	168439	0	0
T9	110086	110074	0	0
T10	111558	111547	0	0
T11	756518	756405	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	16	16	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	8439605	92	0	0
DepthKnown_A	8439605	8437267	0	0
RvalidKnown_A	8439605	8437267	0	0
WreadyKnown_A	8439605	8437267	0	0
gen_passthru_fifo.paramCheckPass	16	16	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8439605	92	0	0
T2	196091	92	0	0
T3	759412	0	0	0
T9	110086	0	0	0
T10	111558	0	0	0
T11	756518	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8439605	8437267	0	0
T1	110239	110228	0	0
T2	196091	196080	0	0
T3	759412	759299	0	0
T4	178775	178615	0	0
T5	168213	168045	0	0
T6	171799	171639	0	0
T7	168610	168439	0	0
T9	110086	110074	0	0
T10	111558	111547	0	0
T11	756518	756405	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8439605	8437267	0	0
T1	110239	110228	0	0
T2	196091	196080	0	0
T3	759412	759299	0	0
T4	178775	178615	0	0
T5	168213	168045	0	0
T6	171799	171639	0	0
T7	168610	168439	0	0
T9	110086	110074	0	0
T10	111558	111547	0	0
T11	756518	756405	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8439605	8437267	0	0
T1	110239	110228	0	0
T2	196091	196080	0	0
T3	759412	759299	0	0
T4	178775	178615	0	0
T5	168213	168045	0	0
T6	171799	171639	0	0
T7	168610	168439	0	0
T9	110086	110074	0	0
T10	111558	111547	0	0
T11	756518	756405	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	16	16	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	8439605	92	0	0
DepthKnown_A	8439605	8437267	0	0
RvalidKnown_A	8439605	8437267	0	0
WreadyKnown_A	8439605	8437267	0	0
gen_passthru_fifo.paramCheckPass	16	16	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8439605	92	0	0
T2	196091	92	0	0
T3	759412	0	0	0
T9	110086	0	0	0
T10	111558	0	0	0
T11	756518	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8439605	8437267	0	0
T1	110239	110228	0	0
T2	196091	196080	0	0
T3	759412	759299	0	0
T4	178775	178615	0	0
T5	168213	168045	0	0
T6	171799	171639	0	0
T7	168610	168439	0	0
T9	110086	110074	0	0
T10	111558	111547	0	0
T11	756518	756405	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8439605	8437267	0	0
T1	110239	110228	0	0
T2	196091	196080	0	0
T3	759412	759299	0	0
T4	178775	178615	0	0
T5	168213	168045	0	0
T6	171799	171639	0	0
T7	168610	168439	0	0
T9	110086	110074	0	0
T10	111558	111547	0	0
T11	756518	756405	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8439605	8437267	0	0
T1	110239	110228	0	0
T2	196091	196080	0	0
T3	759412	759299	0	0
T4	178775	178615	0	0
T5	168213	168045	0	0
T6	171799	171639	0	0
T7	168610	168439	0	0
T9	110086	110074	0	0
T10	111558	111547	0	0
T11	756518	756405	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	16	16	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	1	25.00
CONT_ASSIGN	44	1	0	0.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	0	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	4	80.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	4	80.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	8439605	0	0	0
DepthKnown_A	8439605	8437267	0	0
RvalidKnown_A	8439605	8437267	0	0
WreadyKnown_A	8439605	8437267	0	0
gen_passthru_fifo.paramCheckPass	16	16	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8439605	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8439605	8437267	0	0
T1	110239	110228	0	0
T2	196091	196080	0	0
T3	759412	759299	0	0
T4	178775	178615	0	0
T5	168213	168045	0	0
T6	171799	171639	0	0
T7	168610	168439	0	0
T9	110086	110074	0	0
T10	111558	111547	0	0
T11	756518	756405	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8439605	8437267	0	0
T1	110239	110228	0	0
T2	196091	196080	0	0
T3	759412	759299	0	0
T4	178775	178615	0	0
T5	168213	168045	0	0
T6	171799	171639	0	0
T7	168610	168439	0	0
T9	110086	110074	0	0
T10	111558	111547	0	0
T11	756518	756405	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8439605	8437267	0	0
T1	110239	110228	0	0
T2	196091	196080	0	0
T3	759412	759299	0	0
T4	178775	178615	0	0
T5	168213	168045	0	0
T6	171799	171639	0	0
T7	168610	168439	0	0
T9	110086	110074	0	0
T10	111558	111547	0	0
T11	756518	756405	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	16	16	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	0	0.00
CONT_ASSIGN	45	1	0	0.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	0	1
45	0	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	4	80.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	4	80.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	8439605	0	0	0
DepthKnown_A	8439605	8437267	0	0
RvalidKnown_A	8439605	8437267	0	0
WreadyKnown_A	8439605	8437267	0	0
gen_passthru_fifo.paramCheckPass	16	16	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8439605	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8439605	8437267	0	0
T1	110239	110228	0	0
T2	196091	196080	0	0
T3	759412	759299	0	0
T4	178775	178615	0	0
T5	168213	168045	0	0
T6	171799	171639	0	0
T7	168610	168439	0	0
T9	110086	110074	0	0
T10	111558	111547	0	0
T11	756518	756405	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8439605	8437267	0	0
T1	110239	110228	0	0
T2	196091	196080	0	0
T3	759412	759299	0	0
T4	178775	178615	0	0
T5	168213	168045	0	0
T6	171799	171639	0	0
T7	168610	168439	0	0
T9	110086	110074	0	0
T10	111558	111547	0	0
T11	756518	756405	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8439605	8437267	0	0
T1	110239	110228	0	0
T2	196091	196080	0	0
T3	759412	759299	0	0
T4	178775	178615	0	0
T5	168213	168045	0	0
T6	171799	171639	0	0
T7	168610	168439	0	0
T9	110086	110074	0	0
T10	111558	111547	0	0
T11	756518	756405	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	16	16	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	8439605	92	0	0
DepthKnown_A	8439605	8437267	0	0
RvalidKnown_A	8439605	8437267	0	0
WreadyKnown_A	8439605	8437267	0	0
gen_passthru_fifo.paramCheckPass	16	16	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8439605	92	0	0
T2	196091	92	0	0
T3	759412	0	0	0
T9	110086	0	0	0
T10	111558	0	0	0
T11	756518	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8439605	8437267	0	0
T1	110239	110228	0	0
T2	196091	196080	0	0
T3	759412	759299	0	0
T4	178775	178615	0	0
T5	168213	168045	0	0
T6	171799	171639	0	0
T7	168610	168439	0	0
T9	110086	110074	0	0
T10	111558	111547	0	0
T11	756518	756405	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8439605	8437267	0	0
T1	110239	110228	0	0
T2	196091	196080	0	0
T3	759412	759299	0	0
T4	178775	178615	0	0
T5	168213	168045	0	0
T6	171799	171639	0	0
T7	168610	168439	0	0
T9	110086	110074	0	0
T10	111558	111547	0	0
T11	756518	756405	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8439605	8437267	0	0
T1	110239	110228	0	0
T2	196091	196080	0	0
T3	759412	759299	0	0
T4	178775	178615	0	0
T5	168213	168045	0	0
T6	171799	171639	0	0
T7	168610	168439	0	0
T9	110086	110074	0	0
T10	111558	111547	0	0
T11	756518	756405	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	16	16	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	8439605	92	0	0
DepthKnown_A	8439605	8437267	0	0
RvalidKnown_A	8439605	8437267	0	0
WreadyKnown_A	8439605	8437267	0	0
gen_passthru_fifo.paramCheckPass	16	16	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8439605	92	0	0
T2	196091	92	0	0
T3	759412	0	0	0
T9	110086	0	0	0
T10	111558	0	0	0
T11	756518	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8439605	8437267	0	0
T1	110239	110228	0	0
T2	196091	196080	0	0
T3	759412	759299	0	0
T4	178775	178615	0	0
T5	168213	168045	0	0
T6	171799	171639	0	0
T7	168610	168439	0	0
T9	110086	110074	0	0
T10	111558	111547	0	0
T11	756518	756405	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8439605	8437267	0	0
T1	110239	110228	0	0
T2	196091	196080	0	0
T3	759412	759299	0	0
T4	178775	178615	0	0
T5	168213	168045	0	0
T6	171799	171639	0	0
T7	168610	168439	0	0
T9	110086	110074	0	0
T10	111558	111547	0	0
T11	756518	756405	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8439605	8437267	0	0
T1	110239	110228	0	0
T2	196091	196080	0	0
T3	759412	759299	0	0
T4	178775	178615	0	0
T5	168213	168045	0	0
T6	171799	171639	0	0
T7	168610	168439	0	0
T9	110086	110074	0	0
T10	111558	111547	0	0
T11	756518	756405	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	16	16	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0