Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_30_pull_en_30

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_30_pull_en_30

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_30_pull_select_30

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_30_keeper_en_30

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_30_schmitt_en_30

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_30_od_en_30

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_30_slew_rate_30

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_30_drive_strength_30

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_31_invert_31

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_31_virtual_od_en_31

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_31_pull_en_31

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_31_pull_select_31

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_31_keeper_en_31

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_31_schmitt_en_31

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_31_od_en_31

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_31_slew_rate_31

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_31_drive_strength_31

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_32_invert_32

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_32_virtual_od_en_32

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_32_pull_en_32

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_32_pull_select_32

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_32_keeper_en_32

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_32_schmitt_en_32

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_32_od_en_32

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_32_slew_rate_32

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_32_drive_strength_32

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_33_invert_33

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_33_virtual_od_en_33

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_33_pull_en_33

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_33_pull_select_33

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_33_keeper_en_33

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_33_schmitt_en_33

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_33_od_en_33

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_33_slew_rate_33

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_33_drive_strength_33

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_34_invert_34

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_34_virtual_od_en_34

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_34_pull_en_34

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_34_pull_select_34

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_34_keeper_en_34

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_34_schmitt_en_34

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_34_od_en_34

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_34_slew_rate_34

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_34_drive_strength_34

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_35_invert_35

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_35_virtual_od_en_35

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_35_pull_en_35

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_35_pull_select_35

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_35_keeper_en_35

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_35_schmitt_en_35

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_35_od_en_35

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_35_slew_rate_35

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_35_drive_strength_35

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_36_invert_36

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_36_virtual_od_en_36

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_36_pull_en_36

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_36_pull_select_36

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_36_keeper_en_36

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_36_schmitt_en_36

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_36_od_en_36

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_36_slew_rate_36

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_36_drive_strength_36

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_37_invert_37

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_37_virtual_od_en_37

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_37_pull_en_37

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_37_pull_select_37

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_37_keeper_en_37

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_37_schmitt_en_37

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_37_od_en_37

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_37_slew_rate_37

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_37_drive_strength_37

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_38_invert_38

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_38_virtual_od_en_38

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_38_pull_en_38

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_38_pull_select_38

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_38_keeper_en_38

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_38_schmitt_en_38

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_38_od_en_38

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_38_slew_rate_38

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_38_drive_strength_38

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_39_invert_39

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_39_virtual_od_en_39

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_39_pull_en_39

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_39_pull_select_39

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_39_keeper_en_39

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_39_schmitt_en_39

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_39_od_en_39

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_39_slew_rate_39

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_39_drive_strength_39

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_40_invert_40

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_40_virtual_od_en_40

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_40_pull_en_40

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_40_pull_select_40

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_40_keeper_en_40

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_40_schmitt_en_40

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_40_od_en_40

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_40_slew_rate_40

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_40_drive_strength_40

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_41_invert_41

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_41_virtual_od_en_41

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_41_pull_en_41

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_41_pull_select_41

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_41_keeper_en_41

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_41_schmitt_en_41

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_41_od_en_41

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_41_slew_rate_41

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_41_drive_strength_41

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_42_invert_42

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_42_virtual_od_en_42

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_42_pull_en_42

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_42_pull_select_42

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_42_keeper_en_42

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_42_schmitt_en_42

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_42_od_en_42

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_42_slew_rate_42

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_42_drive_strength_42

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_43_invert_43

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_43_virtual_od_en_43

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_43_pull_en_43

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_43_pull_select_43

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_43_keeper_en_43

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_43_schmitt_en_43

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_43_od_en_43

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_43_slew_rate_43

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_43_drive_strength_43

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_44_invert_44

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_44_virtual_od_en_44

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_44_pull_en_44

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_44_pull_select_44

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_44_keeper_en_44

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_44_schmitt_en_44

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_44_od_en_44

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_44_slew_rate_44

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_44_drive_strength_44

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_45_invert_45

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_45_virtual_od_en_45

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_45_pull_en_45

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_45_pull_select_45

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_45_keeper_en_45

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_45_schmitt_en_45

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_45_od_en_45

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_45_slew_rate_45

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_45_drive_strength_45

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_46_invert_46

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_46_virtual_od_en_46

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_46_pull_en_46

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_46_pull_select_46

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_46_keeper_en_46

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_46_schmitt_en_46

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_46_od_en_46

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_46_slew_rate_46

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_46_drive_strength_46

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_0_invert_0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_0_virtual_od_en_0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_0_pull_en_0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_0_pull_select_0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_0_keeper_en_0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_0_schmitt_en_0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_0_od_en_0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_0_slew_rate_0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_0_drive_strength_0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_1_invert_1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_1_virtual_od_en_1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_1_pull_en_1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_1_pull_select_1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_1_keeper_en_1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_1_schmitt_en_1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_1_od_en_1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_1_slew_rate_1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_1_drive_strength_1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_2_invert_2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_2_virtual_od_en_2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_2_pull_en_2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_2_pull_select_2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_2_keeper_en_2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_2_schmitt_en_2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_2_od_en_2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_2_slew_rate_2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_2_drive_strength_2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_3_invert_3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_3_virtual_od_en_3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_3_pull_en_3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_3_pull_select_3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_3_keeper_en_3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_3_schmitt_en_3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_3_od_en_3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_3_slew_rate_3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_3_drive_strength_3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_4_invert_4

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_4_virtual_od_en_4

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_4_pull_en_4

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_4_pull_select_4

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_4_keeper_en_4

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_4_schmitt_en_4

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_4_od_en_4

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_4_slew_rate_4

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_4_drive_strength_4

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_5_invert_5

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_5_virtual_od_en_5

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_5_pull_en_5

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_5_pull_select_5

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_5_keeper_en_5

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_5_schmitt_en_5

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_5_od_en_5

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_5_slew_rate_5

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_5_drive_strength_5

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_6_invert_6

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_6_virtual_od_en_6

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_6_pull_en_6

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_6_pull_select_6

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_6_keeper_en_6

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_6_schmitt_en_6

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_6_od_en_6

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_6_slew_rate_6

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_6_drive_strength_6

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_7_invert_7

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_7_virtual_od_en_7

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_7_pull_en_7

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_7_pull_select_7

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_7_keeper_en_7

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_7_schmitt_en_7

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_7_od_en_7

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_7_slew_rate_7

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_7_drive_strength_7

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_8_invert_8

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_8_virtual_od_en_8

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_8_pull_en_8

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_8_pull_select_8

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_8_keeper_en_8

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_8_schmitt_en_8

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_8_od_en_8

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_8_slew_rate_8

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_8_drive_strength_8

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_9_invert_9

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_9_virtual_od_en_9

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_9_pull_en_9

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_9_pull_select_9

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_9_keeper_en_9

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_9_schmitt_en_9

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_9_od_en_9

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_9_slew_rate_9

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_9_drive_strength_9

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_10_invert_10

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_10_virtual_od_en_10

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_10_pull_en_10

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_10_pull_select_10

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_10_keeper_en_10

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_10_schmitt_en_10

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_10_od_en_10

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_10_slew_rate_10

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_10_drive_strength_10

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.01	98.85	69.51			99.67	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_30_pull_en_30

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_30_pull_select_30

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_30_keeper_en_30

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_30_schmitt_en_30

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_30_od_en_30

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_30_slew_rate_30

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_30_drive_strength_30

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_31_invert_31

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_31_virtual_od_en_31

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_31_pull_en_31

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_31_pull_select_31

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_31_keeper_en_31

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_31_schmitt_en_31

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_31_od_en_31

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_31_slew_rate_31

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_31_drive_strength_31

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_32_invert_32

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_32_virtual_od_en_32

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_32_pull_en_32

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_32_pull_select_32

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_32_keeper_en_32

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_32_schmitt_en_32

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_32_od_en_32

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_32_slew_rate_32

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_32_drive_strength_32

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_33_invert_33

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_33_virtual_od_en_33

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_33_pull_en_33

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_33_pull_select_33

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_33_keeper_en_33

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_33_schmitt_en_33

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_33_od_en_33

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_33_slew_rate_33

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_33_drive_strength_33

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_34_invert_34

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_34_virtual_od_en_34

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_34_pull_en_34

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_34_pull_select_34

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_34_keeper_en_34

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_34_schmitt_en_34

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_34_od_en_34

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_34_slew_rate_34

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_34_drive_strength_34

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_35_invert_35

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_35_virtual_od_en_35

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_35_pull_en_35

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_35_pull_select_35

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_35_keeper_en_35

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_35_schmitt_en_35

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_35_od_en_35

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_35_slew_rate_35

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_35_drive_strength_35

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_36_invert_36

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_36_virtual_od_en_36

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_36_pull_en_36

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_36_pull_select_36

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_36_keeper_en_36

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_36_schmitt_en_36

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_36_od_en_36

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_36_slew_rate_36

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_36_drive_strength_36

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_37_invert_37

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_37_virtual_od_en_37

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_37_pull_en_37

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_37_pull_select_37

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_37_keeper_en_37

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_37_schmitt_en_37

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_37_od_en_37

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_37_slew_rate_37

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_37_drive_strength_37

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_38_invert_38

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_38_virtual_od_en_38

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_38_pull_en_38

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_38_pull_select_38

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_38_keeper_en_38

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_38_schmitt_en_38

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_38_od_en_38

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_38_slew_rate_38

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_38_drive_strength_38

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_39_invert_39

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_39_virtual_od_en_39

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_39_pull_en_39

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_39_pull_select_39

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_39_keeper_en_39

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_39_schmitt_en_39

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_39_od_en_39

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_39_slew_rate_39

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_39_drive_strength_39

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_40_invert_40

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_40_virtual_od_en_40

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_40_pull_en_40

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_40_pull_select_40

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_40_keeper_en_40

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_40_schmitt_en_40

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_40_od_en_40

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_40_slew_rate_40

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_40_drive_strength_40

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_41_invert_41

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_41_virtual_od_en_41

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_41_pull_en_41

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_41_pull_select_41

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_41_keeper_en_41

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_41_schmitt_en_41

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_41_od_en_41

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_41_slew_rate_41

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_41_drive_strength_41

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_42_invert_42

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_42_virtual_od_en_42

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_42_pull_en_42

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_42_pull_select_42

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_42_keeper_en_42

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_42_schmitt_en_42

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_42_od_en_42

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_42_slew_rate_42

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_42_drive_strength_42

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_43_invert_43

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_43_virtual_od_en_43

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_43_pull_en_43

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_43_pull_select_43

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_43_keeper_en_43

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_43_schmitt_en_43

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_43_od_en_43

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_43_slew_rate_43

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_43_drive_strength_43

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_44_invert_44

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_44_virtual_od_en_44

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_44_pull_en_44

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_44_pull_select_44

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_44_keeper_en_44

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_44_schmitt_en_44

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_44_od_en_44

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_44_slew_rate_44

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_44_drive_strength_44

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_45_invert_45

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_45_virtual_od_en_45

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_45_pull_en_45

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_45_pull_select_45

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_45_keeper_en_45

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_45_schmitt_en_45

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_45_od_en_45

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_45_slew_rate_45

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_45_drive_strength_45

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_46_invert_46

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_46_virtual_od_en_46

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_46_pull_en_46

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_46_pull_select_46

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_46_keeper_en_46

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_46_schmitt_en_46

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_46_od_en_46

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_46_slew_rate_46

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_46_drive_strength_46

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_0_invert_0

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_0_virtual_od_en_0

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_0_pull_en_0

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_0_pull_select_0

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_0_keeper_en_0

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_0_schmitt_en_0

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_0_od_en_0

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_0_slew_rate_0

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_0_drive_strength_0

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_1_invert_1

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_1_virtual_od_en_1

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_1_pull_en_1

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_1_pull_select_1

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_1_keeper_en_1

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_1_schmitt_en_1

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_1_od_en_1

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_1_slew_rate_1

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_1_drive_strength_1

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_2_invert_2

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_2_virtual_od_en_2

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_2_pull_en_2

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_2_pull_select_2

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_2_keeper_en_2

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_2_schmitt_en_2

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_2_od_en_2

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_2_slew_rate_2

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_2_drive_strength_2

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_3_invert_3

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_3_virtual_od_en_3

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_3_pull_en_3

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_3_pull_select_3

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_3_keeper_en_3

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_3_schmitt_en_3

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_3_od_en_3

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_3_slew_rate_3

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_3_drive_strength_3

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_4_invert_4

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_4_virtual_od_en_4

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_4_pull_en_4

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_4_pull_select_4

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_4_keeper_en_4

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_4_schmitt_en_4

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_4_od_en_4

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_4_slew_rate_4

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_4_drive_strength_4

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_5_invert_5

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_5_virtual_od_en_5

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_5_pull_en_5

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_5_pull_select_5

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_5_keeper_en_5

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_5_schmitt_en_5

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_5_od_en_5

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_5_slew_rate_5

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_5_drive_strength_5

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_6_invert_6

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_6_virtual_od_en_6

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_6_pull_en_6

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_6_pull_select_6

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_6_keeper_en_6

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_6_schmitt_en_6

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_6_od_en_6

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_6_slew_rate_6

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_6_drive_strength_6

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_7_invert_7

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_7_virtual_od_en_7

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_7_pull_en_7

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_7_pull_select_7

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_7_keeper_en_7

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_7_schmitt_en_7

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_7_od_en_7

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_7_slew_rate_7

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_7_drive_strength_7

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_8_invert_8

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_8_virtual_od_en_8

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_8_pull_en_8

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_8_pull_select_8

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_8_keeper_en_8

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_8_schmitt_en_8

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_8_od_en_8

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_8_slew_rate_8

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_8_drive_strength_8

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_9_invert_9

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_9_virtual_od_en_9

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_9_pull_en_9

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_9_pull_select_9

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_9_keeper_en_9

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_9_schmitt_en_9

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_9_od_en_9

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_9_slew_rate_9

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_9_drive_strength_9

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_10_invert_10

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_10_virtual_od_en_10

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_10_pull_en_10

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_10_pull_select_10

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_10_keeper_en_10

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_10_schmitt_en_10

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_10_od_en_10

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_10_slew_rate_10

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_10_drive_strength_10

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1