Unified Coverage Report :: Module :: xbar_main

Module : xbar_main

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
33.00			33.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_main_0.1/rtl/autogen/xbar_main.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_main	33.00			33.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_main

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
33.00			33.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
33.00			33.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.37	55.20		73.92			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_main

	Total	Covered	Percent
Totals	550	144	26.18
Total Bits	6824	2252	33.00
Total Bits 0->1	3412	1126	33.00
Total Bits 1->0	3412	1126	33.00

Ports	550	144	26.18
Port Bits	6824	2252	33.00
Port Bits 0->1	3412	1126	33.00
Port Bits 1->0	3412	1126	33.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_main_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_fixed_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_usb_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_spi_host0_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_spi_host1_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_main_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_fixed_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_usb_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_spi_host0_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_spi_host1_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.d_ready	No	No		No		INPUT
tl_rv_core_ibex__corei_i.a_user.data_intg[6:0]	No	No		No		INPUT
tl_rv_core_ibex__corei_i.a_user.cmd_intg[6:0]	No	No		No		INPUT
tl_rv_core_ibex__corei_i.a_user.instr_type[3:0]	No	No		No		INPUT
tl_rv_core_ibex__corei_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_data[31:0]	No	No		No		INPUT
tl_rv_core_ibex__corei_i.a_mask[3:0]	No	No		No		INPUT
tl_rv_core_ibex__corei_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_source[5:0]	No	No		No		INPUT
tl_rv_core_ibex__corei_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_size[1:0]	No	No		No		INPUT
tl_rv_core_ibex__corei_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_opcode[2:0]	No	No		No		INPUT
tl_rv_core_ibex__corei_i.a_valid	No	No		No		INPUT
tl_rv_core_ibex__corei_o.a_ready	No	No		No		OUTPUT
tl_rv_core_ibex__corei_o.d_error	No	No		No		OUTPUT
tl_rv_core_ibex__corei_o.d_user.data_intg[6:0]	Yes	Yes	T1,T9,T10	Yes	T1,T9,T10	OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[0]	No	No		No		OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[1]	Yes	Yes	*T1,*T9,*T10	Yes	T1,T9,T10	OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[2]	No	No		No		OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[4:3]	Yes	Yes	T1,T9,T10	Yes	T1,T9,T10	OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[6:5]	No	No		No		OUTPUT
tl_rv_core_ibex__corei_o.d_data[31:0]	Yes	Yes	T1,T9,T10	Yes	T1,T9,T10	OUTPUT
tl_rv_core_ibex__corei_o.d_sink	No	No		No		OUTPUT
tl_rv_core_ibex__corei_o.d_source[5:0]	No	No		No		OUTPUT
tl_rv_core_ibex__corei_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_size[0]	No	No		No		OUTPUT
tl_rv_core_ibex__corei_o.d_size[1]	Yes	Yes	T1,T9,T10	Yes	T1,T9,T10	OUTPUT
tl_rv_core_ibex__corei_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[0]	Yes	Yes	*T1,*T9,*T10	Yes	T1,T9,T10	OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_valid	No	No		No		OUTPUT
tl_rv_core_ibex__cored_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T11	Yes	T1,T2,T11	INPUT
tl_rv_core_ibex__cored_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_mask[3:0]	Yes	Yes	T1,T2,T11	Yes	T1,T2,T11	INPUT
tl_rv_core_ibex__cored_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_source[5:0]	Yes	Yes	T1,T2,T9	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_size[1:0]	Yes	Yes	T1,T2,T11	Yes	T1,T2,T11	INPUT
tl_rv_core_ibex__cored_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_opcode[1]	No	No		No		INPUT
tl_rv_core_ibex__cored_i.a_opcode[2]	Yes	Yes	T1,T2,T11	Yes	T1,T2,T11	INPUT
tl_rv_core_ibex__cored_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_error	No	No		No		OUTPUT
tl_rv_core_ibex__cored_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[2]	No	No		No		OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[5:3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_rv_core_ibex__cored_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_sink	No	No		No		OUTPUT
tl_rv_core_ibex__cored_o.d_source[5:0]	Yes	Yes	*T1,*T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_size[1:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_rv_dm__sba_i.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_source[5:0]	No	No		No		INPUT
tl_rv_dm__sba_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_size[0]	No	No		No		INPUT
tl_rv_dm__sba_i.a_size[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_opcode[1:0]	No	No		No		INPUT
tl_rv_dm__sba_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_o.d_error	No	No		No		OUTPUT
tl_rv_dm__sba_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[2]	No	No		No		OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[5:3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_rv_dm__sba_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_o.d_sink	No	No		No		OUTPUT
tl_rv_dm__sba_o.d_source[5:0]	No	No		No		OUTPUT
tl_rv_dm__sba_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_size[0]	No	No		No		OUTPUT
tl_rv_dm__sba_o.d_size[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__regs_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__regs_o.a_user.data_intg[6:0]	Yes	Yes	T2	Yes	T2	OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[0]	Yes	Yes	*T2	Yes	T2	OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[1]	No	No		No		OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[4:2]	Yes	Yes	T2	Yes	T2	OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[5]	No	No		No		OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[6]	Yes	Yes	T2	Yes	T2	OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[0]	Yes	Yes	*T2	Yes	T2	OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[3]	Yes	Yes	T2	Yes	T2	OUTPUT
tl_rv_dm__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_data[6:0]	Yes	Yes	T2	Yes	T2	OUTPUT
tl_rv_dm__regs_o.a_data[7]	No	No		No		OUTPUT
tl_rv_dm__regs_o.a_data[10:8]	Yes	Yes	T2	Yes	T2	OUTPUT
tl_rv_dm__regs_o.a_data[12:11]	No	No		No		OUTPUT
tl_rv_dm__regs_o.a_data[13]	Yes	Yes	*T2	Yes	T2	OUTPUT
tl_rv_dm__regs_o.a_data[14]	No	No		No		OUTPUT
tl_rv_dm__regs_o.a_data[17:15]	Yes	Yes	T2	Yes	T2	OUTPUT
tl_rv_dm__regs_o.a_data[18]	No	No		No		OUTPUT
tl_rv_dm__regs_o.a_data[21:19]	Yes	Yes	T2	Yes	T2	OUTPUT
tl_rv_dm__regs_o.a_data[22]	No	No		No		OUTPUT
tl_rv_dm__regs_o.a_data[24:23]	Yes	Yes	T2	Yes	T2	OUTPUT
tl_rv_dm__regs_o.a_data[25]	No	No		No		OUTPUT
tl_rv_dm__regs_o.a_data[28:26]	Yes	Yes	T2	Yes	T2	OUTPUT
tl_rv_dm__regs_o.a_data[30:29]	No	No		No		OUTPUT
tl_rv_dm__regs_o.a_data[31]	Yes	Yes	T2	Yes	T2	OUTPUT
tl_rv_dm__regs_o.a_mask[3:0]	Yes	Yes	T2	Yes	T2	OUTPUT
tl_rv_dm__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_source[0]	Yes	Yes	*T2	Yes	T2	OUTPUT
tl_rv_dm__regs_o.a_source[5:1]	No	No		No		OUTPUT
tl_rv_dm__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_size[0]	No	No		No		OUTPUT
tl_rv_dm__regs_o.a_size[1]	Yes	Yes	T2	Yes	T2	OUTPUT
tl_rv_dm__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_rv_dm__regs_o.a_opcode[2]	Yes	Yes	T2	Yes	T2	OUTPUT
tl_rv_dm__regs_o.a_valid	Yes	Yes	T2	Yes	T2	OUTPUT
tl_rv_dm__regs_i.a_ready	Yes	Yes	T2	Yes	T2	INPUT
tl_rv_dm__regs_i.d_error	No	No		No		INPUT
tl_rv_dm__regs_i.d_user.data_intg[6:0]	No	No		No		INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[1:0]	Yes	Yes	T2	Yes	T2	INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[5:4]	Yes	Yes	T2	Yes	T2	INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_rv_dm__regs_i.d_data[31:0]	Yes	Yes	T2	Yes	T2	INPUT
tl_rv_dm__regs_i.d_sink	No	No		No		INPUT
tl_rv_dm__regs_i.d_source[0]	Yes	Yes	*T2	Yes	T2	INPUT
tl_rv_dm__regs_i.d_source[5:1]	No	No		No		INPUT
tl_rv_dm__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_size[0]	No	No		No		INPUT
tl_rv_dm__regs_i.d_size[1]	Yes	Yes	T2	Yes	T2	INPUT
tl_rv_dm__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_opcode[0]	Yes	Yes	*T2	Yes	T2	INPUT
tl_rv_dm__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_valid	Yes	Yes	T2	Yes	T2	INPUT
tl_rv_dm__mem_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__mem_o.a_user.data_intg[6:0]	Yes	Yes	T2	Yes	T2	OUTPUT
tl_rv_dm__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T2	Yes	T2	OUTPUT
tl_rv_dm__mem_o.a_user.instr_type[0]	Yes	Yes	*T2	Yes	T2	OUTPUT
tl_rv_dm__mem_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_rv_dm__mem_o.a_user.instr_type[3]	Yes	Yes	T2	Yes	T2	OUTPUT
tl_rv_dm__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_data[31:0]	Yes	Yes	T2	Yes	T2	OUTPUT
tl_rv_dm__mem_o.a_mask[3:0]	Yes	Yes	T2	Yes	T2	OUTPUT
tl_rv_dm__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_source[0]	No	No		No		OUTPUT
tl_rv_dm__mem_o.a_source[1]	Yes	Yes	*T2	Yes	T2	OUTPUT
tl_rv_dm__mem_o.a_source[5:2]	No	No		No		OUTPUT
tl_rv_dm__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_size[0]	No	No		No		OUTPUT
tl_rv_dm__mem_o.a_size[1]	Yes	Yes	T2	Yes	T2	OUTPUT
tl_rv_dm__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_rv_dm__mem_o.a_opcode[2]	Yes	Yes	T2	Yes	T2	OUTPUT
tl_rv_dm__mem_o.a_valid	Yes	Yes	T2	Yes	T2	OUTPUT
tl_rv_dm__mem_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_dm__mem_i.d_error	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_dm__mem_i.d_user.data_intg[6:0]	No	No		No		INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[2:0]	Yes	Yes	T2,*T1,*T3	Yes	T2,T1,T3	INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[3]	No	No		No		INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[5:4]	Yes	Yes	T2,*T1,*T3	Yes	T2,T1,T3	INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_rv_dm__mem_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_dm__mem_i.d_sink	No	No		No		INPUT
tl_rv_dm__mem_i.d_source[0]	No	No		No		INPUT
tl_rv_dm__mem_i.d_source[1]	Yes	Yes	*T2	Yes	T2	INPUT
tl_rv_dm__mem_i.d_source[5:2]	No	No		No		INPUT
tl_rv_dm__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_size[0]	No	No		No		INPUT
tl_rv_dm__mem_i.d_size[1]	Yes	Yes	T2	Yes	T2	INPUT
tl_rv_dm__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_dm__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_valid	Yes	Yes	T2	Yes	T2	INPUT
tl_rom_ctrl__rom_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.data_intg[6:0]	Yes	Yes	T1,T9,T10	Yes	T1,T9,T10	OUTPUT
tl_rom_ctrl__rom_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T9,T10	Yes	T1,T9,T10	OUTPUT
tl_rom_ctrl__rom_o.a_user.instr_type[0]	Yes	Yes	*T1,*T9,*T10	Yes	T1,T9,T10	OUTPUT
tl_rom_ctrl__rom_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_rom_ctrl__rom_o.a_user.instr_type[3]	Yes	Yes	T1,T9,T10	Yes	T1,T9,T10	OUTPUT
tl_rom_ctrl__rom_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_data[31:0]	Yes	Yes	T1,T9,T10	Yes	T1,T9,T10	OUTPUT
tl_rom_ctrl__rom_o.a_mask[3:0]	Yes	Yes	T1,T9,T10	Yes	T1,T9,T10	OUTPUT
tl_rom_ctrl__rom_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_source[0]	No	No		No		OUTPUT
tl_rom_ctrl__rom_o.a_source[1]	Yes	Yes	*T1,*T9,*T10	Yes	T1,T9,T10	OUTPUT
tl_rom_ctrl__rom_o.a_source[5:2]	No	No		No		OUTPUT
tl_rom_ctrl__rom_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_size[0]	No	No		No		OUTPUT
tl_rom_ctrl__rom_o.a_size[1]	Yes	Yes	T1,T9,T10	Yes	T1,T9,T10	OUTPUT
tl_rom_ctrl__rom_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_rom_ctrl__rom_o.a_opcode[2]	Yes	Yes	T1,T9,T10	Yes	T1,T9,T10	OUTPUT
tl_rom_ctrl__rom_o.a_valid	Yes	Yes	T1,T9,T10	Yes	T1,T9,T10	OUTPUT
tl_rom_ctrl__rom_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_error	No	No		No		INPUT
tl_rom_ctrl__rom_i.d_user.data_intg[6:0]	Yes	Yes	T1,T9,T10	Yes	T1,T9,T10	INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[1:0]	Yes	Yes	T1,T9,T10	Yes	T1,T9,T10	INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[4]	Yes	Yes	*T1,*T9,*T10	Yes	T1,T9,T10	INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[6:5]	No	No		No		INPUT
tl_rom_ctrl__rom_i.d_data[31:0]	Yes	Yes	T1,T9,T10	Yes	T1,T9,T10	INPUT
tl_rom_ctrl__rom_i.d_sink	No	No		No		INPUT
tl_rom_ctrl__rom_i.d_source[0]	No	No		No		INPUT
tl_rom_ctrl__rom_i.d_source[1]	Yes	Yes	*T1,*T9,*T10	Yes	T1,T9,T10	INPUT
tl_rom_ctrl__rom_i.d_source[5:2]	No	No		No		INPUT
tl_rom_ctrl__rom_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_size[0]	No	No		No		INPUT
tl_rom_ctrl__rom_i.d_size[1]	Yes	Yes	T1,T9,T10	Yes	T1,T9,T10	INPUT
tl_rom_ctrl__rom_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_opcode[0]	No	No		No		INPUT
tl_rom_ctrl__rom_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_valid	Yes	Yes	T1,T9,T10	Yes	T1,T9,T10	INPUT
tl_rom_ctrl__regs_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[6:0]	Yes	Yes	T2	Yes	T2	OUTPUT
tl_rom_ctrl__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T2	Yes	T2	OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[0]	Yes	Yes	*T2	Yes	T2	OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[3]	Yes	Yes	T2	Yes	T2	OUTPUT
tl_rom_ctrl__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_data[31:0]	Yes	Yes	T2	Yes	T2	OUTPUT
tl_rom_ctrl__regs_o.a_mask[3:0]	Yes	Yes	T2	Yes	T2	OUTPUT
tl_rom_ctrl__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_source[0]	Yes	Yes	*T2	Yes	T2	OUTPUT
tl_rom_ctrl__regs_o.a_source[5:1]	No	No		No		OUTPUT
tl_rom_ctrl__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_size[0]	No	No		No		OUTPUT
tl_rom_ctrl__regs_o.a_size[1]	Yes	Yes	T2	Yes	T2	OUTPUT
tl_rom_ctrl__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_rom_ctrl__regs_o.a_opcode[2]	Yes	Yes	T2	Yes	T2	OUTPUT
tl_rom_ctrl__regs_o.a_valid	Yes	Yes	T2	Yes	T2	OUTPUT
tl_rom_ctrl__regs_i.a_ready	Yes	Yes	T2	Yes	T2	INPUT
tl_rom_ctrl__regs_i.d_error	No	No		No		INPUT
tl_rom_ctrl__regs_i.d_user.data_intg[6:0]	No	No		No		INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[1:0]	Yes	Yes	T2	Yes	T2	INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[5:4]	Yes	Yes	T2	Yes	T2	INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_rom_ctrl__regs_i.d_data[31:0]	Yes	Yes	T2	Yes	T2	INPUT
tl_rom_ctrl__regs_i.d_sink	No	No		No		INPUT
tl_rom_ctrl__regs_i.d_source[0]	Yes	Yes	*T2	Yes	T2	INPUT
tl_rom_ctrl__regs_i.d_source[5:1]	No	No		No		INPUT
tl_rom_ctrl__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_size[0]	No	No		No		INPUT
tl_rom_ctrl__regs_i.d_size[1]	Yes	Yes	T2	Yes	T2	INPUT
tl_rom_ctrl__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_opcode[0]	Yes	Yes	*T2	Yes	T2	INPUT
tl_rom_ctrl__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_valid	Yes	Yes	T2	Yes	T2	INPUT
tl_peri_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_peri_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_source[5:0]	Yes	Yes	*T1,*T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_size[1:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_opcode[1]	No	No		No		OUTPUT
tl_peri_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_error	No	No		No		INPUT
tl_peri_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_user.rsp_intg[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_user.rsp_intg[2]	No	No		No		INPUT
tl_peri_i.d_user.rsp_intg[5:3]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_peri_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_peri_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_sink	No	No		No		INPUT
tl_peri_i.d_source[5:0]	Yes	Yes	*T1,*T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_size[1:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_peri_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_spi_host0_o.d_ready	No	No		No		OUTPUT
tl_spi_host0_o.a_user.data_intg[6:0]	No	No		No		OUTPUT
tl_spi_host0_o.a_user.cmd_intg[6:0]	No	No		No		OUTPUT
tl_spi_host0_o.a_user.instr_type[3:0]	No	No		No		OUTPUT
tl_spi_host0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_data[31:0]	No	No		No		OUTPUT
tl_spi_host0_o.a_mask[3:0]	No	No		No		OUTPUT
tl_spi_host0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_source[5:0]	No	No		No		OUTPUT
tl_spi_host0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_size[1:0]	No	No		No		OUTPUT
tl_spi_host0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_opcode[2:0]	No	No		No		OUTPUT
tl_spi_host0_o.a_valid	No	No		No		OUTPUT
tl_spi_host0_i.a_ready	No	No		No		INPUT
tl_spi_host0_i.d_error	No	No		No		INPUT
tl_spi_host0_i.d_user.data_intg[6:0]	No	No		No		INPUT
tl_spi_host0_i.d_user.rsp_intg[6:0]	No	No		No		INPUT
tl_spi_host0_i.d_data[31:0]	No	No		No		INPUT
tl_spi_host0_i.d_sink	No	No		No		INPUT
tl_spi_host0_i.d_source[5:0]	No	No		No		INPUT
tl_spi_host0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_size[1:0]	No	No		No		INPUT
tl_spi_host0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_opcode[0]	No	No		No		INPUT
tl_spi_host0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_valid	No	No		No		INPUT
tl_spi_host1_o.d_ready	No	No		No		OUTPUT
tl_spi_host1_o.a_user.data_intg[6:0]	No	No		No		OUTPUT
tl_spi_host1_o.a_user.cmd_intg[6:0]	No	No		No		OUTPUT
tl_spi_host1_o.a_user.instr_type[3:0]	No	No		No		OUTPUT
tl_spi_host1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_data[31:0]	No	No		No		OUTPUT
tl_spi_host1_o.a_mask[3:0]	No	No		No		OUTPUT
tl_spi_host1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_source[5:0]	No	No		No		OUTPUT
tl_spi_host1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_size[1:0]	No	No		No		OUTPUT
tl_spi_host1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_opcode[2:0]	No	No		No		OUTPUT
tl_spi_host1_o.a_valid	No	No		No		OUTPUT
tl_spi_host1_i.a_ready	No	No		No		INPUT
tl_spi_host1_i.d_error	No	No		No		INPUT
tl_spi_host1_i.d_user.data_intg[6:0]	No	No		No		INPUT
tl_spi_host1_i.d_user.rsp_intg[6:0]	No	No		No		INPUT
tl_spi_host1_i.d_data[31:0]	No	No		No		INPUT
tl_spi_host1_i.d_sink	No	No		No		INPUT
tl_spi_host1_i.d_source[5:0]	No	No		No		INPUT
tl_spi_host1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_size[1:0]	No	No		No		INPUT
tl_spi_host1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_opcode[0]	No	No		No		INPUT
tl_spi_host1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_valid	No	No		No		INPUT
tl_usbdev_o.d_ready	No	No		No		OUTPUT
tl_usbdev_o.a_user.data_intg[6:0]	No	No		No		OUTPUT
tl_usbdev_o.a_user.cmd_intg[6:0]	No	No		No		OUTPUT
tl_usbdev_o.a_user.instr_type[3:0]	No	No		No		OUTPUT
tl_usbdev_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_data[31:0]	No	No		No		OUTPUT
tl_usbdev_o.a_mask[3:0]	No	No		No		OUTPUT
tl_usbdev_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_source[5:0]	No	No		No		OUTPUT
tl_usbdev_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_size[1:0]	No	No		No		OUTPUT
tl_usbdev_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_opcode[2:0]	No	No		No		OUTPUT
tl_usbdev_o.a_valid	No	No		No		OUTPUT
tl_usbdev_i.a_ready	No	No		No		INPUT
tl_usbdev_i.d_error	No	No		No		INPUT
tl_usbdev_i.d_user.data_intg[6:0]	No	No		No		INPUT
tl_usbdev_i.d_user.rsp_intg[6:0]	No	No		No		INPUT
tl_usbdev_i.d_data[31:0]	No	No		No		INPUT
tl_usbdev_i.d_sink	No	No		No		INPUT
tl_usbdev_i.d_source[5:0]	No	No		No		INPUT
tl_usbdev_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_size[1:0]	No	No		No		INPUT
tl_usbdev_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_opcode[0]	No	No		No		INPUT
tl_usbdev_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_valid	No	No		No		INPUT
tl_flash_ctrl__core_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.data_intg[6:0]	No	No		No		OUTPUT
tl_flash_ctrl__core_o.a_user.cmd_intg[6:0]	No	No		No		OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[3:0]	No	No		No		OUTPUT
tl_flash_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_data[31:0]	No	No		No		OUTPUT
tl_flash_ctrl__core_o.a_mask[3:0]	No	No		No		OUTPUT
tl_flash_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_source[5:0]	No	No		No		OUTPUT
tl_flash_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_size[1:0]	No	No		No		OUTPUT
tl_flash_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_opcode[2:0]	No	No		No		OUTPUT
tl_flash_ctrl__core_o.a_valid	No	No		No		OUTPUT
tl_flash_ctrl__core_i.a_ready	No	No		No		INPUT
tl_flash_ctrl__core_i.d_error	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_user.data_intg[6:0]	No	No		No		INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[6:3]	No	No		No		INPUT
tl_flash_ctrl__core_i.d_data[31:0]	No	No		No		INPUT
tl_flash_ctrl__core_i.d_sink	No	No		No		INPUT
tl_flash_ctrl__core_i.d_source[5:0]	No	No		No		INPUT
tl_flash_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_size[1:0]	No	No		No		INPUT
tl_flash_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_opcode[0]	No	No		No		INPUT
tl_flash_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_valid	No	No		No		INPUT
tl_flash_ctrl__prim_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__prim_o.a_user.data_intg[6:0]	No	No		No		OUTPUT
tl_flash_ctrl__prim_o.a_user.cmd_intg[6:0]	No	No		No		OUTPUT
tl_flash_ctrl__prim_o.a_user.instr_type[3:0]	No	No		No		OUTPUT
tl_flash_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_data[31:0]	No	No		No		OUTPUT
tl_flash_ctrl__prim_o.a_mask[3:0]	No	No		No		OUTPUT
tl_flash_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_source[5:0]	No	No		No		OUTPUT
tl_flash_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_size[1:0]	No	No		No		OUTPUT
tl_flash_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_opcode[2:0]	No	No		No		OUTPUT
tl_flash_ctrl__prim_o.a_valid	No	No		No		OUTPUT
tl_flash_ctrl__prim_i.a_ready	No	No		No		INPUT
tl_flash_ctrl__prim_i.d_error	No	No		No		INPUT
tl_flash_ctrl__prim_i.d_user.data_intg[6:0]	No	No		No		INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[6:0]	No	No		No		INPUT
tl_flash_ctrl__prim_i.d_data[31:0]	No	No		No		INPUT
tl_flash_ctrl__prim_i.d_sink	No	No		No		INPUT
tl_flash_ctrl__prim_i.d_source[5:0]	No	No		No		INPUT
tl_flash_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_size[1:0]	No	No		No		INPUT
tl_flash_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_opcode[0]	No	No		No		INPUT
tl_flash_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_valid	No	No		No		INPUT
tl_flash_ctrl__mem_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.data_intg[6:0]	No	No		No		OUTPUT
tl_flash_ctrl__mem_o.a_user.cmd_intg[6:0]	No	No		No		OUTPUT
tl_flash_ctrl__mem_o.a_user.instr_type[3:0]	No	No		No		OUTPUT
tl_flash_ctrl__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_data[31:0]	No	No		No		OUTPUT
tl_flash_ctrl__mem_o.a_mask[3:0]	No	No		No		OUTPUT
tl_flash_ctrl__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_source[5:0]	No	No		No		OUTPUT
tl_flash_ctrl__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_size[1:0]	No	No		No		OUTPUT
tl_flash_ctrl__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_opcode[2:0]	No	No		No		OUTPUT
tl_flash_ctrl__mem_o.a_valid	No	No		No		OUTPUT
tl_flash_ctrl__mem_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_error	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_user.data_intg[6:0]	No	No		No		INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[6:3]	No	No		No		INPUT
tl_flash_ctrl__mem_i.d_data[31:0]	No	No		No		INPUT
tl_flash_ctrl__mem_i.d_sink	No	No		No		INPUT
tl_flash_ctrl__mem_i.d_source[5:0]	No	No		No		INPUT
tl_flash_ctrl__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_size[1:0]	No	No		No		INPUT
tl_flash_ctrl__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_opcode[0]	No	No		No		INPUT
tl_flash_ctrl__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_valid	No	No		No		INPUT
tl_hmac_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_hmac_o.a_user.data_intg[6:0]	No	No		No		OUTPUT
tl_hmac_o.a_user.cmd_intg[6:0]	No	No		No		OUTPUT
tl_hmac_o.a_user.instr_type[3:0]	No	No		No		OUTPUT
tl_hmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_data[31:0]	No	No		No		OUTPUT
tl_hmac_o.a_mask[3:0]	No	No		No		OUTPUT
tl_hmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_source[5:0]	No	No		No		OUTPUT
tl_hmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_size[1:0]	No	No		No		OUTPUT
tl_hmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_opcode[2:0]	No	No		No		OUTPUT
tl_hmac_o.a_valid	No	No		No		OUTPUT
tl_hmac_i.a_ready	No	No		No		INPUT
tl_hmac_i.d_error	No	No		No		INPUT
tl_hmac_i.d_user.data_intg[6:0]	No	No		No		INPUT
tl_hmac_i.d_user.rsp_intg[6:0]	No	No		No		INPUT
tl_hmac_i.d_data[31:0]	No	No		No		INPUT
tl_hmac_i.d_sink	No	No		No		INPUT
tl_hmac_i.d_source[5:0]	No	No		No		INPUT
tl_hmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_size[1:0]	No	No		No		INPUT
tl_hmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_opcode[0]	No	No		No		INPUT
tl_hmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_valid	No	No		No		INPUT
tl_kmac_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_kmac_o.a_user.data_intg[6:0]	No	No		No		OUTPUT
tl_kmac_o.a_user.cmd_intg[6:0]	No	No		No		OUTPUT
tl_kmac_o.a_user.instr_type[3:0]	No	No		No		OUTPUT
tl_kmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_data[31:0]	No	No		No		OUTPUT
tl_kmac_o.a_mask[3:0]	No	No		No		OUTPUT
tl_kmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_source[5:0]	No	No		No		OUTPUT
tl_kmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_size[1:0]	No	No		No		OUTPUT
tl_kmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_opcode[2:0]	No	No		No		OUTPUT
tl_kmac_o.a_valid	No	No		No		OUTPUT
tl_kmac_i.a_ready	No	No		No		INPUT
tl_kmac_i.d_error	No	No		No		INPUT
tl_kmac_i.d_user.data_intg[6:0]	No	No		No		INPUT
tl_kmac_i.d_user.rsp_intg[6:0]	No	No		No		INPUT
tl_kmac_i.d_data[31:0]	No	No		No		INPUT
tl_kmac_i.d_sink	No	No		No		INPUT
tl_kmac_i.d_source[5:0]	No	No		No		INPUT
tl_kmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_size[1:0]	No	No		No		INPUT
tl_kmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_opcode[0]	No	No		No		INPUT
tl_kmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_valid	No	No		No		INPUT
tl_aes_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aes_o.a_user.data_intg[6:0]	No	No		No		OUTPUT
tl_aes_o.a_user.cmd_intg[6:0]	No	No		No		OUTPUT
tl_aes_o.a_user.instr_type[3:0]	No	No		No		OUTPUT
tl_aes_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_data[31:0]	No	No		No		OUTPUT
tl_aes_o.a_mask[3:0]	No	No		No		OUTPUT
tl_aes_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_source[5:0]	No	No		No		OUTPUT
tl_aes_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_size[1:0]	No	No		No		OUTPUT
tl_aes_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_opcode[2:0]	No	No		No		OUTPUT
tl_aes_o.a_valid	No	No		No		OUTPUT
tl_aes_i.a_ready	No	No		No		INPUT
tl_aes_i.d_error	No	No		No		INPUT
tl_aes_i.d_user.data_intg[6:0]	No	No		No		INPUT
tl_aes_i.d_user.rsp_intg[6:0]	No	No		No		INPUT
tl_aes_i.d_data[31:0]	No	No		No		INPUT
tl_aes_i.d_sink	No	No		No		INPUT
tl_aes_i.d_source[5:0]	No	No		No		INPUT
tl_aes_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_size[1:0]	No	No		No		INPUT
tl_aes_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_opcode[0]	No	No		No		INPUT
tl_aes_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_valid	No	No		No		INPUT
tl_entropy_src_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.data_intg[6:0]	No	No		No		OUTPUT
tl_entropy_src_o.a_user.cmd_intg[6:0]	No	No		No		OUTPUT
tl_entropy_src_o.a_user.instr_type[3:0]	No	No		No		OUTPUT
tl_entropy_src_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_data[31:0]	No	No		No		OUTPUT
tl_entropy_src_o.a_mask[3:0]	No	No		No		OUTPUT
tl_entropy_src_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_source[5:0]	No	No		No		OUTPUT
tl_entropy_src_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_size[1:0]	No	No		No		OUTPUT
tl_entropy_src_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_opcode[2:0]	No	No		No		OUTPUT
tl_entropy_src_o.a_valid	No	No		No		OUTPUT
tl_entropy_src_i.a_ready	No	No		No		INPUT
tl_entropy_src_i.d_error	No	No		No		INPUT
tl_entropy_src_i.d_user.data_intg[6:0]	No	No		No		INPUT
tl_entropy_src_i.d_user.rsp_intg[6:0]	No	No		No		INPUT
tl_entropy_src_i.d_data[31:0]	No	No		No		INPUT
tl_entropy_src_i.d_sink	No	No		No		INPUT
tl_entropy_src_i.d_source[5:0]	No	No		No		INPUT
tl_entropy_src_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_size[1:0]	No	No		No		INPUT
tl_entropy_src_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_opcode[0]	No	No		No		INPUT
tl_entropy_src_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_valid	No	No		No		INPUT
tl_csrng_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.data_intg[6:0]	No	No		No		OUTPUT
tl_csrng_o.a_user.cmd_intg[6:0]	No	No		No		OUTPUT
tl_csrng_o.a_user.instr_type[3:0]	No	No		No		OUTPUT
tl_csrng_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_data[31:0]	No	No		No		OUTPUT
tl_csrng_o.a_mask[3:0]	No	No		No		OUTPUT
tl_csrng_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_source[5:0]	No	No		No		OUTPUT
tl_csrng_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_size[1:0]	No	No		No		OUTPUT
tl_csrng_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_opcode[2:0]	No	No		No		OUTPUT
tl_csrng_o.a_valid	No	No		No		OUTPUT
tl_csrng_i.a_ready	No	No		No		INPUT
tl_csrng_i.d_error	No	No		No		INPUT
tl_csrng_i.d_user.data_intg[6:0]	No	No		No		INPUT
tl_csrng_i.d_user.rsp_intg[6:0]	No	No		No		INPUT
tl_csrng_i.d_data[31:0]	No	No		No		INPUT
tl_csrng_i.d_sink	No	No		No		INPUT
tl_csrng_i.d_source[5:0]	No	No		No		INPUT
tl_csrng_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_size[1:0]	No	No		No		INPUT
tl_csrng_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_opcode[0]	No	No		No		INPUT
tl_csrng_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_valid	No	No		No		INPUT
tl_edn0_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.data_intg[6:0]	No	No		No		OUTPUT
tl_edn0_o.a_user.cmd_intg[6:0]	No	No		No		OUTPUT
tl_edn0_o.a_user.instr_type[3:0]	No	No		No		OUTPUT
tl_edn0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_data[31:0]	No	No		No		OUTPUT
tl_edn0_o.a_mask[3:0]	No	No		No		OUTPUT
tl_edn0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_source[5:0]	No	No		No		OUTPUT
tl_edn0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_size[1:0]	No	No		No		OUTPUT
tl_edn0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_opcode[2:0]	No	No		No		OUTPUT
tl_edn0_o.a_valid	No	No		No		OUTPUT
tl_edn0_i.a_ready	No	No		No		INPUT
tl_edn0_i.d_error	No	No		No		INPUT
tl_edn0_i.d_user.data_intg[6:0]	No	No		No		INPUT
tl_edn0_i.d_user.rsp_intg[6:0]	No	No		No		INPUT
tl_edn0_i.d_data[31:0]	No	No		No		INPUT
tl_edn0_i.d_sink	No	No		No		INPUT
tl_edn0_i.d_source[5:0]	No	No		No		INPUT
tl_edn0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_size[1:0]	No	No		No		INPUT
tl_edn0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_opcode[0]	No	No		No		INPUT
tl_edn0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_valid	No	No		No		INPUT
tl_edn1_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn1_o.a_user.data_intg[6:0]	No	No		No		OUTPUT
tl_edn1_o.a_user.cmd_intg[6:0]	No	No		No		OUTPUT
tl_edn1_o.a_user.instr_type[3:0]	No	No		No		OUTPUT
tl_edn1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_data[31:0]	No	No		No		OUTPUT
tl_edn1_o.a_mask[3:0]	No	No		No		OUTPUT
tl_edn1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_source[5:0]	No	No		No		OUTPUT
tl_edn1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_size[1:0]	No	No		No		OUTPUT
tl_edn1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_opcode[2:0]	No	No		No		OUTPUT
tl_edn1_o.a_valid	No	No		No		OUTPUT
tl_edn1_i.a_ready	No	No		No		INPUT
tl_edn1_i.d_error	No	No		No		INPUT
tl_edn1_i.d_user.data_intg[6:0]	No	No		No		INPUT
tl_edn1_i.d_user.rsp_intg[6:0]	No	No		No		INPUT
tl_edn1_i.d_data[31:0]	No	No		No		INPUT
tl_edn1_i.d_sink	No	No		No		INPUT
tl_edn1_i.d_source[5:0]	No	No		No		INPUT
tl_edn1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_size[1:0]	No	No		No		INPUT
tl_edn1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_opcode[0]	No	No		No		INPUT
tl_edn1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_valid	No	No		No		INPUT
tl_rv_plic_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_plic_o.a_user.data_intg[6:0]	No	No		No		OUTPUT
tl_rv_plic_o.a_user.cmd_intg[6:0]	No	No		No		OUTPUT
tl_rv_plic_o.a_user.instr_type[3:0]	No	No		No		OUTPUT
tl_rv_plic_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_data[31:0]	No	No		No		OUTPUT
tl_rv_plic_o.a_mask[3:0]	No	No		No		OUTPUT
tl_rv_plic_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_source[5:0]	No	No		No		OUTPUT
tl_rv_plic_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_size[1:0]	No	No		No		OUTPUT
tl_rv_plic_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_opcode[2:0]	No	No		No		OUTPUT
tl_rv_plic_o.a_valid	No	No		No		OUTPUT
tl_rv_plic_i.a_ready	No	No		No		INPUT
tl_rv_plic_i.d_error	No	No		No		INPUT
tl_rv_plic_i.d_user.data_intg[6:0]	No	No		No		INPUT
tl_rv_plic_i.d_user.rsp_intg[6:0]	No	No		No		INPUT
tl_rv_plic_i.d_data[31:0]	No	No		No		INPUT
tl_rv_plic_i.d_sink	No	No		No		INPUT
tl_rv_plic_i.d_source[5:0]	No	No		No		INPUT
tl_rv_plic_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_size[1:0]	No	No		No		INPUT
tl_rv_plic_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_opcode[0]	No	No		No		INPUT
tl_rv_plic_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_valid	No	No		No		INPUT
tl_otbn_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otbn_o.a_user.data_intg[6:0]	Yes	Yes	T1,T3,T9	Yes	T1,T3,T9	OUTPUT
tl_otbn_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T3,T9	Yes	T1,T3,T9	OUTPUT
tl_otbn_o.a_user.instr_type[0]	Yes	Yes	*T1,*T3,*T9	Yes	T1,T3,T9	OUTPUT
tl_otbn_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_otbn_o.a_user.instr_type[3]	Yes	Yes	T1,T3,T9	Yes	T1,T3,T9	OUTPUT
tl_otbn_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_data[31:0]	Yes	Yes	T1,T9,T10	Yes	T1,T9,T10	OUTPUT
tl_otbn_o.a_mask[3:0]	Yes	Yes	T1,T3,T9	Yes	T1,T3,T9	OUTPUT
tl_otbn_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_source[0]	Yes	Yes	*T1,*T3,*T9	Yes	T1,T3,T9	OUTPUT
tl_otbn_o.a_source[5:1]	No	No		No		OUTPUT
tl_otbn_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_size[0]	No	No		No		OUTPUT
tl_otbn_o.a_size[1]	Yes	Yes	T1,T3,T9	Yes	T1,T3,T9	OUTPUT
tl_otbn_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_otbn_o.a_opcode[2]	Yes	Yes	T1,T3,T9	Yes	T1,T3,T9	OUTPUT
tl_otbn_o.a_valid	Yes	Yes	T1,T3,T9	Yes	T1,T3,T9	OUTPUT
tl_otbn_i.a_ready	Yes	Yes	T1,T3,T9	Yes	T1,T3,T9	INPUT
tl_otbn_i.d_error	No	No		No		INPUT
tl_otbn_i.d_user.data_intg[6:0]	Yes	Yes	T1,T3,T9	Yes	T1,T3,T9	INPUT
tl_otbn_i.d_user.rsp_intg[1:0]	Yes	Yes	T1,T3,T9	Yes	T1,T3,T9	INPUT
tl_otbn_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_otbn_i.d_user.rsp_intg[5:4]	Yes	Yes	T1,T3,T9	Yes	T1,T3,T9	INPUT
tl_otbn_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_otbn_i.d_data[31:0]	Yes	Yes	T1,T3,T9	Yes	T1,T3,T9	INPUT
tl_otbn_i.d_sink	No	No		No		INPUT
tl_otbn_i.d_source[0]	Yes	Yes	*T1,*T3,*T9	Yes	T1,T3,T9	INPUT
tl_otbn_i.d_source[5:1]	No	No		No		INPUT
tl_otbn_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_size[0]	No	No		No		INPUT
tl_otbn_i.d_size[1]	Yes	Yes	T1,T3,T9	Yes	T1,T3,T9	INPUT
tl_otbn_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_opcode[0]	Yes	Yes	*T1,*T3,*T9	Yes	T1,T3,T9	INPUT
tl_otbn_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_valid	Yes	Yes	T1,T3,T9	Yes	T1,T3,T9	INPUT
tl_keymgr_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_keymgr_o.a_user.data_intg[6:0]	No	No		No		OUTPUT
tl_keymgr_o.a_user.cmd_intg[6:0]	No	No		No		OUTPUT
tl_keymgr_o.a_user.instr_type[3:0]	No	No		No		OUTPUT
tl_keymgr_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_data[31:0]	No	No		No		OUTPUT
tl_keymgr_o.a_mask[3:0]	No	No		No		OUTPUT
tl_keymgr_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_source[5:0]	No	No		No		OUTPUT
tl_keymgr_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_size[1:0]	No	No		No		OUTPUT
tl_keymgr_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_opcode[2:0]	No	No		No		OUTPUT
tl_keymgr_o.a_valid	No	No		No		OUTPUT
tl_keymgr_i.a_ready	No	No		No		INPUT
tl_keymgr_i.d_error	No	No		No		INPUT
tl_keymgr_i.d_user.data_intg[6:0]	No	No		No		INPUT
tl_keymgr_i.d_user.rsp_intg[6:0]	No	No		No		INPUT
tl_keymgr_i.d_data[31:0]	No	No		No		INPUT
tl_keymgr_i.d_sink	No	No		No		INPUT
tl_keymgr_i.d_source[5:0]	No	No		No		INPUT
tl_keymgr_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_size[1:0]	No	No		No		INPUT
tl_keymgr_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_opcode[0]	No	No		No		INPUT
tl_keymgr_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_valid	No	No		No		INPUT
tl_rv_core_ibex__cfg_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.data_intg[6:0]	Yes	Yes	T2	Yes	T2	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[0]	Yes	Yes	*T2	Yes	T2	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[1]	No	No		No		OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[6:2]	Yes	Yes	T2	Yes	T2	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[0]	Yes	Yes	*T2	Yes	T2	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[3]	Yes	Yes	T2	Yes	T2	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_data[31:0]	Yes	Yes	T2	Yes	T2	OUTPUT
tl_rv_core_ibex__cfg_o.a_mask[3:0]	Yes	Yes	T2	Yes	T2	OUTPUT
tl_rv_core_ibex__cfg_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_source[0]	Yes	Yes	*T2	Yes	T2	OUTPUT
tl_rv_core_ibex__cfg_o.a_source[5:1]	No	No		No		OUTPUT
tl_rv_core_ibex__cfg_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_size[0]	No	No		No		OUTPUT
tl_rv_core_ibex__cfg_o.a_size[1]	Yes	Yes	T2	Yes	T2	OUTPUT
tl_rv_core_ibex__cfg_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[2]	Yes	Yes	T2	Yes	T2	OUTPUT
tl_rv_core_ibex__cfg_o.a_valid	Yes	Yes	T2	Yes	T2	OUTPUT
tl_rv_core_ibex__cfg_i.a_ready	Yes	Yes	T2	Yes	T2	INPUT
tl_rv_core_ibex__cfg_i.d_error	Yes	Yes	T2	Yes	T2	INPUT
tl_rv_core_ibex__cfg_i.d_user.data_intg[6:0]	Yes	Yes	T2	Yes	T2	INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[2:0]	Yes	Yes	T2	Yes	T2	INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[3]	No	No		No		INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[5:4]	Yes	Yes	T2	Yes	T2	INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_rv_core_ibex__cfg_i.d_data[31:0]	Yes	Yes	T2	Yes	T2	INPUT
tl_rv_core_ibex__cfg_i.d_sink	No	No		No		INPUT
tl_rv_core_ibex__cfg_i.d_source[0]	Yes	Yes	*T2	Yes	T2	INPUT
tl_rv_core_ibex__cfg_i.d_source[5:1]	No	No		No		INPUT
tl_rv_core_ibex__cfg_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_size[0]	No	No		No		INPUT
tl_rv_core_ibex__cfg_i.d_size[1]	Yes	Yes	T2	Yes	T2	INPUT
tl_rv_core_ibex__cfg_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_opcode[0]	Yes	Yes	*T2	Yes	T2	INPUT
tl_rv_core_ibex__cfg_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_valid	Yes	Yes	T2	Yes	T2	INPUT
tl_sram_ctrl_main__regs_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.data_intg[6:0]	No	No		No		OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[6:0]	No	No		No		OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[3:0]	No	No		No		OUTPUT
tl_sram_ctrl_main__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_data[31:0]	No	No		No		OUTPUT
tl_sram_ctrl_main__regs_o.a_mask[3:0]	No	No		No		OUTPUT
tl_sram_ctrl_main__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_source[5:0]	No	No		No		OUTPUT
tl_sram_ctrl_main__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_size[1:0]	No	No		No		OUTPUT
tl_sram_ctrl_main__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_opcode[2:0]	No	No		No		OUTPUT
tl_sram_ctrl_main__regs_o.a_valid	No	No		No		OUTPUT
tl_sram_ctrl_main__regs_i.a_ready	No	No		No		INPUT
tl_sram_ctrl_main__regs_i.d_error	No	No		No		INPUT
tl_sram_ctrl_main__regs_i.d_user.data_intg[6:0]	No	No		No		INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[6:0]	No	No		No		INPUT
tl_sram_ctrl_main__regs_i.d_data[31:0]	No	No		No		INPUT
tl_sram_ctrl_main__regs_i.d_sink	No	No		No		INPUT
tl_sram_ctrl_main__regs_i.d_source[5:0]	No	No		No		INPUT
tl_sram_ctrl_main__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_size[1:0]	No	No		No		INPUT
tl_sram_ctrl_main__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_opcode[0]	No	No		No		INPUT
tl_sram_ctrl_main__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_valid	No	No		No		INPUT
tl_sram_ctrl_main__ram_o.d_ready	Yes	Yes	T1,T9,T10	Yes	T1,T9,T10	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.data_intg[6:0]	Yes	Yes	T1,T9,T10	Yes	T1,T9,T10	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T9,T10	Yes	T1,T9,T10	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.instr_type[0]	Yes	Yes	*T1,*T9,*T10	Yes	T1,T9,T10	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_sram_ctrl_main__ram_o.a_user.instr_type[3]	Yes	Yes	T1,T9,T10	Yes	T1,T9,T10	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_data[31:0]	Yes	Yes	T1,T9,T10	Yes	T1,T9,T10	OUTPUT
tl_sram_ctrl_main__ram_o.a_mask[3:0]	Yes	Yes	T1,T9,T10	Yes	T1,T9,T10	OUTPUT
tl_sram_ctrl_main__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_source[0]	No	No		No		OUTPUT
tl_sram_ctrl_main__ram_o.a_source[1]	Yes	Yes	*T1,*T9,*T10	Yes	T1,T9,T10	OUTPUT
tl_sram_ctrl_main__ram_o.a_source[5:2]	No	No		No		OUTPUT
tl_sram_ctrl_main__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_size[0]	No	No		No		OUTPUT
tl_sram_ctrl_main__ram_o.a_size[1]	Yes	Yes	T1,T9,T10	Yes	T1,T9,T10	OUTPUT
tl_sram_ctrl_main__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[2]	Yes	Yes	T1,T9,T10	Yes	T1,T9,T10	OUTPUT
tl_sram_ctrl_main__ram_o.a_valid	Yes	Yes	T1,T9,T10	Yes	T1,T9,T10	OUTPUT
tl_sram_ctrl_main__ram_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_error	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_user.data_intg[6:0]	Yes	Yes	T1,T9,T10	Yes	T1,T9,T10	INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[3]	No	No		No		INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[5:4]	Yes	Yes	T1,T9,T10	Yes	T1,T9,T10	INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_sram_ctrl_main__ram_i.d_data[31:0]	Yes	Yes	T1,T9,T10	Yes	T1,T9,T10	INPUT
tl_sram_ctrl_main__ram_i.d_sink	No	No		No		INPUT
tl_sram_ctrl_main__ram_i.d_source[0]	No	No		No		INPUT
tl_sram_ctrl_main__ram_i.d_source[1]	Yes	Yes	*T1,*T9,*T10	Yes	T1,T9,T10	INPUT
tl_sram_ctrl_main__ram_i.d_source[5:2]	No	No		No		INPUT
tl_sram_ctrl_main__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_size[0]	No	No		No		INPUT
tl_sram_ctrl_main__ram_i.d_size[1]	Yes	Yes	T1,T9,T10	Yes	T1,T9,T10	INPUT
tl_sram_ctrl_main__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_opcode[0]	Yes	Yes	*T1,*T9,*T10	Yes	T1,T9,T10	INPUT
tl_sram_ctrl_main__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_valid	Yes	Yes	T1,T9,T10	Yes	T1,T9,T10	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range