Unified Coverage Report :: Module :: prim_mubi4_sync

Module : prim_mubi4_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync	100.00						100.00

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.93	96.37	100.00			93.22	94.12	u_pinmux_strap_sampling

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : prim_mubi4_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	16	16	0	0
OutputsKnown_A	1741522	1725755	0	0
gen_no_flops.OutputDelay_A	1741522	1725755	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16	16	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1741522	1725755	0	0
T1	266152	264929	0	0
T2	471630	470982	0	0
T3	184088	182603	0	0
T4	10194	9232	0	0
T5	10129	9222	0	0
T6	10641	9133	0	0
T7	10334	9313	0	0
T9	265363	264558	0	0
T10	269393	268093	0	0
T11	182656	181911	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1741522	1725755	0	0
T1	266152	264929	0	0
T2	471630	470982	0	0
T3	184088	182603	0	0
T4	10194	9232	0	0
T5	10129	9222	0	0
T6	10641	9133	0	0
T7	10334	9313	0	0
T9	265363	264558	0	0
T10	269393	268093	0	0
T11	182656	181911	0	0

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	16	16	0	0
OutputsKnown_A	1741522	1725755	0	0
gen_no_flops.OutputDelay_A	1741522	1725755	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16	16	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1741522	1725755	0	0
T1	266152	264929	0	0
T2	471630	470982	0	0
T3	184088	182603	0	0
T4	10194	9232	0	0
T5	10129	9222	0	0
T6	10641	9133	0	0
T7	10334	9313	0	0
T9	265363	264558	0	0
T10	269393	268093	0	0
T11	182656	181911	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1741522	1725755	0	0
T1	266152	264929	0	0
T2	471630	470982	0	0
T3	184088	182603	0	0
T4	10194	9232	0	0
T5	10129	9222	0	0
T6	10641	9133	0	0
T7	10334	9313	0	0
T9	265363	264558	0	0
T10	269393	268093	0	0
T11	182656	181911	0	0