Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg 100.00 1 100 1 64 64



Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 64 0 64 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_num_of_outstanding 64 0 64 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 64 0 64 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_num_of_outstanding 64 0 64 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 64 0 64 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_num_of_outstanding 64 0 64 100.00 100 1 1 0


Summary for Variable cp_num_of_outstanding

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 64 0 64 100.00


User Defined Bins for cp_num_of_outstanding

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[1] 3536611 1 T14 2065 T15 40 T16 1768
values[2] 729360 1 T14 171 T15 21 T16 160
values[3] 110625 1 T14 2 T15 2 T31 94
values[4] 58669 1 T31 65 T33 287 T62 27
values[5] 39014 1 T31 47 T33 217 T62 29
values[6] 28882 1 T31 53 T33 140 T62 18
values[7] 23023 1 T31 66 T33 108 T62 21
values[8] 19936 1 T31 62 T33 62 T62 32
values[9] 17753 1 T31 55 T33 80 T62 40
values[10] 16141 1 T31 50 T33 61 T62 32
values[11] 14947 1 T31 61 T33 45 T62 13
values[12] 14701 1 T31 54 T33 61 T62 17
values[13] 14074 1 T31 46 T33 46 T62 36
values[14] 13555 1 T31 65 T33 47 T62 27
values[15] 13200 1 T31 82 T33 44 T62 48
values[16] 12161 1 T31 63 T33 31 T62 24
values[17] 11356 1 T31 45 T33 18 T62 14
values[18] 11093 1 T31 24 T33 13 T62 25
values[19] 10703 1 T31 16 T33 19 T62 16
values[20] 10443 1 T31 28 T33 17 T62 8
values[21] 10077 1 T31 32 T33 31 T62 3
values[22] 9850 1 T31 46 T33 33 T62 7
values[23] 9479 1 T31 42 T33 27 T62 9
values[24] 9431 1 T31 37 T33 21 T62 5
values[25] 9096 1 T31 31 T33 22 T62 3
values[26] 8274 1 T31 23 T33 22 T62 7
values[27] 7969 1 T31 28 T33 28 T62 8
values[28] 7647 1 T31 10 T33 26 T62 10
values[29] 7116 1 T31 20 T33 20 T62 18
values[30] 6686 1 T31 19 T33 21 T62 11
values[31] 6510 1 T31 16 T33 10 T62 7
values[32] 5960 1 T31 13 T33 11 T62 4
values[33] 5526 1 T31 9 T33 13 T62 2
values[34] 5129 1 T31 7 T33 9 T62 3
values[35] 4835 1 T31 11 T33 11 T62 3
values[36] 4480 1 T31 9 T33 14 T62 2
values[37] 4326 1 T31 12 T33 11 T62 3
values[38] 4000 1 T31 7 T33 5 T62 3
values[39] 3775 1 T31 13 T33 5 T62 4
values[40] 3638 1 T31 4 T33 11 T62 3
values[41] 3579 1 T31 3 T33 5 T62 5
values[42] 3578 1 T31 5 T33 9 T62 3
values[43] 3472 1 T31 3 T33 9 T62 5
values[44] 3580 1 T31 3 T33 10 T62 1
values[45] 3417 1 T31 5 T33 10 T62 1
values[46] 3366 1 T31 3 T33 10 T62 3
values[47] 3319 1 T31 3 T33 13 T62 1
values[48] 3225 1 T31 3 T33 19 T62 1
values[49] 3059 1 T31 3 T33 7 T62 1
values[50] 3141 1 T31 6 T33 16 T62 1
values[51] 3089 1 T31 4 T33 11 T62 4
values[52] 2926 1 T31 5 T33 4 T62 4
values[53] 3033 1 T31 3 T33 4 T62 2
values[54] 2984 1 T31 3 T33 4 T62 1
values[55] 2884 1 T31 2 T33 10 T62 3
values[56] 2861 1 T31 2 T33 15 T62 1
values[57] 2747 1 T31 2 T33 4 T62 2
values[58] 2722 1 T31 2 T33 1 T62 2
values[59] 2653 1 T31 2 T33 1 T62 1
values[60] 2734 1 T31 2 T33 1 T62 3
values[61] 3091 1 T31 2 T33 1 T62 3
values[62] 5121 1 T31 2 T33 2 T62 2
values[63] 19957 1 T31 3 T33 4 T62 5
values[64] 226631 1 T31 13 T33 34 T62 6


Summary for Variable cp_num_of_outstanding

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 64 0 64 100.00


User Defined Bins for cp_num_of_outstanding

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[1] 4622612 1 T14 2376 T15 123 T16 1932
values[2] 777411 1 T14 161 T15 26 T16 115
values[3] 76114 1 T15 7 T16 2 T31 72
values[4] 13637 1 T15 1 T31 2 T33 11
values[5] 5119 1 T31 2 T33 6 T215 1
values[6] 3168 1 T31 2 T33 9 T62 4
values[7] 2438 1 T31 2 T33 13 T62 4
values[8] 2096 1 T31 2 T33 12 T62 1
values[9] 1910 1 T31 2 T33 8 T62 1
values[10] 1838 1 T31 2 T33 14 T62 1
values[11] 1699 1 T31 2 T33 15 T62 2
values[12] 1587 1 T31 2 T33 12 T62 1
values[13] 1487 1 T31 2 T33 6 T62 2
values[14] 1455 1 T31 2 T33 6 T62 2
values[15] 1341 1 T31 2 T33 8 T62 1
values[16] 1293 1 T31 2 T33 13 T62 3
values[17] 1327 1 T31 2 T33 16 T62 3
values[18] 1306 1 T31 2 T33 14 T62 2
values[19] 1206 1 T31 3 T33 3 T62 1
values[20] 1083 1 T31 2 T33 3 T62 1
values[21] 932 1 T31 2 T33 2 T62 2
values[22] 846 1 T31 2 T33 6 T62 6
values[23] 768 1 T31 2 T33 5 T62 4
values[24] 695 1 T31 3 T33 2 T62 2
values[25] 718 1 T31 2 T33 2 T62 1
values[26] 700 1 T31 2 T33 3 T62 2
values[27] 640 1 T31 2 T33 4 T62 3
values[28] 652 1 T31 2 T33 2 T62 2
values[29] 708 1 T31 2 T33 5 T62 2
values[30] 704 1 T31 2 T33 8 T62 6
values[31] 645 1 T31 2 T33 7 T62 1
values[32] 570 1 T31 2 T33 1 T62 1
values[33] 584 1 T31 2 T62 5 T342 5
values[34] 571 1 T31 2 T62 1 T342 11
values[35] 532 1 T31 2 T62 1 T342 17
values[36] 509 1 T31 2 T62 3 T342 7
values[37] 521 1 T31 2 T62 3 T342 6
values[38] 591 1 T31 2 T62 1 T342 12
values[39] 512 1 T31 2 T62 1 T342 9
values[40] 495 1 T31 1 T62 3 T342 5
values[41] 493 1 T31 1 T62 3 T342 3
values[42] 461 1 T31 3 T62 1 T342 5
values[43] 447 1 T31 2 T62 2 T342 7
values[44] 444 1 T31 2 T62 3 T342 7
values[45] 444 1 T31 2 T62 5 T342 1
values[46] 420 1 T31 2 T62 1 T342 1
values[47] 369 1 T31 2 T62 2 T342 1
values[48] 401 1 T31 2 T62 2 T342 1
values[49] 400 1 T31 2 T62 1 T342 1
values[50] 398 1 T31 2 T62 2 T342 1
values[51] 406 1 T31 2 T62 1 T342 1
values[52] 404 1 T31 2 T62 1 T342 1
values[53] 372 1 T31 2 T62 2 T342 3
values[54] 369 1 T31 2 T62 1 T342 2
values[55] 369 1 T31 2 T62 3 T342 1
values[56] 389 1 T31 2 T62 3 T342 2
values[57] 383 1 T31 2 T62 1 T342 1
values[58] 375 1 T31 2 T62 2 T342 1
values[59] 373 1 T31 2 T62 1 T342 1
values[60] 377 1 T31 2 T62 1 T342 1
values[61] 395 1 T31 2 T62 1 T342 1
values[62] 645 1 T31 2 T62 1 T342 2
values[63] 3188 1 T31 10 T62 2 T342 23
values[64] 25038 1 T31 163 T62 8 T342 37


Summary for Variable cp_num_of_outstanding

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 64 0 64 100.00


User Defined Bins for cp_num_of_outstanding

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[1] 569594 1 T14 26 T15 1 T16 87
values[2] 2487321 1 T14 2284 T15 63 T16 593
values[3] 1127877 1 T14 186 T15 23 T16 1130
values[4] 151931 1 T16 10 T31 194 T33 534
values[5] 78392 1 T16 1 T31 131 T33 331
values[6] 51718 1 T31 104 T33 206 T62 35
values[7] 37347 1 T31 79 T33 179 T62 31
values[8] 29735 1 T31 75 T33 157 T62 38
values[9] 25230 1 T31 45 T33 127 T62 33
values[10] 22718 1 T31 59 T33 104 T62 42
values[11] 20124 1 T31 52 T33 79 T62 50
values[12] 18314 1 T31 64 T33 68 T62 23
values[13] 16721 1 T31 45 T33 65 T62 9
values[14] 15831 1 T31 64 T33 57 T62 16
values[15] 15100 1 T31 87 T33 46 T62 24
values[16] 14357 1 T31 65 T33 40 T62 27
values[17] 13751 1 T31 63 T33 33 T62 28
values[18] 13425 1 T31 47 T33 37 T62 26
values[19] 12821 1 T31 50 T33 40 T62 25
values[20] 11939 1 T31 43 T33 39 T62 14
values[21] 11898 1 T31 51 T33 26 T62 19
values[22] 11625 1 T31 54 T33 24 T62 40
values[23] 11175 1 T31 74 T33 24 T62 41
values[24] 10857 1 T31 69 T33 23 T62 19
values[25] 10474 1 T31 47 T33 16 T62 19
values[26] 9899 1 T31 31 T33 12 T62 14
values[27] 9260 1 T31 25 T33 10 T62 9
values[28] 8916 1 T31 26 T33 12 T62 15
values[29] 8853 1 T31 33 T33 3 T62 15
values[30] 8094 1 T31 33 T33 4 T62 11
values[31] 7311 1 T31 25 T33 2 T62 6
values[32] 6823 1 T31 60 T33 2 T62 8
values[33] 6158 1 T31 28 T33 2 T62 2
values[34] 5809 1 T31 10 T33 7 T62 3
values[35] 5534 1 T31 7 T33 6 T62 5
values[36] 5091 1 T31 7 T33 14 T62 10
values[37] 4733 1 T31 5 T33 9 T62 7
values[38] 4676 1 T31 4 T33 9 T62 3
values[39] 4378 1 T31 5 T33 7 T62 2
values[40] 4235 1 T31 13 T33 11 T62 12
values[41] 4107 1 T31 5 T33 5 T62 4
values[42] 4013 1 T31 10 T33 2 T62 4
values[43] 3932 1 T31 3 T33 3 T62 10
values[44] 3877 1 T31 2 T33 7 T62 8
values[45] 3713 1 T31 6 T33 7 T62 3
values[46] 3619 1 T31 4 T33 4 T62 2
values[47] 3546 1 T31 12 T33 2 T62 2
values[48] 3598 1 T31 7 T33 4 T62 2
values[49] 3612 1 T31 1 T33 6 T62 4
values[50] 3421 1 T31 3 T33 9 T62 2
values[51] 3295 1 T31 3 T33 3 T62 1
values[52] 3222 1 T31 2 T33 5 T62 1
values[53] 3254 1 T31 2 T33 4 T62 4
values[54] 3196 1 T31 2 T33 10 T62 1
values[55] 3201 1 T31 3 T33 11 T62 1
values[56] 3015 1 T31 2 T33 10 T62 1
values[57] 3101 1 T31 1 T33 7 T62 1
values[58] 2989 1 T33 2 T62 5 T216 8
values[59] 2883 1 T33 4 T62 2 T216 8
values[60] 2978 1 T33 5 T62 3 T216 8
values[61] 3249 1 T33 3 T62 2 T216 9
values[62] 4695 1 T33 5 T62 2 T216 8
values[63] 20646 1 T33 4 T62 2 T216 163
values[64] 211862 1 T33 56 T62 2 T216 1281

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