Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64



Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 973598 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 1516211 1 T11 1222 T12 338 T13 2005


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 1922552 1 T11 2335 T12 79 T13 3001
values[0x0] 268445 1 T11 45 T12 150 T13 1142
values[0x1] 298812 1 T11 41 T12 744 T13 1168


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 729934 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 1759875 1 T11 1594 T12 770 T13 2903


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 38123 1 T11 55 T12 18 T13 89
valid_sources[0x01] 38178 1 T11 46 T12 20 T13 123
valid_sources[0x02] 41679 1 T11 34 T12 11 T13 68
valid_sources[0x03] 38278 1 T11 39 T12 15 T13 75
valid_sources[0x04] 39665 1 T11 47 T12 16 T13 110
valid_sources[0x05] 38875 1 T11 42 T12 10 T13 69
valid_sources[0x06] 39276 1 T11 44 T12 12 T13 98
valid_sources[0x07] 39384 1 T11 28 T12 13 T13 86
valid_sources[0x08] 39451 1 T11 49 T12 13 T13 70
valid_sources[0x09] 39747 1 T11 46 T12 16 T13 109
valid_sources[0x0a] 39026 1 T11 39 T12 20 T13 69
valid_sources[0x0b] 38578 1 T11 38 T12 12 T13 69
valid_sources[0x0c] 37787 1 T11 34 T12 20 T13 65
valid_sources[0x0d] 39507 1 T11 23 T12 16 T13 70
valid_sources[0x0e] 38583 1 T11 31 T12 21 T13 51
valid_sources[0x0f] 38071 1 T11 31 T12 17 T13 82
valid_sources[0x10] 37245 1 T11 46 T12 11 T13 66
valid_sources[0x11] 38613 1 T11 39 T12 23 T13 67
valid_sources[0x12] 37808 1 T11 32 T12 15 T13 84
valid_sources[0x13] 39909 1 T11 37 T12 17 T13 82
valid_sources[0x14] 38571 1 T11 45 T12 16 T13 88
valid_sources[0x15] 38876 1 T11 42 T12 13 T13 103
valid_sources[0x16] 38807 1 T11 48 T12 18 T13 69
valid_sources[0x17] 38776 1 T11 36 T12 10 T13 64
valid_sources[0x18] 40252 1 T11 33 T12 12 T13 66
valid_sources[0x19] 39729 1 T11 43 T12 17 T13 124
valid_sources[0x1a] 41346 1 T11 26 T12 18 T13 44
valid_sources[0x1b] 39196 1 T11 38 T12 23 T13 100
valid_sources[0x1c] 39913 1 T11 37 T12 15 T13 103
valid_sources[0x1d] 38530 1 T11 41 T12 14 T13 61
valid_sources[0x1e] 38541 1 T11 35 T12 23 T13 76
valid_sources[0x1f] 38690 1 T11 33 T12 18 T13 64
valid_sources[0x20] 39117 1 T11 32 T12 20 T13 83


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 1089086 1 T11 1136 T12 73 T13 731
values[0x0] all_enables biggest_size 221796 1 T11 45 T12 128 T13 689
values[0x1] all_enables biggest_size 205329 1 T11 41 T12 137 T13 585


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 2819770 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 446971 1 T14 9 T15 5 T16 288


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 1105379 1 T14 52 T15 17 T16 650
values[0x0] 1054984 1 T14 3 T15 22 T16 623
values[0x1] 1106378 1 T14 49 T15 24 T16 655


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 2183858 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 1082883 1 T14 41 T15 19 T16 650


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 51024 1 T14 3 T15 2 T16 24
valid_sources[0x01] 50076 1 T14 3 T15 1 T16 17
valid_sources[0x02] 50638 1 T14 1 T15 3 T16 30
valid_sources[0x03] 51572 1 T14 2 T15 2 T16 98
valid_sources[0x04] 51574 1 T14 5 T16 67 T17 48
valid_sources[0x05] 50959 1 T14 4 T15 2 T16 16
valid_sources[0x06] 51848 1 T16 50 T17 33 T31 7
valid_sources[0x07] 51261 1 T14 1 T15 2 T16 33
valid_sources[0x08] 51493 1 T14 3 T16 69 T17 44
valid_sources[0x09] 51140 1 T14 3 T16 29 T17 52
valid_sources[0x0a] 50740 1 T15 2 T16 86 T17 34
valid_sources[0x0b] 51360 1 T14 1 T15 4 T16 18
valid_sources[0x0c] 51069 1 T14 1 T16 64 T17 42
valid_sources[0x0d] 50935 1 T14 2 T15 1 T16 2
valid_sources[0x0e] 50235 1 T14 4 T16 11 T17 41
valid_sources[0x0f] 51368 1 T14 2 T15 2 T16 9
valid_sources[0x10] 50277 1 T14 1 T15 2 T17 44
valid_sources[0x11] 50332 1 T14 1 T16 4 T17 17
valid_sources[0x12] 50801 1 T14 4 T16 37 T17 68
valid_sources[0x13] 51620 1 T16 43 T17 67 T31 17
valid_sources[0x14] 50518 1 T14 1 T15 2 T16 4
valid_sources[0x15] 52400 1 T14 1 T16 12 T17 15
valid_sources[0x16] 50816 1 T14 1 T15 1 T16 51
valid_sources[0x17] 49891 1 T15 2 T16 40 T17 39
valid_sources[0x18] 50424 1 T14 2 T15 2 T16 9
valid_sources[0x19] 50058 1 T14 2 T16 47 T17 39
valid_sources[0x1a] 49958 1 T14 1 T16 22 T17 50
valid_sources[0x1b] 51938 1 T14 2 T15 2 T16 56
valid_sources[0x1c] 51566 1 T14 2 T16 1 T17 7
valid_sources[0x1d] 51300 1 T14 1 T16 25 T17 71
valid_sources[0x1e] 50836 1 T14 1 T16 13 T17 34
valid_sources[0x1f] 51431 1 T14 2 T16 1 T31 17
valid_sources[0x20] 51202 1 T15 1 T16 28 T31 14


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 47188 1 T14 4 T16 22 T17 25
values[0x0] all_enables biggest_size 352846 1 T15 5 T16 244 T17 212
values[0x1] all_enables biggest_size 46937 1 T14 5 T16 22 T17 31


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 3011816 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 489469 1 T14 12 T15 26 T16 319


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 1196996 1 T14 52 T15 53 T16 651
values[0x0] 1105890 1 T14 6 T15 52 T16 683
values[0x1] 1198399 1 T14 57 T15 52 T16 715


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 2310712 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 1190573 1 T14 47 T15 55 T16 719


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 54213 1 T15 1 T16 1 T31 19
valid_sources[0x01] 54254 1 T14 2 T15 3 T16 28
valid_sources[0x02] 55171 1 T14 1 T15 4 T16 78
valid_sources[0x03] 55150 1 T14 4 T15 3 T16 15
valid_sources[0x04] 54483 1 T14 1 T15 3 T16 47
valid_sources[0x05] 54908 1 T14 1 T15 3 T16 33
valid_sources[0x06] 55908 1 T14 2 T15 4 T16 115
valid_sources[0x07] 55553 1 T16 86 T17 49 T31 13
valid_sources[0x08] 54338 1 T14 1 T15 3 T16 9
valid_sources[0x09] 54904 1 T15 2 T16 4 T17 47
valid_sources[0x0a] 55449 1 T14 2 T15 3 T16 51
valid_sources[0x0b] 54792 1 T14 2 T15 3 T16 143
valid_sources[0x0c] 55001 1 T14 1 T15 3 T16 24
valid_sources[0x0d] 54696 1 T14 5 T15 4 T16 14
valid_sources[0x0e] 54093 1 T15 4 T16 17 T17 74
valid_sources[0x0f] 54917 1 T14 5 T15 4 T16 28
valid_sources[0x10] 54634 1 T14 2 T15 2 T16 25
valid_sources[0x11] 54808 1 T14 5 T15 1 T16 66
valid_sources[0x12] 54618 1 T14 2 T15 3 T16 3
valid_sources[0x13] 54823 1 T15 2 T16 15 T17 74
valid_sources[0x14] 54879 1 T14 2 T15 2 T16 35
valid_sources[0x15] 54473 1 T14 5 T15 1 T16 39
valid_sources[0x16] 53570 1 T14 4 T15 3 T16 38
valid_sources[0x17] 53710 1 T17 29 T31 15 T33 62
valid_sources[0x18] 54057 1 T14 1 T15 2 T16 35
valid_sources[0x19] 54744 1 T16 7 T17 57 T31 13
valid_sources[0x1a] 54838 1 T15 2 T16 43 T17 50
valid_sources[0x1b] 54841 1 T14 2 T15 2 T16 42
valid_sources[0x1c] 55353 1 T15 2 T16 5 T17 20
valid_sources[0x1d] 54972 1 T16 24 T17 52 T31 14
valid_sources[0x1e] 54619 1 T15 2 T16 35 T17 47
valid_sources[0x1f] 55174 1 T15 1 T16 76 T31 12
valid_sources[0x20] 54703 1 T14 3 T15 2 T16 7


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 51248 1 T14 5 T15 3 T16 28
values[0x0] all_enables biggest_size 386888 1 T14 4 T15 21 T16 265
values[0x1] all_enables biggest_size 51333 1 T14 3 T15 2 T16 26


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 2836793 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 448630 1 T14 12 T15 9 T16 242


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 1111375 1 T14 48 T15 27 T16 606
values[0x0] 1062973 1 T14 5 T15 25 T16 604
values[0x1] 1111075 1 T14 45 T15 35 T16 611


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 2196985 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 1088438 1 T14 43 T15 26 T16 597


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 50708 1 T16 24 T31 9 T33 40
valid_sources[0x01] 51390 1 T14 1 T16 34 T17 82
valid_sources[0x02] 51260 1 T14 2 T16 23 T17 38
valid_sources[0x03] 51976 1 T14 6 T16 24 T17 15
valid_sources[0x04] 51331 1 T14 2 T16 27 T17 29
valid_sources[0x05] 51651 1 T14 1 T16 14 T17 28
valid_sources[0x06] 52085 1 T14 1 T16 26 T17 35
valid_sources[0x07] 52013 1 T14 1 T16 35 T17 20
valid_sources[0x08] 50853 1 T14 1 T16 28 T17 55
valid_sources[0x09] 51742 1 T14 2 T16 30 T17 53
valid_sources[0x0a] 50463 1 T14 2 T15 6 T16 31
valid_sources[0x0b] 51632 1 T14 2 T16 33 T17 23
valid_sources[0x0c] 51882 1 T14 1 T16 32 T17 39
valid_sources[0x0d] 51692 1 T15 6 T16 34 T17 26
valid_sources[0x0e] 50798 1 T15 9 T16 38 T17 68
valid_sources[0x0f] 51575 1 T14 1 T16 32 T17 57
valid_sources[0x10] 51660 1 T14 2 T16 27 T17 39
valid_sources[0x11] 51333 1 T16 25 T17 8 T31 7
valid_sources[0x12] 51534 1 T16 28 T17 45 T31 16
valid_sources[0x13] 51746 1 T14 3 T15 2 T16 23
valid_sources[0x14] 51726 1 T14 4 T16 23 T17 43
valid_sources[0x15] 52424 1 T14 2 T16 25 T17 37
valid_sources[0x16] 50925 1 T14 1 T16 17 T17 16
valid_sources[0x17] 50646 1 T16 21 T17 19 T31 14
valid_sources[0x18] 50901 1 T14 4 T16 21 T17 7
valid_sources[0x19] 50486 1 T14 4 T16 25 T17 46
valid_sources[0x1a] 50991 1 T14 1 T16 24 T17 28
valid_sources[0x1b] 51332 1 T16 26 T17 37 T31 12
valid_sources[0x1c] 51616 1 T16 26 T17 9 T31 8
valid_sources[0x1d] 50805 1 T14 6 T16 30 T17 83
valid_sources[0x1e] 51588 1 T15 1 T16 20 T17 59
valid_sources[0x1f] 51008 1 T14 3 T16 26 T31 24
valid_sources[0x20] 51708 1 T14 2 T16 32 T31 14


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 46745 1 T14 8 T15 1 T16 22
values[0x0] all_enables biggest_size 354722 1 T14 1 T15 7 T16 195
values[0x1] all_enables biggest_size 47163 1 T14 3 T15 1 T16 25

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%