Unified Coverage Report :: Module :: prim_alert_sender

Module : prim_alert_sender

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
58.33			58.33

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_sender.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[0].u_alert_sender	33.33			33.33
tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[1].u_alert_sender	33.33			33.33
tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[2].u_alert_sender	33.33			33.33
tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[3].u_alert_sender	33.33			33.33
tb.dut.top_earlgrey.u_pinmux_aon.gen_alert_tx[0].u_prim_alert_sender	58.33			58.33
tb.dut.top_earlgrey.u_rv_plic.gen_alert_tx[0].u_prim_alert_sender	58.33			58.33

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[0].u_alert_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
33.33			33.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
33.33			33.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
42.11	28.24	14.29	62.34		58.33	47.37	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[1].u_alert_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
33.33			33.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
33.33			33.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
42.11	28.24	14.29	62.34		58.33	47.37	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[2].u_alert_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
33.33			33.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
33.33			33.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
42.11	28.24	14.29	62.34		58.33	47.37	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[3].u_alert_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
33.33			33.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
33.33			33.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
42.11	28.24	14.29	62.34		58.33	47.37	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_alert_tx[0].u_prim_alert_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
58.33			58.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
58.33			58.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
71.75	93.65	52.50	96.08		35.73	80.77	u_pinmux_aon

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_plic.gen_alert_tx[0].u_prim_alert_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
58.33			58.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
58.33			58.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
73.51	43.71	66.67	93.28		75.00	88.89	u_rv_plic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : prim_alert_sender

	Total	Covered	Percent
Totals	12	7	58.33
Total Bits	24	14	58.33
Total Bits 0->1	12	7	58.33
Total Bits 1->0	12	7	58.33

Ports	12	7	58.33
Port Bits	24	14	58.33
Port Bits 0->1	12	7	58.33
Port Bits 1->0	12	7	58.33

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_test_i	Yes	Yes	T27,T43	Yes	T27,T43	INPUT
alert_req_i	No	No		No		INPUT
alert_ack_o	No	No		No		OUTPUT
alert_state_o	No	No		No		OUTPUT
alert_rx_i.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i.ack_p	Yes	Yes	T27,T43	Yes	T27,T43	INPUT
alert_rx_i.ping_n	No	No		No		INPUT
alert_rx_i.ping_p	No	No		No		INPUT
alert_tx_o.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T27,T43	Yes	T27,T43	OUTPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[0].u_alert_sender

	Total	Covered	Percent
Totals	12	4	33.33
Total Bits	24	8	33.33
Total Bits 0->1	12	4	33.33
Total Bits 1->0	12	4	33.33

Ports	12	4	33.33
Port Bits	24	8	33.33
Port Bits 0->1	12	4	33.33
Port Bits 1->0	12	4	33.33

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_test_i	No	No		No		INPUT
alert_req_i	No	No		No		INPUT
alert_ack_o	No	No		No		OUTPUT
alert_state_o	No	No		No		OUTPUT
alert_rx_i.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i.ack_p	No	No		No		INPUT
alert_rx_i.ping_n	No	No		No		INPUT
alert_rx_i.ping_p	No	No		No		INPUT
alert_tx_o.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o.alert_p	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[1].u_alert_sender

	Total	Covered	Percent
Totals	12	4	33.33
Total Bits	24	8	33.33
Total Bits 0->1	12	4	33.33
Total Bits 1->0	12	4	33.33

Ports	12	4	33.33
Port Bits	24	8	33.33
Port Bits 0->1	12	4	33.33
Port Bits 1->0	12	4	33.33

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_test_i	No	No		No		INPUT
alert_req_i	No	No		No		INPUT
alert_ack_o	No	No		No		OUTPUT
alert_state_o	No	No		No		OUTPUT
alert_rx_i.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i.ack_p	No	No		No		INPUT
alert_rx_i.ping_n	No	No		No		INPUT
alert_rx_i.ping_p	No	No		No		INPUT
alert_tx_o.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o.alert_p	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[2].u_alert_sender

	Total	Covered	Percent
Totals	12	4	33.33
Total Bits	24	8	33.33
Total Bits 0->1	12	4	33.33
Total Bits 1->0	12	4	33.33

Ports	12	4	33.33
Port Bits	24	8	33.33
Port Bits 0->1	12	4	33.33
Port Bits 1->0	12	4	33.33

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_test_i	No	No		No		INPUT
alert_req_i	No	No		No		INPUT
alert_ack_o	No	No		No		OUTPUT
alert_state_o	No	No		No		OUTPUT
alert_rx_i.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i.ack_p	No	No		No		INPUT
alert_rx_i.ping_n	No	No		No		INPUT
alert_rx_i.ping_p	No	No		No		INPUT
alert_tx_o.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o.alert_p	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[3].u_alert_sender

	Total	Covered	Percent
Totals	12	4	33.33
Total Bits	24	8	33.33
Total Bits 0->1	12	4	33.33
Total Bits 1->0	12	4	33.33

Ports	12	4	33.33
Port Bits	24	8	33.33
Port Bits 0->1	12	4	33.33
Port Bits 1->0	12	4	33.33

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_test_i	No	No		No		INPUT
alert_req_i	No	No		No		INPUT
alert_ack_o	No	No		No		OUTPUT
alert_state_o	No	No		No		OUTPUT
alert_rx_i.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i.ack_p	No	No		No		INPUT
alert_rx_i.ping_n	No	No		No		INPUT
alert_rx_i.ping_p	No	No		No		INPUT
alert_tx_o.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o.alert_p	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_alert_tx[0].u_prim_alert_sender

	Total	Covered	Percent
Totals	12	7	58.33
Total Bits	24	14	58.33
Total Bits 0->1	12	7	58.33
Total Bits 1->0	12	7	58.33

Ports	12	7	58.33
Port Bits	24	14	58.33
Port Bits 0->1	12	7	58.33
Port Bits 1->0	12	7	58.33

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_test_i	Yes	Yes	T43	Yes	T43	INPUT
alert_req_i	No	No		No		INPUT
alert_ack_o	No	No		No		OUTPUT
alert_state_o	No	No		No		OUTPUT
alert_rx_i.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i.ack_p	Yes	Yes	T43	Yes	T43	INPUT
alert_rx_i.ping_n	No	No		No		INPUT
alert_rx_i.ping_p	No	No		No		INPUT
alert_tx_o.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T43	Yes	T43	OUTPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.gen_alert_tx[0].u_prim_alert_sender

	Total	Covered	Percent
Totals	12	7	58.33
Total Bits	24	14	58.33
Total Bits 0->1	12	7	58.33
Total Bits 1->0	12	7	58.33

Ports	12	7	58.33
Port Bits	24	14	58.33
Port Bits 0->1	12	7	58.33
Port Bits 1->0	12	7	58.33

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_test_i	Yes	Yes	T27	Yes	T27	INPUT
alert_req_i	No	No		No		INPUT
alert_ack_o	No	No		No		OUTPUT
alert_state_o	No	No		No		OUTPUT
alert_rx_i.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i.ack_p	Yes	Yes	T27	Yes	T27	INPUT
alert_rx_i.ping_n	No	No		No		INPUT
alert_rx_i.ping_p	No	No		No		INPUT
alert_tx_o.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T27	Yes	T27	OUTPUT