Unified Coverage Report :: Module :: i2c

Module : i2c

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.78			98.78

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_i2c0	96.91			96.91
tb.dut.top_earlgrey.u_i2c1	97.55			97.55
tb.dut.top_earlgrey.u_i2c2	98.77			98.77

---

Module Instance : tb.dut.top_earlgrey.u_i2c0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.91			96.91

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.91			96.91

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
79.99	55.91		84.05			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_i2c1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.55			97.55

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.55			97.55

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
79.99	55.91		84.05			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_i2c2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.77			98.77

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.77			98.77

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
79.99	55.91		84.05			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : i2c

	Total	Covered	Percent
Totals	48	46	95.83
Total Bits	328	324	98.78
Total Bits 0->1	164	162	98.78
Total Bits 1->0	164	162	98.78

Ports	48	46	95.83
Port Bits	328	324	98.78
Port Bits 0->1	164	162	98.78
Port Bits 1->0	164	162	98.78

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	INPUT
rst_ni	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	INPUT
tl_i.d_ready	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
tl_i.a_address[6:0]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
tl_i.a_address[15:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
tl_i.a_address[18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[19]	Yes	Yes	*T14,*T15,*T16	Yes	T14,T15,T16	INPUT
tl_i.a_address[29:20]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T14,*T15,*T16	Yes	T14,T15,T16	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
tl_i.a_valid	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
tl_o.a_ready	Yes	Yes	T15,T16,T17	Yes	T14,T15,T16	OUTPUT
tl_o.d_error	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	OUTPUT
tl_o.d_sink	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	T14,T16,T17	Yes	T14,T15,T16	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T14,*T15,*T16	Yes	T14,T15,T16	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T13,T20,T18	Yes	T13,T20,T18	INPUT
alert_rx_i[0].ping_n	No	No		No		INPUT
alert_rx_i[0].ping_p	No	No		No		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T13,T20,T18	Yes	T13,T20,T18	OUTPUT
cio_scl_i	Yes	Yes	T34,T1,T2	Yes	T34,T1,T2	INPUT
cio_scl_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_scl_en_o	Yes	Yes	T13,T29,T18	Yes	T13,T29,T18	OUTPUT
cio_sda_i	Yes	Yes	T44,T1,T2	Yes	T44,T1,T2	INPUT
cio_sda_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_sda_en_o	Yes	Yes	T13,T20,T29	Yes	T13,T20,T29	OUTPUT
intr_fmt_threshold_o	Yes	Yes	T29,T18,T34	Yes	T29,T18,T34	OUTPUT
intr_rx_threshold_o	Yes	Yes	T29,T21,T22	Yes	T29,T21,T22	OUTPUT
intr_fmt_overflow_o	Yes	Yes	T29,T21	Yes	T29,T21	OUTPUT
intr_rx_overflow_o	Yes	Yes	T21,T22,T23	Yes	T21,T22,T23	OUTPUT
intr_nak_o	Yes	Yes	T21,T22,T23	Yes	T21,T22,T23	OUTPUT
intr_scl_interference_o	Yes	Yes	T29,T21,T22	Yes	T29,T21,T22	OUTPUT
intr_sda_interference_o	Yes	Yes	T20,T29,T18	Yes	T20,T29,T18	OUTPUT
intr_stretch_timeout_o	Yes	Yes	T29,T21,T22	Yes	T29,T21,T22	OUTPUT
intr_sda_unstable_o	Yes	Yes	T21,T23,T30	Yes	T21,T23,T30	OUTPUT
intr_cmd_complete_o	Yes	Yes	T21,T22,T23	Yes	T21,T22,T23	OUTPUT
intr_tx_stretch_o	Yes	Yes	T21,T23	Yes	T21,T23	OUTPUT
intr_tx_overflow_o	Yes	Yes	T29,T21,T23	Yes	T29,T21,T23	OUTPUT
intr_acq_full_o	Yes	Yes	T29,T23,T30	Yes	T29,T23,T30	OUTPUT
intr_unexp_stop_o	Yes	Yes	T29,T23,T30	Yes	T29,T23,T30	OUTPUT
intr_host_timeout_o	Yes	Yes	T29,T22,T23	Yes	T29,T22,T23	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_i2c0

	Total	Covered	Percent
Totals	48	43	89.58
Total Bits	324	314	96.91
Total Bits 0->1	162	157	96.91
Total Bits 1->0	162	157	96.91

Ports	48	43	89.58
Port Bits	324	314	96.91
Port Bits 0->1	162	157	96.91
Port Bits 1->0	162	157	96.91

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	INPUT
rst_ni	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	INPUT
tl_i.d_ready	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
tl_i.a_address[6:0]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
tl_i.a_address[18:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[19]	Yes	Yes	*T14,*T15,*T16	Yes	T14,T15,T16	INPUT
tl_i.a_address[29:20]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T14,*T15,*T16	Yes	T14,T15,T16	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
tl_i.a_valid	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
tl_o.a_ready	Yes	Yes	T15,T16,T17	Yes	T14,T15,T16	OUTPUT
tl_o.d_error	Yes	Yes	T14,T16,T17	Yes	T14,T16,T17	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T14,T16,T17	Yes	T14,T16,T17	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T14,T15,T16	Yes	T14,T16,T17	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T14,T16,T17	Yes	T14,T16,T17	OUTPUT
tl_o.d_sink	Yes	Yes	T14,T16,T17	Yes	T14,T16,T17	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	T14,T16,T17	Yes	T14,T15,T16	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T14,*T16,*T17	Yes	T14,T15,T16	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T13,T20,T18	Yes	T13,T20,T18	INPUT
alert_rx_i[0].ping_n	No	No		No		INPUT
alert_rx_i[0].ping_p	No	No		No		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T13,T20,T18	Yes	T13,T20,T18	OUTPUT
cio_scl_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cio_scl_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_scl_en_o	Yes	Yes	T29,T18,T19	Yes	T29,T18,T19	OUTPUT
cio_sda_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cio_sda_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_sda_en_o	Yes	Yes	T20,T29,T35	Yes	T20,T29,T35	OUTPUT
intr_fmt_threshold_o	Yes	Yes	T18,T60,T48	Yes	T18,T60,T48	OUTPUT
intr_rx_threshold_o	Yes	Yes	T30	Yes	T30	OUTPUT
intr_fmt_overflow_o	Yes	Yes	T29	Yes	T29	OUTPUT
intr_rx_overflow_o	Yes	Yes	T23	Yes	T23	OUTPUT
intr_nak_o	No	No		No		OUTPUT
intr_scl_interference_o	No	No		No		OUTPUT
intr_sda_interference_o	Yes	Yes	T29,T18,T19	Yes	T29,T18,T19	OUTPUT
intr_stretch_timeout_o	Yes	Yes	T29,T21,T22	Yes	T29,T21,T22	OUTPUT
intr_sda_unstable_o	Yes	Yes	T21,T23,T30	Yes	T21,T23,T30	OUTPUT
intr_cmd_complete_o	Yes	Yes	T21,T23,T30	Yes	T21,T23,T30	OUTPUT
intr_tx_stretch_o	Yes	Yes	T21	Yes	T21	OUTPUT
intr_tx_overflow_o	Yes	Yes	T29,T30	Yes	T29,T30	OUTPUT
intr_acq_full_o	No	No		No		OUTPUT
intr_unexp_stop_o	Yes	Yes	T29,T23,T30	Yes	T29,T23,T30	OUTPUT
intr_host_timeout_o	Yes	Yes	T22,T23	Yes	T22,T23	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_i2c1

	Total	Covered	Percent
Totals	48	44	91.67
Total Bits	326	318	97.55
Total Bits 0->1	163	159	97.55
Total Bits 1->0	163	159	97.55

Ports	48	44	91.67
Port Bits	326	318	97.55
Port Bits 0->1	163	159	97.55
Port Bits 1->0	163	159	97.55

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	INPUT
rst_ni	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	INPUT
tl_i.d_ready	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
tl_i.a_address[6:0]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
tl_i.a_address[15:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T14,*T15,*T16	Yes	T14,T15,T16	INPUT
tl_i.a_address[18:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[19]	Yes	Yes	*T14,*T15,*T16	Yes	T14,T15,T16	INPUT
tl_i.a_address[29:20]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T14,*T15,*T16	Yes	T14,T15,T16	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
tl_i.a_valid	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
tl_o.a_ready	Yes	Yes	T15,T16,T17	Yes	T14,T15,T16	OUTPUT
tl_o.d_error	Yes	Yes	T14,T16,T17	Yes	T14,T16,T17	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T14,T16,T17	Yes	T14,T15,T16	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T14,T15,T16	Yes	T14,T16,T17	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	OUTPUT
tl_o.d_sink	Yes	Yes	T14,T15,T16	Yes	T14,T16,T17	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	T14,T16,T17	Yes	T14,T15,T16	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T14,T15,T16	Yes	T14,T16,T17	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T14,*T16,*T17	Yes	T14,T16,T17	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T20,T18,T19	Yes	T20,T18,T19	INPUT
alert_rx_i[0].ping_n	No	No		No		INPUT
alert_rx_i[0].ping_p	No	No		No		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T20,T18,T19	Yes	T20,T18,T19	OUTPUT
cio_scl_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cio_scl_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_scl_en_o	Yes	Yes	T18,T19,T34	Yes	T18,T19,T34	OUTPUT
cio_sda_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cio_sda_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_sda_en_o	Yes	Yes	T18,T32,T34	Yes	T18,T32,T34	OUTPUT
intr_fmt_threshold_o	Yes	Yes	T29,T18,T34	Yes	T29,T18,T34	OUTPUT
intr_rx_threshold_o	Yes	Yes	T22,T23,T30	Yes	T22,T23,T30	OUTPUT
intr_fmt_overflow_o	Yes	Yes	T21	Yes	T21	OUTPUT
intr_rx_overflow_o	Yes	Yes	T22	Yes	T22	OUTPUT
intr_nak_o	Yes	Yes	T22,T23	Yes	T22,T23	OUTPUT
intr_scl_interference_o	Yes	Yes	T29,T22,T23	Yes	T29,T22,T23	OUTPUT
intr_sda_interference_o	Yes	Yes	T29,T18,T19	Yes	T29,T18,T19	OUTPUT
intr_stretch_timeout_o	Yes	Yes	T29,T23,T30	Yes	T29,T23,T30	OUTPUT
intr_sda_unstable_o	No	No		No		OUTPUT
intr_cmd_complete_o	Yes	Yes	T23	Yes	T23	OUTPUT
intr_tx_stretch_o	Yes	Yes	T23	Yes	T23	OUTPUT
intr_tx_overflow_o	Yes	Yes	T23	Yes	T23	OUTPUT
intr_acq_full_o	Yes	Yes	T30	Yes	T30	OUTPUT
intr_unexp_stop_o	Yes	Yes	T23	Yes	T23	OUTPUT
intr_host_timeout_o	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_i2c2

	Total	Covered	Percent
Totals	48	46	95.83
Total Bits	326	322	98.77
Total Bits 0->1	163	161	98.77
Total Bits 1->0	163	161	98.77

Ports	48	46	95.83
Port Bits	326	322	98.77
Port Bits 0->1	163	161	98.77
Port Bits 1->0	163	161	98.77

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	INPUT
rst_ni	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	INPUT
tl_i.d_ready	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
tl_i.a_address[6:0]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
tl_i.a_address[16:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T14,*T15,*T16	Yes	T14,T15,T16	INPUT
tl_i.a_address[18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[19]	Yes	Yes	*T14,*T15,*T16	Yes	T14,T15,T16	INPUT
tl_i.a_address[29:20]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T14,*T15,*T16	Yes	T14,T15,T16	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
tl_i.a_valid	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
tl_o.a_ready	Yes	Yes	T15,T16,T17	Yes	T14,T15,T16	OUTPUT
tl_o.d_error	Yes	Yes	T14,T15,T17	Yes	T14,T15,T17	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	OUTPUT
tl_o.d_sink	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	T14,T16,T17	Yes	T14,T16,T17	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T14,*T15,*T16	Yes	T14,T15,T16	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T20,T18,T19	Yes	T20,T18,T19	INPUT
alert_rx_i[0].ping_n	No	No		No		INPUT
alert_rx_i[0].ping_p	No	No		No		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T20,T18,T19	Yes	T20,T18,T19	OUTPUT
cio_scl_i	Yes	Yes	T34,T1,T2	Yes	T34,T1,T2	INPUT
cio_scl_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_scl_en_o	Yes	Yes	T13,T29,T19	Yes	T13,T29,T19	OUTPUT
cio_sda_i	Yes	Yes	T44,T1,T2	Yes	T44,T1,T2	INPUT
cio_sda_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_sda_en_o	Yes	Yes	T13,T20,T29	Yes	T13,T20,T29	OUTPUT
intr_fmt_threshold_o	Yes	Yes	T18,T51,T45	Yes	T18,T51,T45	OUTPUT
intr_rx_threshold_o	Yes	Yes	T29,T21,T22	Yes	T29,T21,T22	OUTPUT
intr_fmt_overflow_o	Yes	Yes	T21	Yes	T21	OUTPUT
intr_rx_overflow_o	Yes	Yes	T21,T23	Yes	T21,T23	OUTPUT
intr_nak_o	Yes	Yes	T21,T22,T23	Yes	T21,T22,T23	OUTPUT
intr_scl_interference_o	Yes	Yes	T29,T21,T22	Yes	T29,T21,T22	OUTPUT
intr_sda_interference_o	Yes	Yes	T20,T18,T44	Yes	T20,T18,T44	OUTPUT
intr_stretch_timeout_o	Yes	Yes	T23	Yes	T23	OUTPUT
intr_sda_unstable_o	Yes	Yes	T21,T23	Yes	T21,T23	OUTPUT
intr_cmd_complete_o	Yes	Yes	T22	Yes	T22	OUTPUT
intr_tx_stretch_o	Yes	Yes	T21,T23	Yes	T21,T23	OUTPUT
intr_tx_overflow_o	Yes	Yes	T21	Yes	T21	OUTPUT
intr_acq_full_o	Yes	Yes	T29,T23,T30	Yes	T29,T23,T30	OUTPUT
intr_unexp_stop_o	Yes	Yes	T29	Yes	T29	OUTPUT
intr_host_timeout_o	Yes	Yes	T29	Yes	T29	OUTPUT

*Tests covering at least one bit in the range