Unified Coverage Report :: Module :: sensor_ctrl

Module : sensor_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
52.01	31.51	19.49	59.03		100.00	50.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_systems_sensor_ctrl_0.1/rtl/sensor_ctrl.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_sensor_ctrl_aon	52.01	31.51	19.49	59.03		100.00	50.00

---

Module Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
52.01	31.51	19.49	59.03		100.00	50.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
74.34	73.49	63.40	59.03		82.01	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
79.99	55.91		84.05			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_sync_assign[0].u_alert_in_buf	0.00	0.00
gen_alert_sync_assign[10].u_alert_in_buf	0.00	0.00
gen_alert_sync_assign[1].u_alert_in_buf	0.00	0.00
gen_alert_sync_assign[2].u_alert_in_buf	0.00	0.00
gen_alert_sync_assign[3].u_alert_in_buf	0.00	0.00
gen_alert_sync_assign[4].u_alert_in_buf	0.00	0.00
gen_alert_sync_assign[5].u_alert_in_buf	0.00	0.00
gen_alert_sync_assign[6].u_alert_in_buf	0.00	0.00
gen_alert_sync_assign[7].u_alert_in_buf	0.00	0.00
gen_alert_sync_assign[8].u_alert_in_buf	0.00	0.00
gen_alert_sync_assign[9].u_alert_in_buf	0.00	0.00
u_alert_n_sync	100.00	100.00				100.00
u_alert_p_sync	100.00	100.00				100.00
u_init_chg	94.44	100.00	83.33			100.00
u_init_intr	91.67	100.00	66.67			100.00	100.00
u_io_intr	89.58	100.00	58.33			100.00	100.00
u_io_status_chg	100.00	100.00				100.00
u_reg	82.58	77.90	72.06			80.35	100.00
u_wake_sync	100.00	100.00				100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : sensor_ctrl

	Line No.	Total	Covered	Percent
TOTAL		73	23	31.51
ALWAYS	180	0	0
ALWAYS	180	2	0	0.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	194	1	0	0.00
CONT_ASSIGN	194	1	0	0.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	194	1	0	0.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	194	1	0	0.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	0	0.00
CONT_ASSIGN	195	1	0	0.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	0	0.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	0	0.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	198	1	0	0.00
CONT_ASSIGN	198	1	0	0.00
CONT_ASSIGN	198	1	0	0.00
CONT_ASSIGN	198	1	0	0.00
CONT_ASSIGN	198	1	0	0.00
CONT_ASSIGN	198	1	0	0.00
CONT_ASSIGN	198	1	0	0.00
CONT_ASSIGN	198	1	0	0.00
CONT_ASSIGN	198	1	0	0.00
CONT_ASSIGN	198	1	0	0.00
CONT_ASSIGN	198	1	0	0.00
CONT_ASSIGN	201	1	0	0.00
CONT_ASSIGN	201	1	0	0.00
CONT_ASSIGN	201	1	0	0.00
CONT_ASSIGN	201	1	0	0.00
CONT_ASSIGN	201	1	0	0.00
CONT_ASSIGN	201	1	0	0.00
CONT_ASSIGN	201	1	0	0.00
CONT_ASSIGN	201	1	0	0.00
CONT_ASSIGN	201	1	0	0.00
CONT_ASSIGN	201	1	0	0.00
CONT_ASSIGN	201	1	0	0.00
CONT_ASSIGN	204	1	0	0.00
CONT_ASSIGN	204	1	0	0.00
CONT_ASSIGN	204	1	0	0.00
CONT_ASSIGN	204	1	0	0.00
CONT_ASSIGN	204	1	0	0.00
CONT_ASSIGN	204	1	0	0.00
CONT_ASSIGN	204	1	0	0.00
CONT_ASSIGN	204	1	0	0.00
CONT_ASSIGN	204	1	0	0.00
CONT_ASSIGN	204	1	0	0.00
CONT_ASSIGN	204	1	0	0.00
CONT_ASSIGN	211	1	1	100.00
ALWAYS	221	0	0
ALWAYS	221	3	0	0.00
ALWAYS	229	0	0
ALWAYS	229	3	0	0.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	240	1	1	100.00
CONT_ASSIGN	291	1	0	0.00
ALWAYS	307	3	3	100.00
ALWAYS	318	3	3	100.00
CONT_ASSIGN	329	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_systems_sensor_ctrl_0.1/rtl/sensor_ctrl.sv' or '../src/lowrisc_systems_sensor_ctrl_0.1/rtl/sensor_ctrl.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
180	0	1
181	0	1
194	7	11
195	7	11
198	0	11
201	0	11
204	0	11
211	1	1
221	0	1
222	0	1
223	0	1
229	0	1
230	0	1
231	0	1
238	1	1
240	1	1
291	0	1
307	1	1
308	1	1
310	1	1
318	1	1
319	1	1
321	1	1
329		unreachable

---

Cond Coverage for Module : sensor_ctrl

	Total	Covered	Percent
Conditions	118	23	19.49
Logical	118	23	19.49
Non-Logical	0	0
Event	0	0

 LINE       181
 EXPRESSION (alert_event_p[i] | ((~alert_event_n[i])))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       194
 EXPRESSION (event_vld[0] & ((~reg2hw.fatal_alert_en[0])))
             ------1-----   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       194
 EXPRESSION (event_vld[1] & ((~reg2hw.fatal_alert_en[1])))
             ------1-----   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       194
 EXPRESSION (event_vld[2] & ((~reg2hw.fatal_alert_en[2])))
             ------1-----   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       194
 EXPRESSION (event_vld[3] & ((~reg2hw.fatal_alert_en[3])))
             ------1-----   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       194
 EXPRESSION (event_vld[4] & ((~reg2hw.fatal_alert_en[4])))
             ------1-----   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       194
 EXPRESSION (event_vld[5] & ((~reg2hw.fatal_alert_en[5])))
             ------1-----   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       194
 EXPRESSION (event_vld[6] & ((~reg2hw.fatal_alert_en[6])))
             ------1-----   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       194
 EXPRESSION (event_vld[7] & ((~reg2hw.fatal_alert_en[7])))
             ------1-----   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       194
 EXPRESSION (event_vld[8] & ((~reg2hw.fatal_alert_en[8])))
             ------1-----   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       194
 EXPRESSION (event_vld[9] & ((~reg2hw.fatal_alert_en[9])))
             ------1-----   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       194
 EXPRESSION (event_vld[10] & ((~reg2hw.fatal_alert_en[10])))
             ------1------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       195
 EXPRESSION (event_vld[0] & reg2hw.fatal_alert_en[0])
             ------1-----   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T27
1	0	Not Covered
1	1	Not Covered

 LINE       195
 EXPRESSION (event_vld[1] & reg2hw.fatal_alert_en[1])
             ------1-----   ------------2-----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       195
 EXPRESSION (event_vld[2] & reg2hw.fatal_alert_en[2])
             ------1-----   ------------2-----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       195
 EXPRESSION (event_vld[3] & reg2hw.fatal_alert_en[3])
             ------1-----   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T27
1	0	Not Covered
1	1	Not Covered

 LINE       195
 EXPRESSION (event_vld[4] & reg2hw.fatal_alert_en[4])
             ------1-----   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T27
1	0	Not Covered
1	1	Not Covered

 LINE       195
 EXPRESSION (event_vld[5] & reg2hw.fatal_alert_en[5])
             ------1-----   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T27
1	0	Not Covered
1	1	Not Covered

 LINE       195
 EXPRESSION (event_vld[6] & reg2hw.fatal_alert_en[6])
             ------1-----   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T27
1	0	Not Covered
1	1	Not Covered

 LINE       195
 EXPRESSION (event_vld[7] & reg2hw.fatal_alert_en[7])
             ------1-----   ------------2-----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       195
 EXPRESSION (event_vld[8] & reg2hw.fatal_alert_en[8])
             ------1-----   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T27
1	0	Not Covered
1	1	Not Covered

 LINE       195
 EXPRESSION (event_vld[9] & reg2hw.fatal_alert_en[9])
             ------1-----   ------------2-----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       195
 EXPRESSION (event_vld[10] & reg2hw.fatal_alert_en[10])
             ------1------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T27
1	0	Not Covered
1	1	Not Covered

 LINE       204
 EXPRESSION (recov_event[0] & reg2hw.recov_alert[0].q)
             -------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       204
 EXPRESSION (recov_event[1] & reg2hw.recov_alert[1].q)
             -------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       204
 EXPRESSION (recov_event[2] & reg2hw.recov_alert[2].q)
             -------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       204
 EXPRESSION (recov_event[3] & reg2hw.recov_alert[3].q)
             -------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       204
 EXPRESSION (recov_event[4] & reg2hw.recov_alert[4].q)
             -------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       204
 EXPRESSION (recov_event[5] & reg2hw.recov_alert[5].q)
             -------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       204
 EXPRESSION (recov_event[6] & reg2hw.recov_alert[6].q)
             -------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       204
 EXPRESSION (recov_event[7] & reg2hw.recov_alert[7].q)
             -------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       204
 EXPRESSION (recov_event[8] & reg2hw.recov_alert[8].q)
             -------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       204
 EXPRESSION (recov_event[9] & reg2hw.recov_alert[9].q)
             -------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       204
 EXPRESSION (recov_event[10] & reg2hw.recov_alert[10].q)
             -------1-------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       222
 EXPRESSION (alert_event_p[i] & event_clr[i])
             --------1-------   ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       223
 SUB-EXPRESSION (((~alert_event_n[i])) & event_clr[i])
                 ----------1----------   ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       238
 EXPRESSION (reg2hw.alert_test.recov_alert.qe & reg2hw.alert_test.recov_alert.q)
             ----------------1---------------   ---------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T27

 LINE       240
 EXPRESSION (reg2hw.alert_test.fatal_alert.qe & reg2hw.alert_test.fatal_alert.q)
             ----------------1---------------   ---------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T27

 LINE       291
 EXPRESSION (((|async_alert_event_p)) | ((~&async_alert_event_n)) | ((|reg2hw.recov_alert)))
             ------------1-----------   ------------2------------   -----------3-----------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Not Covered
1	0	0	Not Covered

---

Toggle Coverage for Module : sensor_ctrl

	Total	Covered	Percent
Totals	108	26	24.07
Total Bits	454	268	59.03
Total Bits 0->1	227	135	59.47
Total Bits 1->0	227	133	58.59

Ports	108	26	24.07
Port Bits	454	268	59.03
Port Bits 0->1	227	135	59.47
Port Bits 1->0	227	133	58.59

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_aon_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_aon_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T27	Yes	T27	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T27	Yes	T27	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T27,*T28,*T43	Yes	T27,T28,T43	INPUT
tl_i.a_address[18:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[19]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[21:20]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[22]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:23]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T27,*T28,*T24	Yes	T27,T28,T24	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T27,T28,T24	Yes	T27,T28,T24	INPUT
tl_i.a_valid	Yes	Yes	T27	Yes	T27	INPUT
tl_o.a_ready	Yes	Yes	T27	Yes	T27	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[1:0]	No	No		No		OUTPUT
tl_o.d_user.data_intg[2]	Yes	Yes	*T27	Yes	T27	OUTPUT
tl_o.d_user.data_intg[3]	No	No		No		OUTPUT
tl_o.d_user.data_intg[4]	Yes	Yes	*T27	Yes	T27	OUTPUT
tl_o.d_user.data_intg[5]	No	No		No		OUTPUT
tl_o.d_user.data_intg[6]	Yes	Yes	T27	Yes	T27	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T27	Yes	T27	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	T27	Yes	T27	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T27	Yes	T27	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[0]	Yes	Yes	*T27	Yes	T27	OUTPUT
tl_o.d_source[5:1]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T27	Yes	T27	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T27	Yes	T27	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T27	Yes	T27	OUTPUT
ast_alert_i.alerts[0].n	No	No		No		INPUT
ast_alert_i.alerts[0].p	No	No		No		INPUT
ast_alert_i.alerts[1].n	No	No		No		INPUT
ast_alert_i.alerts[1].p	No	No		No		INPUT
ast_alert_i.alerts[2].n	No	No		No		INPUT
ast_alert_i.alerts[2].p	No	No		No		INPUT
ast_alert_i.alerts[3].n	No	No		No		INPUT
ast_alert_i.alerts[3].p	No	No		No		INPUT
ast_alert_i.alerts[4].n	No	No		No		INPUT
ast_alert_i.alerts[4].p	No	No		No		INPUT
ast_alert_i.alerts[5].n	No	No		No		INPUT
ast_alert_i.alerts[5].p	No	No		No		INPUT
ast_alert_i.alerts[6].n	No	No		No		INPUT
ast_alert_i.alerts[6].p	No	No		No		INPUT
ast_alert_i.alerts[7].n	No	No		No		INPUT
ast_alert_i.alerts[7].p	No	No		No		INPUT
ast_alert_i.alerts[8].n	No	No		No		INPUT
ast_alert_i.alerts[8].p	No	No		No		INPUT
ast_alert_i.alerts[9].n	No	No		No		INPUT
ast_alert_i.alerts[9].p	No	No		No		INPUT
ast_alert_i.alerts[10].n	No	No		No		INPUT
ast_alert_i.alerts[10].p	No	No		No		INPUT
ast_alert_o.alerts_trig[0].n	No	No		No		OUTPUT
ast_alert_o.alerts_trig[0].p	No	No		No		OUTPUT
ast_alert_o.alerts_trig[1].n	No	No		No		OUTPUT
ast_alert_o.alerts_trig[1].p	No	No		No		OUTPUT
ast_alert_o.alerts_trig[2].n	No	No		No		OUTPUT
ast_alert_o.alerts_trig[2].p	No	No		No		OUTPUT
ast_alert_o.alerts_trig[3].n	No	No		No		OUTPUT
ast_alert_o.alerts_trig[3].p	No	No		No		OUTPUT
ast_alert_o.alerts_trig[4].n	No	No		No		OUTPUT
ast_alert_o.alerts_trig[4].p	No	No		No		OUTPUT
ast_alert_o.alerts_trig[5].n	No	No		No		OUTPUT
ast_alert_o.alerts_trig[5].p	No	No		No		OUTPUT
ast_alert_o.alerts_trig[6].n	No	No		No		OUTPUT
ast_alert_o.alerts_trig[6].p	No	No		No		OUTPUT
ast_alert_o.alerts_trig[7].n	No	No		No		OUTPUT
ast_alert_o.alerts_trig[7].p	No	No		No		OUTPUT
ast_alert_o.alerts_trig[8].n	No	No		No		OUTPUT
ast_alert_o.alerts_trig[8].p	No	No		No		OUTPUT
ast_alert_o.alerts_trig[9].n	No	No		No		OUTPUT
ast_alert_o.alerts_trig[9].p	No	No		No		OUTPUT
ast_alert_o.alerts_trig[10].n	No	No		No		OUTPUT
ast_alert_o.alerts_trig[10].p	No	No		No		OUTPUT
ast_alert_o.alerts_ack[0].n	No	No		No		OUTPUT
ast_alert_o.alerts_ack[0].p	No	No		No		OUTPUT
ast_alert_o.alerts_ack[1].n	No	No		No		OUTPUT
ast_alert_o.alerts_ack[1].p	No	No		No		OUTPUT
ast_alert_o.alerts_ack[2].n	No	No		No		OUTPUT
ast_alert_o.alerts_ack[2].p	No	No		No		OUTPUT
ast_alert_o.alerts_ack[3].n	No	No		No		OUTPUT
ast_alert_o.alerts_ack[3].p	No	No		No		OUTPUT
ast_alert_o.alerts_ack[4].n	No	No		No		OUTPUT
ast_alert_o.alerts_ack[4].p	No	No		No		OUTPUT
ast_alert_o.alerts_ack[5].n	No	No		No		OUTPUT
ast_alert_o.alerts_ack[5].p	No	No		No		OUTPUT
ast_alert_o.alerts_ack[6].n	No	No		No		OUTPUT
ast_alert_o.alerts_ack[6].p	No	No		No		OUTPUT
ast_alert_o.alerts_ack[7].n	No	No		No		OUTPUT
ast_alert_o.alerts_ack[7].p	No	No		No		OUTPUT
ast_alert_o.alerts_ack[8].n	No	No		No		OUTPUT
ast_alert_o.alerts_ack[8].p	No	No		No		OUTPUT
ast_alert_o.alerts_ack[9].n	No	No		No		OUTPUT
ast_alert_o.alerts_ack[9].p	No	No		No		OUTPUT
ast_alert_o.alerts_ack[10].n	No	No		No		OUTPUT
ast_alert_o.alerts_ack[10].p	No	No		No		OUTPUT
ast_status_i.io_pok[1:0]	No	No		Yes	T1,T2,T3	INPUT
ast2pinmux_i[8:0]	Unreachable	Unreachable		Unreachable		INPUT
ast_init_done_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cio_ast_debug_out_o[8:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cio_ast_debug_out_en_o[8:0]	Unreachable	Unreachable		Unreachable		OUTPUT
intr_io_status_change_o	No	No		No		OUTPUT
intr_init_status_change_o	Yes	Yes	T27	Yes	T27	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T27	Yes	T27	INPUT
alert_rx_i[0].ping_n	No	No		No		INPUT
alert_rx_i[0].ping_p	No	No		No		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T27	Yes	T27	INPUT
alert_rx_i[1].ping_n	No	No		No		INPUT
alert_rx_i[1].ping_p	No	No		No		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T27	Yes	T27	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T27	Yes	T27	OUTPUT
wkup_req_o	No	No		No		OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : sensor_ctrl

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	307	2	2	100.00
IF	318	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_systems_sensor_ctrl_0.1/rtl/sensor_ctrl.sv' or '../src/lowrisc_systems_sensor_ctrl_0.1/rtl/sensor_ctrl.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	307	if ((!rst_aon_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	318	if ((!rst_aon_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : sensor_ctrl

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	1	50.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	1	50.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
FpvSecCmRegWeOnehotCheck_A	1973484	0	0	0
NumAlertsMatch_A	16	16	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1973484	0	0	0

NumAlertsMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16	16	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0