Unified Coverage Report :: Group :: tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	3731198	1			T14	2768		T15	6089		T16	957
values[2]	766398	1			T14	360		T15	1471		T16	74
values[3]	108149	1			T14	40		T15	418		T17	2
values[4]	55869	1			T14	57		T15	174		T38	284
values[5]	37660	1			T14	44		T15	125		T38	206
values[6]	27722	1			T14	60		T15	66		T38	195
values[7]	22800	1			T14	39		T15	61		T38	115
values[8]	19636	1			T14	29		T15	43		T38	57
values[9]	17814	1			T14	23		T15	24		T38	46
values[10]	16591	1			T14	31		T15	15		T38	49
values[11]	15367	1			T14	40		T15	12		T38	26
values[12]	14485	1			T14	58		T15	9		T38	23
values[13]	13701	1			T14	52		T15	10		T38	13
values[14]	12772	1			T14	91		T15	4		T38	8
values[15]	12347	1			T14	72		T38	10		T52	38
values[16]	12082	1			T14	47		T38	11		T52	34
values[17]	11662	1			T14	29		T38	15		T52	26
values[18]	11018	1			T14	31		T38	7		T52	26
values[19]	10471	1			T14	31		T38	10		T52	30
values[20]	10077	1			T14	25		T38	5		T52	20
values[21]	9896	1			T14	37		T38	19		T52	15
values[22]	10140	1			T14	48		T38	4		T52	13
values[23]	10060	1			T14	37		T38	8		T52	21
values[24]	9628	1			T14	23		T38	6		T52	22
values[25]	9130	1			T14	32		T38	11		T52	10
values[26]	8802	1			T14	53		T38	21		T52	8
values[27]	8357	1			T14	70		T38	18		T52	6
values[28]	7689	1			T14	34		T38	7		T52	15
values[29]	7420	1			T14	32		T52	2		T98	77
values[30]	6885	1			T14	47		T98	95		T72	2
values[31]	6407	1			T14	52		T98	67		T72	1
values[32]	5819	1			T14	33		T98	57		T72	1
values[33]	5464	1			T14	22		T98	62		T72	1
values[34]	5393	1			T14	13		T98	34		T72	1
values[35]	4755	1			T14	26		T98	26		T72	1
values[36]	4547	1			T14	23		T98	18		T72	1
values[37]	4303	1			T14	7		T98	22		T72	1
values[38]	4141	1			T14	8		T98	20		T72	1
values[39]	3979	1			T14	4		T98	20		T72	1
values[40]	3756	1			T14	4		T98	8		T72	1
values[41]	3642	1			T14	8		T98	3		T72	1
values[42]	3570	1			T14	11		T98	7		T72	3
values[43]	3488	1			T14	5		T98	6		T72	4
values[44]	3564	1			T14	9		T98	3		T72	2
values[45]	3416	1			T14	7		T98	2		T72	1
values[46]	3366	1			T14	6		T98	5		T72	1
values[47]	3319	1			T14	12		T98	4		T72	1
values[48]	3333	1			T14	6		T98	4		T72	1
values[49]	3251	1			T14	6		T98	2		T72	2
values[50]	3237	1			T14	1		T98	5		T72	2
values[51]	3208	1			T14	2		T98	2		T72	1
values[52]	3051	1			T14	5		T98	2		T72	1
values[53]	2988	1			T14	5		T98	2		T72	2
values[54]	3027	1			T14	4		T98	2		T72	1
values[55]	2902	1			T14	1		T98	1		T72	1
values[56]	2848	1			T14	6		T98	2		T72	3
values[57]	2828	1			T14	5		T98	1		T72	2
values[58]	2813	1			T14	2		T98	5		T72	1
values[59]	2702	1			T14	4		T72	1		T291	4
values[60]	2742	1			T72	1		T291	4		T298	3
values[61]	3085	1			T72	7		T291	6		T298	3
values[62]	4819	1			T72	4		T291	7		T298	3
values[63]	19213	1			T72	12		T291	25		T298	50
values[64]	252276	1			T72	119		T291	40		T298	537

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	4843026	1			T14	3776		T15	8345		T16	955
values[2]	812119	1			T14	906		T15	1416		T16	70
values[3]	79043	1			T14	29		T15	298		T16	1
values[4]	14799	1			T14	3		T15	88		T17	4
values[5]	5914	1			T15	49		T38	88		T94	1
values[6]	3632	1			T15	39		T38	91		T72	15
values[7]	2751	1			T15	39		T38	77		T72	25
values[8]	2187	1			T15	30		T38	43		T72	16
values[9]	1927	1			T15	23		T38	42		T72	30
values[10]	1781	1			T15	31		T38	25		T72	16
values[11]	1695	1			T15	16		T38	9		T72	9
values[12]	1591	1			T15	1		T38	17		T72	15
values[13]	1519	1			T15	1		T38	25		T72	17
values[14]	1428	1			T15	1		T38	27		T72	5
values[15]	1400	1			T15	1		T38	31		T72	2
values[16]	1338	1			T15	1		T38	13		T72	4
values[17]	1270	1			T15	4		T38	12		T72	3
values[18]	1138	1			T15	1		T38	10		T72	5
values[19]	1110	1			T15	2		T38	11		T72	7
values[20]	1048	1			T15	1		T38	7		T72	9
values[21]	1057	1			T15	3		T38	4		T72	5
values[22]	1024	1			T15	1		T38	11		T72	12
values[23]	903	1			T15	4		T38	14		T72	17
values[24]	826	1			T15	2		T38	8		T72	9
values[25]	769	1			T15	3		T38	5		T72	5
values[26]	770	1			T15	2		T38	9		T72	3
values[27]	770	1			T15	4		T38	4		T291	3
values[28]	722	1			T15	5		T38	4		T291	2
values[29]	655	1			T15	9		T38	4		T291	3
values[30]	656	1			T15	10		T38	4		T291	2
values[31]	606	1			T38	5		T291	1		T96	3
values[32]	617	1			T38	2		T291	1		T96	2
values[33]	608	1			T38	5		T291	7		T96	3
values[34]	634	1			T38	2		T291	1		T96	2
values[35]	592	1			T38	8		T291	1		T96	2
values[36]	564	1			T38	3		T291	1		T96	1
values[37]	560	1			T38	2		T291	1		T96	1
values[38]	534	1			T38	1		T291	3		T96	2
values[39]	537	1			T38	1		T291	4		T96	1
values[40]	543	1			T38	1		T291	2		T96	2
values[41]	569	1			T38	1		T291	1		T96	1
values[42]	571	1			T38	5		T291	2		T96	1
values[43]	569	1			T38	2		T291	4		T96	1
values[44]	465	1			T38	1		T291	3		T96	1
values[45]	469	1			T38	1		T291	7		T96	2
values[46]	455	1			T38	3		T291	1		T96	2
values[47]	480	1			T38	3		T291	3		T96	3
values[48]	479	1			T38	7		T291	1		T96	3
values[49]	437	1			T38	7		T291	1		T96	1
values[50]	443	1			T38	2		T291	1		T96	3
values[51]	409	1			T38	4		T291	1		T96	1
values[52]	450	1			T38	1		T291	2		T96	3
values[53]	454	1			T38	2		T291	4		T96	1
values[54]	416	1			T38	4		T291	3		T96	3
values[55]	401	1			T38	1		T291	2		T96	3
values[56]	392	1			T38	1		T291	1		T96	2
values[57]	399	1			T38	2		T291	1		T96	1
values[58]	379	1			T38	1		T291	1		T96	2
values[59]	405	1			T38	2		T291	2		T96	1
values[60]	440	1			T38	3		T291	2		T96	1
values[61]	541	1			T38	4		T291	4		T96	8
values[62]	999	1			T38	5		T291	11		T96	14
values[63]	4179	1			T38	15		T291	6		T96	50
values[64]	27515	1			T38	22		T291	4		T96	99

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	597864	1			T14	18		T15	813		T16	8
values[2]	2664646	1			T14	2834		T15	3028		T16	859
values[3]	1160647	1			T14	142		T15	3423		T16	79
values[4]	149532	1			T14	44		T15	491		T17	1
values[5]	75376	1			T14	45		T15	278		T38	300
values[6]	48809	1			T14	29		T15	167		T38	205
values[7]	34577	1			T14	55		T15	132		T38	159
values[8]	27367	1			T14	45		T15	82		T38	160
values[9]	23613	1			T14	68		T15	68		T38	169
values[10]	21097	1			T14	69		T15	70		T38	140
values[11]	19415	1			T14	47		T15	43		T38	103
values[12]	17987	1			T14	30		T15	24		T38	63
values[13]	16645	1			T14	33		T15	15		T38	57
values[14]	15785	1			T14	48		T15	14		T38	41
values[15]	14850	1			T14	41		T15	5		T38	46
values[16]	14846	1			T14	39		T15	3		T38	27
values[17]	14200	1			T14	36		T15	3		T38	16
values[18]	13612	1			T14	39		T38	13		T52	16
values[19]	12808	1			T14	41		T38	16		T52	26
values[20]	12348	1			T14	63		T38	19		T52	18
values[21]	11823	1			T14	80		T38	7		T52	12
values[22]	11485	1			T14	68		T38	6		T52	13
values[23]	10987	1			T14	45		T38	4		T52	9
values[24]	10737	1			T14	41		T38	15		T52	5
values[25]	10297	1			T14	50		T38	9		T52	12
values[26]	9679	1			T14	18		T38	6		T52	5
values[27]	8950	1			T14	32		T38	2		T52	5
values[28]	8467	1			T14	28		T38	3		T52	11
values[29]	8252	1			T14	31		T38	2		T52	6
values[30]	7737	1			T14	24		T38	4		T52	3
values[31]	7018	1			T14	20		T38	2		T52	9
values[32]	6476	1			T14	13		T38	3		T52	7
values[33]	6173	1			T14	13		T38	3		T52	8
values[34]	5721	1			T14	27		T38	3		T52	7
values[35]	5394	1			T14	28		T38	5		T52	6
values[36]	5149	1			T14	35		T38	3		T52	6
values[37]	4891	1			T14	20		T38	4		T52	3
values[38]	4582	1			T14	14		T38	8		T52	2
values[39]	4362	1			T14	14		T38	7		T52	5
values[40]	4244	1			T14	2		T38	3		T52	6
values[41]	4310	1			T14	6		T38	1		T52	2
values[42]	4173	1			T14	6		T38	5		T52	3
values[43]	4108	1			T14	2		T38	3		T52	5
values[44]	4022	1			T14	5		T38	7		T52	6
values[45]	3800	1			T14	8		T38	1		T52	3
values[46]	3832	1			T14	4		T38	3		T98	15
values[47]	3755	1			T14	2		T38	1		T98	20
values[48]	3764	1			T14	4		T38	3		T98	18
values[49]	3665	1			T14	2		T38	1		T98	10
values[50]	3490	1			T14	2		T38	5		T98	17
values[51]	3472	1			T38	2		T98	18		T72	7
values[52]	3396	1			T38	1		T98	13		T72	5
values[53]	3393	1			T38	4		T98	22		T72	3
values[54]	3356	1			T38	6		T98	20		T72	2
values[55]	3278	1			T38	1		T98	6		T72	5
values[56]	3223	1			T38	2		T98	7		T72	2
values[57]	3241	1			T38	2		T98	8		T72	1
values[58]	3137	1			T38	3		T72	2		T298	3
values[59]	2980	1			T38	2		T72	1		T298	3
values[60]	2925	1			T38	3		T72	2		T298	3
values[61]	3292	1			T38	3		T72	1		T298	3
values[62]	4735	1			T38	6		T298	3		T92	20
values[63]	21939	1			T38	22		T298	77		T92	46
values[64]	238565	1			T38	42		T298	517		T92	208