Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64



Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 872009 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 1593623 1 T11 2432 T12 53 T13 321


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 1819687 1 T11 4669 T12 6 T13 85
values[0x0] 308361 1 T11 46 T12 43 T13 208
values[0x1] 337584 1 T11 59 T12 703 T13 1660


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 658940 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 1806692 1 T11 3187 T12 535 T13 1441


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 38271 1 T11 79 T12 5 T13 21
valid_sources[0x01] 38396 1 T11 92 T12 10 T13 25
valid_sources[0x02] 38382 1 T11 86 T13 13 T19 781
valid_sources[0x03] 38349 1 T11 62 T13 24 T19 741
valid_sources[0x04] 38164 1 T11 72 T12 8 T13 35
valid_sources[0x05] 37794 1 T11 72 T12 18 T13 41
valid_sources[0x06] 39336 1 T11 70 T12 6 T13 24
valid_sources[0x07] 38811 1 T11 107 T12 20 T13 40
valid_sources[0x08] 38446 1 T11 66 T12 26 T13 30
valid_sources[0x09] 40961 1 T11 76 T12 4 T13 19
valid_sources[0x0a] 39187 1 T11 71 T13 32 T19 743
valid_sources[0x0b] 38564 1 T11 69 T12 17 T13 30
valid_sources[0x0c] 38515 1 T11 67 T12 3 T13 32
valid_sources[0x0d] 38562 1 T11 69 T12 5 T13 43
valid_sources[0x0e] 38340 1 T11 65 T12 14 T13 43
valid_sources[0x0f] 38433 1 T11 90 T12 23 T13 36
valid_sources[0x10] 38845 1 T11 75 T12 17 T13 52
valid_sources[0x11] 38729 1 T11 65 T12 40 T13 30
valid_sources[0x12] 37831 1 T11 83 T12 9 T13 14
valid_sources[0x13] 38704 1 T11 68 T12 6 T13 38
valid_sources[0x14] 38325 1 T11 73 T12 63 T13 25
valid_sources[0x15] 39125 1 T11 77 T12 15 T13 39
valid_sources[0x16] 38037 1 T11 79 T12 5 T13 32
valid_sources[0x17] 38314 1 T11 84 T12 11 T13 27
valid_sources[0x18] 38840 1 T11 76 T12 10 T13 27
valid_sources[0x19] 38860 1 T11 72 T12 52 T13 21
valid_sources[0x1a] 38694 1 T11 57 T12 8 T13 32
valid_sources[0x1b] 38297 1 T11 73 T12 1 T13 26
valid_sources[0x1c] 39118 1 T11 67 T12 2 T13 31
valid_sources[0x1d] 38817 1 T11 84 T12 3 T13 33
valid_sources[0x1e] 38499 1 T11 78 T12 4 T13 27
valid_sources[0x1f] 38872 1 T11 72 T12 4 T13 30
valid_sources[0x20] 38727 1 T11 75 T12 2 T13 35


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 1076282 1 T11 2328 T12 4 T13 78
values[0x0] all_enables biggest_size 266237 1 T11 46 T12 26 T13 134
values[0x1] all_enables biggest_size 251104 1 T11 58 T12 23 T13 109


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 2862193 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 451977 1 T14 618 T15 30 T16 5


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 1122754 1 T14 1576 T15 176 T16 20
values[0x0] 1069330 1 T14 1490 T15 29 T16 3
values[0x1] 1122086 1 T14 1571 T15 183 T16 23


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 2215530 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 1098640 1 T14 1516 T15 144 T16 18


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 51530 1 T14 76 T15 4 T18 7
valid_sources[0x01] 52275 1 T14 73 T15 5 T38 15
valid_sources[0x02] 50819 1 T14 62 T38 14 T61 24
valid_sources[0x03] 52885 1 T14 65 T15 5 T16 1
valid_sources[0x04] 51064 1 T14 68 T15 3 T18 3
valid_sources[0x05] 50580 1 T14 69 T15 10 T16 2
valid_sources[0x06] 51127 1 T14 80 T15 3 T18 6
valid_sources[0x07] 51375 1 T14 78 T15 5 T18 11
valid_sources[0x08] 52431 1 T14 68 T15 4 T38 11
valid_sources[0x09] 51766 1 T14 72 T15 7 T16 1
valid_sources[0x0a] 51613 1 T14 84 T15 9 T38 13
valid_sources[0x0b] 52078 1 T14 75 T15 7 T38 8
valid_sources[0x0c] 51608 1 T14 58 T15 9 T18 8
valid_sources[0x0d] 52528 1 T14 64 T15 5 T38 12
valid_sources[0x0e] 51871 1 T14 59 T15 10 T16 1
valid_sources[0x0f] 52536 1 T14 77 T15 6 T16 2
valid_sources[0x10] 51608 1 T14 84 T15 11 T38 13
valid_sources[0x11] 51639 1 T14 64 T15 5 T16 2
valid_sources[0x12] 52871 1 T14 79 T15 14 T16 1
valid_sources[0x13] 52355 1 T14 73 T15 4 T38 13
valid_sources[0x14] 52051 1 T14 73 T15 7 T38 17
valid_sources[0x15] 51271 1 T14 78 T15 8 T17 2
valid_sources[0x16] 52659 1 T14 59 T15 8 T16 1
valid_sources[0x17] 51883 1 T14 78 T15 3 T16 4
valid_sources[0x18] 51507 1 T14 70 T15 6 T18 1
valid_sources[0x19] 51398 1 T14 59 T15 7 T16 1
valid_sources[0x1a] 51955 1 T14 84 T15 8 T16 1
valid_sources[0x1b] 51690 1 T14 61 T15 7 T18 7
valid_sources[0x1c] 51602 1 T14 71 T15 1 T16 1
valid_sources[0x1d] 50450 1 T14 63 T15 8 T18 4
valid_sources[0x1e] 51824 1 T14 62 T15 11 T38 12
valid_sources[0x1f] 52267 1 T14 74 T15 2 T38 20
valid_sources[0x20] 51897 1 T14 55 T15 6 T16 1


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 47580 1 T14 51 T15 9 T16 1
values[0x0] all_enables biggest_size 356871 1 T14 494 T15 8 T16 1
values[0x1] all_enables biggest_size 47526 1 T14 73 T15 13 T16 3


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 3054809 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 496587 1 T14 633 T15 44 T16 10


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 1216049 1 T14 1550 T15 220 T16 27
values[0x0] 1119521 1 T14 1549 T15 40 T16 5
values[0x1] 1215826 1 T14 1615 T15 208 T16 20


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 2343581 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 1207815 1 T14 1606 T15 190 T16 18


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 55678 1 T14 67 T15 7 T38 10
valid_sources[0x01] 55391 1 T14 86 T15 11 T17 2
valid_sources[0x02] 55101 1 T14 88 T15 7 T18 1
valid_sources[0x03] 54913 1 T14 60 T15 4 T18 10
valid_sources[0x04] 54558 1 T14 74 T15 9 T38 18
valid_sources[0x05] 54890 1 T14 74 T15 10 T16 1
valid_sources[0x06] 55981 1 T14 74 T15 12 T16 1
valid_sources[0x07] 55884 1 T14 84 T15 6 T16 7
valid_sources[0x08] 55103 1 T14 87 T15 5 T18 13
valid_sources[0x09] 55422 1 T14 54 T15 3 T38 13
valid_sources[0x0a] 54794 1 T14 73 T15 12 T16 1
valid_sources[0x0b] 55149 1 T14 84 T15 3 T17 1
valid_sources[0x0c] 56188 1 T14 80 T15 10 T17 1
valid_sources[0x0d] 56065 1 T14 89 T15 3 T16 4
valid_sources[0x0e] 55478 1 T14 88 T15 5 T17 1
valid_sources[0x0f] 56254 1 T14 64 T15 4 T38 14
valid_sources[0x10] 55659 1 T14 52 T15 4 T38 9
valid_sources[0x11] 55906 1 T14 82 T15 7 T17 1
valid_sources[0x12] 56097 1 T14 81 T15 14 T38 14
valid_sources[0x13] 55315 1 T14 83 T15 12 T18 2
valid_sources[0x14] 55816 1 T14 72 T15 8 T38 24
valid_sources[0x15] 54913 1 T14 70 T15 6 T16 2
valid_sources[0x16] 55705 1 T14 89 T15 8 T18 1
valid_sources[0x17] 55231 1 T14 85 T15 6 T38 9
valid_sources[0x18] 55801 1 T14 74 T15 5 T16 1
valid_sources[0x19] 56390 1 T14 74 T15 6 T17 1
valid_sources[0x1a] 56137 1 T14 69 T15 7 T16 2
valid_sources[0x1b] 55444 1 T14 58 T15 13 T38 14
valid_sources[0x1c] 55577 1 T14 81 T15 6 T16 1
valid_sources[0x1d] 56370 1 T14 64 T15 8 T16 4
valid_sources[0x1e] 55909 1 T14 61 T15 11 T38 17
valid_sources[0x1f] 55633 1 T14 78 T15 5 T16 1
valid_sources[0x20] 55333 1 T14 77 T15 5 T16 1


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 51953 1 T14 60 T15 10 T16 4
values[0x0] all_enables biggest_size 392265 1 T14 501 T15 21 T16 3
values[0x1] all_enables biggest_size 52369 1 T14 72 T15 13 T16 3


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 2879824 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 454068 1 T14 616 T15 35 T16 1


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 1128229 1 T14 1459 T15 188 T16 16
values[0x0] 1075467 1 T14 1486 T15 28 T16 2
values[0x1] 1130196 1 T14 1465 T15 193 T16 26


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 2229892 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 1104000 1 T14 1449 T15 150 T16 20


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 51843 1 T14 40 T15 5 T38 10
valid_sources[0x01] 51894 1 T14 19 T15 5 T38 13
valid_sources[0x02] 51176 1 T14 18 T15 9 T17 1
valid_sources[0x03] 52087 1 T14 50 T15 5 T18 21
valid_sources[0x04] 51556 1 T14 51 T15 5 T38 8
valid_sources[0x05] 52432 1 T14 55 T15 10 T16 3
valid_sources[0x06] 52123 1 T14 83 T15 8 T16 1
valid_sources[0x07] 51725 1 T14 97 T15 11 T38 12
valid_sources[0x08] 51729 1 T14 128 T15 8 T16 3
valid_sources[0x09] 52082 1 T14 82 T15 4 T18 43
valid_sources[0x0a] 51061 1 T14 42 T15 7 T16 2
valid_sources[0x0b] 52008 1 T14 33 T15 3 T38 15
valid_sources[0x0c] 52276 1 T14 113 T15 4 T38 12
valid_sources[0x0d] 53060 1 T14 16 T15 5 T16 1
valid_sources[0x0e] 52368 1 T14 145 T15 10 T38 17
valid_sources[0x0f] 52417 1 T14 38 T15 3 T38 19
valid_sources[0x10] 52165 1 T14 93 T15 11 T16 1
valid_sources[0x11] 50976 1 T14 49 T15 3 T18 19
valid_sources[0x12] 52162 1 T14 125 T15 15 T38 16
valid_sources[0x13] 51836 1 T14 43 T15 4 T16 1
valid_sources[0x14] 51849 1 T14 30 T15 3 T38 12
valid_sources[0x15] 52403 1 T14 99 T15 8 T16 1
valid_sources[0x16] 52141 1 T14 102 T15 3 T16 1
valid_sources[0x17] 51616 1 T14 120 T15 8 T16 1
valid_sources[0x18] 51939 1 T14 55 T15 4 T38 11
valid_sources[0x19] 52828 1 T14 113 T15 5 T16 1
valid_sources[0x1a] 51617 1 T14 44 T15 6 T18 3
valid_sources[0x1b] 52841 1 T14 71 T15 9 T18 3
valid_sources[0x1c] 51971 1 T14 81 T15 8 T16 1
valid_sources[0x1d] 52463 1 T14 74 T15 7 T16 1
valid_sources[0x1e] 52376 1 T14 49 T15 9 T38 16
valid_sources[0x1f] 52105 1 T14 26 T15 4 T18 27
valid_sources[0x20] 51997 1 T14 52 T15 9 T38 18


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 48094 1 T14 68 T15 12 T17 1
values[0x0] all_enables biggest_size 358323 1 T14 490 T15 12 T16 1
values[0x1] all_enables biggest_size 47651 1 T14 58 T15 11 T18 2

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%