Unified Coverage Report :: Module :: hmac

Module : hmac

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.73			98.73

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_hmac	98.73			98.73

---

Module Instance : tb.dut.top_earlgrey.u_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.73			98.73

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.73			98.73

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
84.37	69.18		83.95			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : hmac

	Total	Covered	Percent
Totals	33	31	93.94
Total Bits	314	310	98.73
Total Bits 0->1	157	155	98.73
Total Bits 1->0	157	155	98.73

Ports	33	31	93.94
Port Bits	314	310	98.73
Port Bits 0->1	157	155	98.73
Port Bits 1->0	157	155	98.73

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	INPUT
rst_ni	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	INPUT
tl_i.d_ready	Yes	Yes	T15,T16,T17	Yes	T14,T15,T16	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T15,T16,T17	Yes	T15,T16,T17	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T15,T16,T18	Yes	T15,T16,T18	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T15,T16,T18	Yes	T15,T16,T18	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T15,T16,T17	Yes	T15,T16,T17	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T15,T16,T17	Yes	T15,T16,T17	INPUT
tl_i.a_address[11:0]	Yes	Yes	T15,T16,*T18	Yes	T15,T16,T18	INPUT
tl_i.a_address[15:12]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T15,*T16,*T17	Yes	T15,T16,T17	INPUT
tl_i.a_address[19:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[20]	Yes	Yes	*T15,*T16,*T17	Yes	T15,T16,T17	INPUT
tl_i.a_address[23:21]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[24]	Yes	Yes	*T15,*T16,*T17	Yes	T15,T16,T17	INPUT
tl_i.a_address[29:25]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T15,*T16,*T17	Yes	T15,T16,T17	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	T15,T16,T17	Yes	T15,T16,T17	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T15,T16,T17	Yes	T15,T16,T17	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T15,T16,T17	Yes	T15,T16,T17	INPUT
tl_i.a_valid	Yes	Yes	T15,T16,T17	Yes	T15,T16,T17	INPUT
tl_o.a_ready	Yes	Yes	T15,T17,T18	Yes	T14,T15,T16	OUTPUT
tl_o.d_error	Yes	Yes	T15,T16,T17	Yes	T15,T16,T17	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T15,T16,T17	Yes	T14,T15,T16	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T15,T16,T17	Yes	T15,T16,T17	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T15,T16,T17	Yes	T14,T15,T16	OUTPUT
tl_o.d_sink	Yes	Yes	T15,T16,T17	Yes	T15,T16,T17	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	T15,T16,T17	Yes	T15,T16,T17	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T14,T15,T16	Yes	T15,T16,T17	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T15,*T16,*T17	Yes	T15,T16,T17	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T15,T16,T17	Yes	T15,T16,T17	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T19,T21,T22	Yes	T19,T21,T22	INPUT
alert_rx_i[0].ping_n	No	No		No		INPUT
alert_rx_i[0].ping_p	No	No		No		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T19,T21,T22	Yes	T19,T21,T22	OUTPUT
intr_hmac_done_o	Yes	Yes	T26,T24	Yes	T26,T24	OUTPUT
intr_fifo_empty_o	Yes	Yes	T34,T26,T23	Yes	T34,T26,T23	OUTPUT
intr_hmac_err_o	Yes	Yes	T34,T23,T25	Yes	T34,T23,T25	OUTPUT
idle_o[3:0]	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	OUTPUT

*Tests covering at least one bit in the range