Unified Coverage Report :: Module :: pwm

Module : pwm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.69			98.69

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_pwm_0.1/rtl/pwm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_pwm_aon	98.69			98.69

---

Module Instance : tb.dut.top_earlgrey.u_pwm_aon

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.69			98.69

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.69			98.69

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
84.37	69.18		83.95			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : pwm

	Total	Covered	Percent
Totals	32	30	93.75
Total Bits	306	302	98.69
Total Bits 0->1	153	151	98.69
Total Bits 1->0	153	151	98.69

Ports	32	30	93.75
Port Bits	306	302	98.69
Port Bits 0->1	153	151	98.69
Port Bits 1->0	153	151	98.69

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	INPUT
rst_ni	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	INPUT
clk_core_i	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
rst_core_ni	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	INPUT
tl_i.d_ready	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T15,T16,T17	Yes	T15,T16,T17	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T15,T16,T17	Yes	T15,T16,T17	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
tl_i.a_address[6:0]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
tl_i.a_address[15:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T14,*T15,*T16	Yes	T14,T15,T16	INPUT
tl_i.a_address[17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[18]	Yes	Yes	*T14,*T15,*T16	Yes	T14,T15,T16	INPUT
tl_i.a_address[21:19]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[22]	Yes	Yes	*T14,*T15,*T16	Yes	T14,T15,T16	INPUT
tl_i.a_address[29:23]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T14,*T15,*T16	Yes	T14,T15,T16	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
tl_i.a_valid	Yes	Yes	T15,T16,T17	Yes	T15,T16,T17	INPUT
tl_o.a_ready	Yes	Yes	T15,T17,T18	Yes	T14,T15,T16	OUTPUT
tl_o.d_error	Yes	Yes	T15,T16,T17	Yes	T15,T16,T18	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T15,T16,T17	Yes	T15,T16,T17	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T15,T16,T17	Yes	T15,T16,T17	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T15,T16,T17	Yes	T15,T16,T17	OUTPUT
tl_o.d_sink	Yes	Yes	T15,T16,T17	Yes	T15,T16,T17	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	T15,T16,*T17	Yes	T15,T16,T17	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T15,T16,T17	Yes	T15,T16,T17	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T15,*T18,*T38	Yes	T15,T18,T38	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T15,T16,T17	Yes	T15,T16,T17	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T19,T20,T21	Yes	T19,T20,T21	INPUT
alert_rx_i[0].ping_n	No	No		No		INPUT
alert_rx_i[0].ping_p	No	No		No		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T19,T20,T21	Yes	T19,T20,T21	OUTPUT
cio_pwm_o[5:0]	Yes	Yes	T19,T21,T35	Yes	T19,T21,T35	OUTPUT
cio_pwm_en_o[5:0]	Unreachable	Unreachable		Unreachable		OUTPUT

*Tests covering at least one bit in the range