Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_status_0_en_27.wr_en_data_arb

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_status_0_en_27.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.00	100.00	90.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.00	100.00	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.24	85.71	100.00			100.00		u_mio_pad_sleep_status_0_en_27

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_status_0_en_28.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.00	100.00	90.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.00	100.00	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.24	85.71	100.00			100.00		u_mio_pad_sleep_status_0_en_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_status_0_en_29.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.00	100.00	90.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.00	100.00	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.24	85.71	100.00			100.00		u_mio_pad_sleep_status_0_en_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_status_0_en_30.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.00	100.00	90.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.00	100.00	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.24	85.71	100.00			100.00		u_mio_pad_sleep_status_0_en_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_status_0_en_31.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.00	100.00	90.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.00	100.00	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.24	85.71	100.00			100.00		u_mio_pad_sleep_status_0_en_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_status_1_en_32.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.00	100.00	90.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.00	100.00	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.24	85.71	100.00			100.00		u_mio_pad_sleep_status_1_en_32

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_status_1_en_33.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.00	100.00	90.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.00	100.00	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.24	85.71	100.00			100.00		u_mio_pad_sleep_status_1_en_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_status_1_en_34.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.00	100.00	90.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.00	100.00	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.24	85.71	100.00			100.00		u_mio_pad_sleep_status_1_en_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_status_1_en_35.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.00	100.00	90.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.00	100.00	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.24	85.71	100.00			100.00		u_mio_pad_sleep_status_1_en_35

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_status_1_en_36.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.00	100.00	90.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.00	100.00	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.24	85.71	100.00			100.00		u_mio_pad_sleep_status_1_en_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_status_1_en_37.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.00	100.00	90.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.00	100.00	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.24	85.71	100.00			100.00		u_mio_pad_sleep_status_1_en_37

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_status_1_en_38.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.00	100.00	90.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.00	100.00	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.24	85.71	100.00			100.00		u_mio_pad_sleep_status_1_en_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_status_1_en_39.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.00	100.00	90.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.00	100.00	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.24	85.71	100.00			100.00		u_mio_pad_sleep_status_1_en_39

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_status_0_en_27.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	135	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
113	1	1
135	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_status_0_en_27.wr_en_data_arb

	Total	Covered	Percent
Conditions	10	9	90.00
Logical	10	9	90.00
Non-Logical	0	0
Event	0	0

 LINE       113
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Covered	T20,T35,T64
1	0	Covered	T71,T19,T20

 LINE       135
 EXPRESSION ((de ? d : q) & (we ? wd : '1))
             ------1-----   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Not Covered
1	1	Covered	T20,T35,T64

 LINE       135
 SUB-EXPRESSION (de ? d : q)
                 -1

-1-	Status	Tests
0	Covered	T14,T15,T16
1	Covered	T20,T35,T64

 LINE       135
 SUB-EXPRESSION (we ? wd : '1)
                 -1

-1-	Status	Tests
0	Covered	T14,T15,T16
1	Covered	T71,T19,T20

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_status_0_en_28.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	135	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
113	1	1
135	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_status_0_en_28.wr_en_data_arb

	Total	Covered	Percent
Conditions	10	9	90.00
Logical	10	9	90.00
Non-Logical	0	0
Event	0	0

 LINE       113
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Covered	T20,T21,T22
1	0	Covered	T71,T19,T20

 LINE       135
 EXPRESSION ((de ? d : q) & (we ? wd : '1))
             ------1-----   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Not Covered
1	1	Covered	T20,T21,T22

 LINE       135
 SUB-EXPRESSION (de ? d : q)
                 -1

-1-	Status	Tests
0	Covered	T14,T15,T16
1	Covered	T20,T21,T22

 LINE       135
 SUB-EXPRESSION (we ? wd : '1)
                 -1

-1-	Status	Tests
0	Covered	T14,T15,T16
1	Covered	T71,T19,T20

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_status_0_en_29.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	135	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
113	1	1
135	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_status_0_en_29.wr_en_data_arb

	Total	Covered	Percent
Conditions	10	9	90.00
Logical	10	9	90.00
Non-Logical	0	0
Event	0	0

 LINE       113
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Covered	T19,T20,T21
1	0	Covered	T71,T19,T20

 LINE       135
 EXPRESSION ((de ? d : q) & (we ? wd : '1))
             ------1-----   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Not Covered
1	1	Covered	T19,T20,T21

 LINE       135
 SUB-EXPRESSION (de ? d : q)
                 -1

-1-	Status	Tests
0	Covered	T14,T15,T16
1	Covered	T19,T20,T21

 LINE       135
 SUB-EXPRESSION (we ? wd : '1)
                 -1

-1-	Status	Tests
0	Covered	T14,T15,T16
1	Covered	T71,T19,T20

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_status_0_en_30.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	135	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
113	1	1
135	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_status_0_en_30.wr_en_data_arb

	Total	Covered	Percent
Conditions	10	9	90.00
Logical	10	9	90.00
Non-Logical	0	0
Event	0	0

 LINE       113
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Covered	T19,T21,T35
1	0	Covered	T71,T19,T20

 LINE       135
 EXPRESSION ((de ? d : q) & (we ? wd : '1))
             ------1-----   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Not Covered
1	1	Covered	T19,T21,T35

 LINE       135
 SUB-EXPRESSION (de ? d : q)
                 -1

-1-	Status	Tests
0	Covered	T14,T15,T16
1	Covered	T19,T21,T35

 LINE       135
 SUB-EXPRESSION (we ? wd : '1)
                 -1

-1-	Status	Tests
0	Covered	T14,T15,T16
1	Covered	T71,T19,T20

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_status_0_en_31.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	135	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
113	1	1
135	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_status_0_en_31.wr_en_data_arb

	Total	Covered	Percent
Conditions	10	9	90.00
Logical	10	9	90.00
Non-Logical	0	0
Event	0	0

 LINE       113
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Covered	T35,T66,T58
1	0	Covered	T71,T19,T20

 LINE       135
 EXPRESSION ((de ? d : q) & (we ? wd : '1))
             ------1-----   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Not Covered
1	1	Covered	T35,T66,T58

 LINE       135
 SUB-EXPRESSION (de ? d : q)
                 -1

-1-	Status	Tests
0	Covered	T14,T15,T16
1	Covered	T35,T66,T58

 LINE       135
 SUB-EXPRESSION (we ? wd : '1)
                 -1

-1-	Status	Tests
0	Covered	T14,T15,T16
1	Covered	T71,T19,T20

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_status_1_en_32.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	135	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
113	1	1
135	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_status_1_en_32.wr_en_data_arb

	Total	Covered	Percent
Conditions	10	9	90.00
Logical	10	9	90.00
Non-Logical	0	0
Event	0	0

 LINE       113
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Covered	T19,T21,T35
1	0	Covered	T19,T115,T86

 LINE       135
 EXPRESSION ((de ? d : q) & (we ? wd : '1))
             ------1-----   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Not Covered
1	1	Covered	T19,T21,T35

 LINE       135
 SUB-EXPRESSION (de ? d : q)
                 -1

-1-	Status	Tests
0	Covered	T14,T15,T16
1	Covered	T19,T21,T35

 LINE       135
 SUB-EXPRESSION (we ? wd : '1)
                 -1

-1-	Status	Tests
0	Covered	T14,T15,T16
1	Covered	T19,T115,T86

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_status_1_en_33.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	135	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
113	1	1
135	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_status_1_en_33.wr_en_data_arb

	Total	Covered	Percent
Conditions	10	9	90.00
Logical	10	9	90.00
Non-Logical	0	0
Event	0	0

 LINE       113
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Covered	T19,T20,T35
1	0	Covered	T19,T115,T86

 LINE       135
 EXPRESSION ((de ? d : q) & (we ? wd : '1))
             ------1-----   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Not Covered
1	1	Covered	T19,T20,T35

 LINE       135
 SUB-EXPRESSION (de ? d : q)
                 -1

-1-	Status	Tests
0	Covered	T14,T15,T16
1	Covered	T19,T20,T35

 LINE       135
 SUB-EXPRESSION (we ? wd : '1)
                 -1

-1-	Status	Tests
0	Covered	T14,T15,T16
1	Covered	T19,T115,T86

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_status_1_en_34.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	135	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
113	1	1
135	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_status_1_en_34.wr_en_data_arb

	Total	Covered	Percent
Conditions	10	9	90.00
Logical	10	9	90.00
Non-Logical	0	0
Event	0	0

 LINE       113
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Covered	T19,T36,T57
1	0	Covered	T19,T115,T86

 LINE       135
 EXPRESSION ((de ? d : q) & (we ? wd : '1))
             ------1-----   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Not Covered
1	1	Covered	T19,T36,T57

 LINE       135
 SUB-EXPRESSION (de ? d : q)
                 -1

-1-	Status	Tests
0	Covered	T14,T15,T16
1	Covered	T19,T36,T57

 LINE       135
 SUB-EXPRESSION (we ? wd : '1)
                 -1

-1-	Status	Tests
0	Covered	T14,T15,T16
1	Covered	T19,T115,T86

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_status_1_en_35.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	135	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
113	1	1
135	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_status_1_en_35.wr_en_data_arb

	Total	Covered	Percent
Conditions	10	9	90.00
Logical	10	9	90.00
Non-Logical	0	0
Event	0	0

 LINE       113
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Covered	T19,T21,T22
1	0	Covered	T19,T115,T86

 LINE       135
 EXPRESSION ((de ? d : q) & (we ? wd : '1))
             ------1-----   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Not Covered
1	1	Covered	T19,T21,T22

 LINE       135
 SUB-EXPRESSION (de ? d : q)
                 -1

-1-	Status	Tests
0	Covered	T14,T15,T16
1	Covered	T19,T21,T22

 LINE       135
 SUB-EXPRESSION (we ? wd : '1)
                 -1

-1-	Status	Tests
0	Covered	T14,T15,T16
1	Covered	T19,T115,T86

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_status_1_en_36.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	135	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
113	1	1
135	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_status_1_en_36.wr_en_data_arb

	Total	Covered	Percent
Conditions	10	9	90.00
Logical	10	9	90.00
Non-Logical	0	0
Event	0	0

 LINE       113
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Covered	T40,T56,T106
1	0	Covered	T19,T115,T86

 LINE       135
 EXPRESSION ((de ? d : q) & (we ? wd : '1))
             ------1-----   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Not Covered
1	1	Covered	T40,T56,T106

 LINE       135
 SUB-EXPRESSION (de ? d : q)
                 -1

-1-	Status	Tests
0	Covered	T14,T15,T16
1	Covered	T40,T56,T106

 LINE       135
 SUB-EXPRESSION (we ? wd : '1)
                 -1

-1-	Status	Tests
0	Covered	T14,T15,T16
1	Covered	T19,T115,T86

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_status_1_en_37.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	135	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
113	1	1
135	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_status_1_en_37.wr_en_data_arb

	Total	Covered	Percent
Conditions	10	9	90.00
Logical	10	9	90.00
Non-Logical	0	0
Event	0	0

 LINE       113
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Covered	T20,T35,T65
1	0	Covered	T19,T115,T86

 LINE       135
 EXPRESSION ((de ? d : q) & (we ? wd : '1))
             ------1-----   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Not Covered
1	1	Covered	T20,T35,T65

 LINE       135
 SUB-EXPRESSION (de ? d : q)
                 -1

-1-	Status	Tests
0	Covered	T14,T15,T16
1	Covered	T20,T35,T65

 LINE       135
 SUB-EXPRESSION (we ? wd : '1)
                 -1

-1-	Status	Tests
0	Covered	T14,T15,T16
1	Covered	T19,T115,T86

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_status_1_en_38.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	135	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
113	1	1
135	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_status_1_en_38.wr_en_data_arb

	Total	Covered	Percent
Conditions	10	9	90.00
Logical	10	9	90.00
Non-Logical	0	0
Event	0	0

 LINE       113
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Covered	T21,T22,T36
1	0	Covered	T19,T115,T86

 LINE       135
 EXPRESSION ((de ? d : q) & (we ? wd : '1))
             ------1-----   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Not Covered
1	1	Covered	T21,T22,T36

 LINE       135
 SUB-EXPRESSION (de ? d : q)
                 -1

-1-	Status	Tests
0	Covered	T14,T15,T16
1	Covered	T21,T22,T36

 LINE       135
 SUB-EXPRESSION (we ? wd : '1)
                 -1

-1-	Status	Tests
0	Covered	T14,T15,T16
1	Covered	T19,T115,T86

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_status_1_en_39.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	135	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
113	1	1
135	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_status_1_en_39.wr_en_data_arb

	Total	Covered	Percent
Conditions	10	9	90.00
Logical	10	9	90.00
Non-Logical	0	0
Event	0	0

 LINE       113
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Covered	T20,T66,T36
1	0	Covered	T19,T115,T86

 LINE       135
 EXPRESSION ((de ? d : q) & (we ? wd : '1))
             ------1-----   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Not Covered
1	1	Covered	T20,T66,T36

 LINE       135
 SUB-EXPRESSION (de ? d : q)
                 -1

-1-	Status	Tests
0	Covered	T14,T15,T16
1	Covered	T20,T66,T36

 LINE       135
 SUB-EXPRESSION (we ? wd : '1)
                 -1

-1-	Status	Tests
0	Covered	T14,T15,T16
1	Covered	T19,T115,T86