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Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_mode_16.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_mio_pad_sleep_mode_16


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_mode_17.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_mio_pad_sleep_mode_17


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_mode_18.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_mio_pad_sleep_mode_18


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_mode_19.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_mio_pad_sleep_mode_19


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_mode_20.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_mio_pad_sleep_mode_20


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_mode_21.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_mio_pad_sleep_mode_21


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_mode_22.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_mio_pad_sleep_mode_22


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_mode_23.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_mio_pad_sleep_mode_23


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_mode_24.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_mio_pad_sleep_mode_24


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_mode_25.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_mio_pad_sleep_mode_25


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_mode_26.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_mio_pad_sleep_mode_26


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_mode_27.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_mio_pad_sleep_mode_27


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_mode_28.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_mio_pad_sleep_mode_28


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Go back
Module Instances:
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_mode_16.wr_en_data_arb
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_mode_17.wr_en_data_arb
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_mode_18.wr_en_data_arb
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_mode_19.wr_en_data_arb
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_mode_20.wr_en_data_arb
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_mode_21.wr_en_data_arb
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_mode_22.wr_en_data_arb
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_mode_23.wr_en_data_arb
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_mode_24.wr_en_data_arb
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_mode_25.wr_en_data_arb
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_mode_26.wr_en_data_arb
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_mode_27.wr_en_data_arb
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_mode_28.wr_en_data_arb
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_mode_16.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
33 1 1
34 1 1
39 unreachable

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_mode_16.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT14,T15,T16
01Unreachable
10CoveredT19,T110,T85 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT14,T15,T16
1CoveredT19,T110,T85 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT14,T15,T16
1CoveredT19,T110,T85
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_mode_16.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	34	((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T19,T110,T85
0 Covered T14,T15,T16

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_mode_17.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
33 1 1
34 1 1
39 unreachable

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_mode_17.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT14,T15,T16
01Unreachable
10CoveredT79,T19,T88 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT14,T15,T16
1CoveredT79,T19,T88 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT14,T15,T16
1CoveredT79,T19,T88
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_mode_17.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	34	((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T79,T19,T88
0 Covered T14,T15,T16

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_mode_18.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
33 1 1
34 1 1
39 unreachable

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_mode_18.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT14,T15,T16
01Unreachable
10CoveredT19,T85,T20 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT14,T15,T16
1CoveredT19,T85,T20 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT14,T15,T16
1CoveredT19,T85,T20
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_mode_18.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	34	((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T19,T85,T20
0 Covered T14,T15,T16

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_mode_19.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
33 1 1
34 1 1
39 unreachable

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_mode_19.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT14,T15,T16
01Unreachable
10CoveredT92,T70,T19 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT14,T15,T16
1CoveredT92,T70,T19 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT14,T15,T16
1CoveredT92,T70,T19
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_mode_19.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	34	((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T92,T70,T19
0 Covered T14,T15,T16

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_mode_20.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
33 1 1
34 1 1
39 unreachable

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_mode_20.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT14,T15,T16
01Unreachable
10CoveredT94,T92,T70 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT14,T15,T16
1CoveredT94,T92,T70 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT14,T15,T16
1CoveredT94,T92,T70
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_mode_20.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	34	((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T94,T92,T70
0 Covered T14,T15,T16

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_mode_21.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
33 1 1
34 1 1
39 unreachable

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_mode_21.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT14,T15,T16
01Unreachable
10CoveredT92,T81,T19 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT14,T15,T16
1CoveredT92,T81,T19 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT14,T15,T16
1CoveredT92,T81,T19
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_mode_21.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	34	((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T92,T81,T19
0 Covered T14,T15,T16

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_mode_22.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
33 1 1
34 1 1
39 unreachable

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_mode_22.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT14,T15,T16
01Unreachable
10CoveredT115,T20,T21 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT14,T15,T16
1CoveredT115,T20,T21 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT14,T15,T16
1CoveredT115,T20,T21
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_mode_22.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	34	((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T115,T20,T21
0 Covered T14,T15,T16

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_mode_23.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
33 1 1
34 1 1
39 unreachable

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_mode_23.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT14,T15,T16
01Unreachable
10CoveredT14,T97,T96 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT14,T15,T16
1CoveredT14,T97,T96 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT14,T15,T16
1CoveredT14,T97,T96
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_mode_23.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	34	((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T14,T97,T96
0 Covered T14,T15,T16

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_mode_24.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
33 1 1
34 1 1
39 unreachable

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_mode_24.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT14,T15,T16
01Unreachable
10CoveredT200,T19,T20 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT14,T15,T16
1CoveredT200,T19,T20 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT14,T15,T16
1CoveredT200,T19,T20
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_mode_24.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	34	((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T200,T19,T20
0 Covered T14,T15,T16

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_mode_25.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
33 1 1
34 1 1
39 unreachable

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_mode_25.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT14,T15,T16
01Unreachable
10CoveredT81,T130,T20 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT14,T15,T16
1CoveredT81,T130,T20 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT14,T15,T16
1CoveredT81,T130,T20
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_mode_25.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	34	((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T81,T130,T20
0 Covered T14,T15,T16

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_mode_26.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
33 1 1
34 1 1
39 unreachable

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_mode_26.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT14,T15,T16
01Unreachable
10CoveredT19,T20,T201 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT14,T15,T16
1CoveredT19,T20,T201 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT14,T15,T16
1CoveredT19,T20,T201
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_mode_26.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	34	((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T19,T20,T201
0 Covered T14,T15,T16

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_mode_27.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
33 1 1
34 1 1
39 unreachable

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_mode_27.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT14,T15,T16
01Unreachable
10CoveredT72,T75,T88 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT14,T15,T16
1CoveredT72,T75,T88 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT14,T15,T16
1CoveredT72,T75,T88
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_mode_27.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	34	((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T72,T75,T88
0 Covered T14,T15,T16

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_mode_28.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
33 1 1
34 1 1
39 unreachable

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_mode_28.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT14,T15,T16
01Unreachable
10CoveredT14,T19,T88 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT14,T15,T16
1CoveredT14,T19,T88 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT14,T15,T16
1CoveredT14,T19,T88
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_mode_28.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	34	((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T14,T19,T88
0 Covered T14,T15,T16

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%