Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	438	1			T16	5		T31	2		T53	1
all_values[1]	447	1			T16	1		T31	1		T53	1
all_values[2]	421	1			T16	2		T31	1		T53	1
all_values[3]	458	1			T16	2		T53	4		T207	1
all_values[4]	429	1			T16	2		T31	1		T53	2
all_values[5]	428	1			T16	2		T31	1		T53	6
all_values[6]	460	1			T31	1		T53	2		T77	3
all_values[7]	432	1			T16	1		T31	1		T53	1
all_values[8]	435	1			T16	3		T31	2		T53	1
all_values[9]	472	1			T31	2		T53	3		T207	1
all_values[10]	397	1			T31	1		T53	1		T77	4
all_values[11]	456	1			T16	4		T53	3		T207	1
all_values[12]	424	1			T16	1		T53	6		T207	1
all_values[13]	499	1			T16	1		T31	2		T53	3
all_values[14]	445	1			T16	2		T53	3		T207	1
all_values[15]	401	1			T16	2		T53	1		T77	3
all_values[16]	458	1			T77	7		T81	2		T209	1
all_values[17]	400	1			T16	3		T31	1		T53	5
all_values[18]	435	1			T16	3		T31	1		T53	3
all_values[19]	452	1			T16	2		T31	4		T53	2
all_values[20]	432	1			T16	1		T77	1		T78	1
all_values[21]	408	1			T16	2		T31	2		T53	4
all_values[22]	435	1			T16	1		T31	1		T53	2
all_values[23]	410	1			T16	2		T53	4		T77	4
all_values[24]	394	1			T16	1		T207	1		T77	2
all_values[25]	420	1			T16	1		T31	1		T53	2
all_values[26]	441	1			T16	3		T53	3		T77	6
all_values[27]	460	1			T16	2		T53	4		T77	2
all_values[28]	429	1			T31	1		T53	1		T77	3
all_values[29]	435	1			T16	1		T31	1		T77	2
all_values[30]	415	1			T16	1		T31	1		T53	3
all_values[31]	403	1			T16	2		T31	1		T53	1
all_values[32]	458	1			T16	4		T53	4		T71	3
all_values[33]	442	1			T16	2		T31	1		T53	1
all_values[34]	423	1			T16	3		T53	4		T77	2
all_values[35]	446	1			T31	1		T53	2		T207	1
all_values[36]	446	1			T16	1		T53	3		T77	2
all_values[37]	449	1			T16	4		T31	4		T53	4
all_values[38]	440	1			T31	1		T53	4		T71	1
all_values[39]	429	1			T16	1		T31	3		T53	1
all_values[40]	426	1			T16	2		T31	1		T53	1
all_values[41]	462	1			T16	2		T31	1		T53	2
all_values[42]	436	1			T53	2		T207	1		T77	1
all_values[43]	435	1			T16	3		T31	1		T53	2
all_values[44]	451	1			T16	1		T31	1		T53	3
all_values[45]	473	1			T16	1		T31	1		T53	2
all_values[46]	427	1			T53	1		T77	1		T78	1
all_values[47]	442	1			T16	2		T31	1		T53	3
all_values[48]	421	1			T16	1		T31	1		T53	2
all_values[49]	435	1			T16	2		T31	3		T53	2