Design Module List
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Total Module Definition Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
73.82 84.00 77.41 67.51 65.81 74.36


Total modules in report: 108
modlist.html | modlist1.html
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
pinmux_jtag_breakout 0.00 0.00 0.00
prim_mubi4_dec 0.00 0.00
prim_sync_reqack_data 0.00 0.00 0.00
prim_arbiter_fixed 3.45 0.00 6.67 0.00 7.14
csrng 18.29 18.29
ibex_top 20.68 20.68
pinmux_wkup 25.56 26.32 23.08 27.27
edn 26.20 26.20
entropy_src 32.68 32.68
prim_edn_req 35.19 50.00 30.77 60.00 0.00
tlul_adapter_host 35.23 53.06 30.09 57.78 0.00
tlul_adapter_host 0.00 0.00
tlul_adapter_host ( parameter MAX_REQS=2,EnableDataIntgGen=1,EnableRspDataIntgCheck=0,WordSize=2,OutstandingReqCntW=2,g_multiple_reqs.ReqNumW=1 + MAX_REQS=2,EnableDataIntgGen=0,EnableRspDataIntgCheck=0,WordSize=2,OutstandingReqCntW=2,g_multiple_reqs.ReqNumW=1 ) 51.54 65.22 29.41 60.00
tlul_adapter_host ( parameter MAX_REQS=8,EnableDataIntgGen=0,EnableRspDataIntgCheck=0,WordSize=2,OutstandingReqCntW=4,g_multiple_reqs.ReqNumW=3 ) 42.41 40.91 30.77 55.56
flash_ctrl 36.00 36.00
rv_core_addr_trans 36.58 1.41 58.33 50.00
rv_core_ibex 42.43 30.59 14.29 61.58 58.33 47.37
kmac 47.62 47.62
sensor_ctrl 49.50 23.29 16.95 57.27 100.00 50.00
padring 49.72 49.72
tlul_err_resp 49.87 57.69 36.36 55.56
prim_generic_usb_diff_rx 50.00 66.67 33.33 50.00
lc_ctrl 50.01 50.01
sram_ctrl 51.99 51.99
otp_ctrl 52.87 52.87
prim_packer_fifo 53.31 81.82 60.00 71.43 0.00
prim_alert_sender 58.33 58.33
prim_max_tree 59.51 40.08 39.21 58.77 100.00
pinmux 60.40 72.17 50.73 63.36 34.96 80.77
prim_reg_cdc_arb 62.37 93.00 82.56 73.91 0.00
prim_reg_cdc_arb 36.96 73.91 0.00
prim_reg_cdc_arb ( parameter DataWidth=10,ResetVal=0,DstWrReq=1 + DataWidth=4,ResetVal,DstWrReq=1 + DataWidth=1,ResetVal=0,DstWrReq=1 + DataWidth=14,ResetVal=0,DstWrReq=1 + DataWidth=28,ResetVal=0,DstWrReq=1 + DataWidth=8,ResetVal=0,DstWrReq=1 + DataWidth=32,ResetVal=0,DstWrReq=1 ) 75.56 86.00 65.12
prim_reg_cdc_arb ( parameter DataWidth=2,ResetVal=0,DstWrReq=0 + DataWidth=20,ResetVal,DstWrReq=0 + DataWidth=18,ResetVal=118010,DstWrReq=0 + DataWidth=16,ResetVal,DstWrReq=0 + DataWidth=1,ResetVal=0,DstWrReq=0 + DataWidth=12,ResetVal=0,DstWrReq=0 + DataWidth=8,ResetVal,DstWrReq=0 + DataWidth=14,ResetVal=0,DstWrReq=0 + DataWidth=17,ResetVal=2000,DstWrReq=0 + DataWidth=7,ResetVal=0,DstWrReq=0 + DataWidth=5,ResetVal=0,DstWrReq=0 + DataWidth=32,ResetVal,DstWrReq=0 + DataWidth=4,ResetVal=0,DstWrReq=0 + DataWidth=6,ResetVal=0,DstWrReq=0 + DataWidth=13,ResetVal=0,DstWrReq=0 ) 100.00 100.00 100.00
ast 67.92 67.92
rv_plic_gateway 69.17 100.00 20.00 87.50
keymgr 70.13 70.13
chip_earlgrey_asic 70.96 72.73 50.00 90.14
alert_handler 72.25 72.25
usbdev_aon_wake 72.41 68.57 63.16 57.89 100.00
rv_plic 73.94 46.15 66.67 93.00 75.00 88.89
top_earlgrey 73.95 68.10 53.75 100.00
otbn 76.26 76.26
spi_device 82.41 82.41
prim_generic_clock_mux2 85.19 100.00 55.56 100.00
prim_esc_receiver 85.71 85.71
usbdev 86.19 86.19
clkmgr 88.89 88.89
spi_host 89.39 89.39
prim_intr_hw 89.58 100.00 58.33 100.00 100.00
sensor_ctrl_reg_top 90.69 97.33 71.67 93.75 100.00
adc_ctrl 90.74 90.74
tlul_rsp_intg_gen 91.67 83.33 100.00
tlul_rsp_intg_gen 100.00 100.00
tlul_rsp_intg_gen ( parameter EnableRspIntgGen=0,EnableDataIntgGen=0 ) 66.67 66.67
tlul_rsp_intg_gen ( parameter EnableRspIntgGen=1,EnableDataIntgGen=1 ) 100.00 100.00
prim_sync_reqack 91.67 100.00 66.67 100.00 100.00
pwrmgr 92.39 92.39
clk_ctrl_and_main_pd_sva_if 92.86 92.86
tlul_rsp_intg_chk 93.33 100.00 80.00 100.00
aes 93.38 93.38
rstmgr 93.84 93.84
prim_edge_detector 94.44 100.00 83.33 100.00
prim_reg_cdc 94.51 100.00 78.02 100.00 100.00
prim_reg_cdc 100.00 100.00 100.00 100.00
prim_reg_cdc ( parameter DataWidth=1,ResetVal=0,BitMask=1,DstWrReq=0,TxnWidth=3 + DataWidth=1,ResetVal=0,BitMask=1,DstWrReq=1,TxnWidth=3 ) 84.62 84.62
prim_reg_cdc ( parameter DataWidth=2,ResetVal=0,BitMask=3,DstWrReq=0,TxnWidth=3 + DataWidth=10,ResetVal=0,BitMask=769,DstWrReq=1,TxnWidth=3 + DataWidth=4,ResetVal,BitMask=15,DstWrReq=1,TxnWidth=3 + DataWidth=20,ResetVal,BitMask=1048575,DstWrReq=0,TxnWidth=3 + DataWidth=18,ResetVal=118010,BitMask=262143,DstWrReq=0,TxnWidth=3 + DataWidth=16,ResetVal,BitMask=65535,DstWrReq=0,TxnWidth=3 + DataWidth=12,ResetVal=0,BitMask=4095,DstWrReq=0,TxnWidth=3 + DataWidth=8,ResetVal,BitMask=255,DstWrReq=0,TxnWidth=3 + DataWidth=14,ResetVal=0,BitMask=16383,DstWrReq=0,TxnWidth=3 + DataWidth=17,ResetVal=2000,BitMask=131071,DstWrReq=0,TxnWidth=3 + DataWidth=7,ResetVal=0,BitMask=119,DstWrReq=0,TxnWidth=3 + DataWidth=5,ResetVal=0,BitMask=31,DstWrReq=0,TxnWidth=3 + DataWidth=32,ResetVal,BitMask,DstWrReq=0,TxnWidth=3 + DataWidth=4,ResetVal=0,BitMask=15,DstWrReq=0,TxnWidth=3 + DataWidth=14,ResetVal=0,BitMask=16383,DstWrReq=1,TxnWidth=3 + DataWidth=28,ResetVal=0,BitMask=268374015,DstWrReq=1,TxnWidth=3 + DataWidth=8,ResetVal=0,BitMask=255,DstWrReq=1,TxnWidth=3 + DataWidth=6,ResetVal=0,BitMask=63,DstWrReq=0,TxnWidth=3 + DataWidth=13,ResetVal=0,BitMask=8191,DstWrReq=0,TxnWidth=3 + DataWidth=32,ResetVal=0,BitMask=-1,DstWrReq=1,TxnWidth=3 ) 71.43 71.43
tlul_socket_1n 95.64 94.64 93.18 94.74 100.00
pinmux_strap_sampling 95.93 96.37 100.00 93.22 94.12
aon_timer 96.18 96.18
rv_plic_target 96.30 88.89 100.00 100.00
rom_ctrl 97.08 97.08
pattgen 97.33 97.33
sysrst_ctrl 98.20 98.20
rv_timer 98.63 98.63
pwm 98.69 98.69
uart 98.69 98.69
hmac 98.73 98.73
i2c 98.78 98.78
rv_core_ibex_cfg_reg_top 98.83 99.44 98.72 97.14 100.00
pinmux_reg_top 99.03 99.16 97.14 99.83 100.00
rv_dm 99.12 99.12
gpio 99.26 99.26
tlul_adapter_reg 99.49 100.00 97.96 100.00 100.00
rv_plic_reg_top 99.80 99.94 99.75 99.52 100.00
prim_lc_sync 100.00 100.00 100.00
prim_lc_sync 100.00 100.00
prim_lc_sync ( parameter NumCopies=1,AsyncOn=1,ResetValueIsOn=0,LcResetValue=10 ) 100.00 100.00
prim_lc_sync ( parameter NumCopies=2,AsyncOn=1,ResetValueIsOn=0,LcResetValue=10 ) 100.00 100.00
prim_lc_sync ( parameter NumCopies=3,AsyncOn=0,ResetValueIsOn=0,LcResetValue=10 ) 100.00 100.00
prim_lc_sync ( parameter NumCopies=4,AsyncOn=0,ResetValueIsOn=0,LcResetValue=10 ) 100.00 100.00
prim_lc_sender 100.00 100.00
tlul_data_integ_dec 100.00 100.00
tlul_cmd_intg_chk 100.00 100.00 100.00
tlul_cmd_intg_gen 100.00 100.00 100.00
tlul_fifo_sync 100.00 100.00 100.00
prim_subreg 100.00 100.00 100.00 100.00
prim_subreg 100.00 100.00 100.00
prim_subreg ( parameter DW=1,SwAccess=3,RESVAL,Mubi=0 + DW=1,SwAccess=0,RESVAL,Mubi=0 + DW=1,SwAccess=1,RESVAL,Mubi=0 + DW=1,SwAccess=5,RESVAL,Mubi=0 + DW=1,SwAccess=4,RESVAL=0,Mubi=0 ) 100.00 100.00
prim_subreg ( parameter DW=2,SwAccess=0,RESVAL,Mubi=0 + DW=2,SwAccess=1,RESVAL=0,Mubi=0 + DW=2,SwAccess=3,RESVAL=0,Mubi=0 ) 100.00 100.00
prim_subreg ( parameter DW=3,SwAccess=0,RESVAL,Mubi=0 + DW=3,SwAccess=1,RESVAL,Mubi=0 + DW=3,SwAccess=3,RESVAL=0,Mubi=0 ) 100.00 100.00
prim_subreg ( parameter DW=32,SwAccess=1,RESVAL,Mubi=0 + DW=32,SwAccess=0,RESVAL,Mubi=0 + DW=32,SwAccess=3,RESVAL=0,Mubi=0 ) 100.00 100.00
prim_subreg ( parameter DW=4,SwAccess=0,RESVAL,Mubi + DW=4,SwAccess=1,RESVAL=0,Mubi=0 + DW=4,SwAccess=4,RESVAL=9,Mubi=1 ) 100.00 100.00
prim_subreg ( parameter DW=6,SwAccess=0,RESVAL,Mubi=0 + DW=6,SwAccess=1,RESVAL=0,Mubi=0 ) 100.00 100.00
prim_subreg ( parameter DW=7,SwAccess=1,RESVAL=0,Mubi=0 + DW=7,SwAccess=0,RESVAL,Mubi=0 ) 100.00 100.00
prim_subreg ( parameter DW=8,SwAccess=0,RESVAL,Mubi=0 + DW=8,SwAccess=1,RESVAL,Mubi=0 + DW=8,SwAccess=3,RESVAL=0,Mubi=0 ) 100.00 100.00
prim_filter 100.00 100.00 100.00 100.00
prim_lc_or_hardened 100.00 100.00 100.00 100.00
prim_generic_buf 100.00 100.00
prim_pulse_sync 100.00 100.00 100.00 100.00 100.00
prim_fifo_sync 100.00 100.00 100.00
prim_subreg_arb 100.00 100.00 100.00 100.00
prim_subreg_arb 100.00 100.00
prim_subreg_arb ( parameter DW=1,SwAccess=0,Mubi=0 ) 100.00 100.00
prim_subreg_arb ( parameter DW=1,SwAccess=3,Mubi=0 ) 100.00 100.00
prim_subreg_arb ( parameter DW=1,SwAccess=3,Mubi=0 + DW=32,SwAccess=3,Mubi=0 + DW=3,SwAccess=3,Mubi=0 + DW=10,SwAccess=3,Mubi=0 + DW=5,SwAccess=3,Mubi=0 + DW=8,SwAccess=3,Mubi=0 + DW=2,SwAccess=3,Mubi=0 ) 100.00 100.00
prim_subreg_arb ( parameter DW=1,SwAccess=4,Mubi=0 ) 100.00 100.00 100.00
prim_subreg_arb ( parameter DW=1,SwAccess=5,Mubi=0 ) 100.00 100.00
prim_subreg_arb ( parameter DW=1,SwAccess=5,Mubi=0 + DW=16,SwAccess=5,Mubi=0 ) 100.00 100.00
prim_subreg_arb ( parameter DW=2,SwAccess=0,Mubi=0 ) 100.00 100.00
prim_subreg_arb ( parameter DW=3,SwAccess=0,Mubi=0 ) 100.00 100.00
prim_subreg_arb ( parameter DW=32,SwAccess=0,Mubi=0 ) 100.00 100.00
prim_subreg_arb ( parameter DW=32,SwAccess=0,Mubi=0 + DW=1,SwAccess=0,Mubi=0 + DW=2,SwAccess=0,Mubi=0 + DW=16,SwAccess=0,Mubi=0 + DW=8,SwAccess=0,Mubi=0 + DW=3,SwAccess=0,Mubi=0 + DW=24,SwAccess=0,Mubi=0 + DW=10,SwAccess=0,Mubi=0 + DW=4,SwAccess=0,Mubi=1 + DW=31,SwAccess=0,Mubi=0 + DW=7,SwAccess=0,Mubi=0 + DW=6,SwAccess=0,Mubi=0 + DW=12,SwAccess=0,Mubi=0 + DW=11,SwAccess=0,Mubi=0 + DW=5,SwAccess=0,Mubi=0 + DW=9,SwAccess=0,Mubi=0 + DW=27,SwAccess=0,Mubi=0 + DW=20,SwAccess=0,Mubi=0 ) 100.00 100.00
prim_subreg_arb ( parameter DW=32,SwAccess=1,Mubi=0 + DW=1,SwAccess=1,Mubi=0 + DW=16,SwAccess=1,Mubi=0 + DW=5,SwAccess=1,Mubi=0 + DW=9,SwAccess=1,Mubi=0 + DW=8,SwAccess=1,Mubi=0 + DW=3,SwAccess=1,Mubi=0 + DW=7,SwAccess=1,Mubi=0 + DW=6,SwAccess=1,Mubi=0 + DW=4,SwAccess=1,Mubi=0 + DW=2,SwAccess=1,Mubi=0 + DW=10,SwAccess=1,Mubi=0 + DW=20,SwAccess=1,Mubi=0 ) 100.00 100.00
prim_subreg_arb ( parameter DW=4,SwAccess=0,Mubi=1 ) 100.00 100.00
prim_subreg_arb ( parameter DW=4,SwAccess=4,Mubi=1 ) 100.00 100.00 100.00
prim_subreg_arb ( parameter DW=6,SwAccess=0,Mubi=0 ) 100.00 100.00
prim_subreg_arb ( parameter DW=7,SwAccess=0,Mubi=0 ) 100.00 100.00
prim_subreg_arb ( parameter DW=8,SwAccess=0,Mubi=0 ) 100.00 100.00
prim_subreg_ext 100.00 100.00
prim_secded_inv_39_32_enc 100.00 100.00
xbar_main 100.00 100.00
tlul_err 100.00 100.00 100.00 100.00 100.00
prim_secded_inv_64_57_enc 100.00 100.00
prim_generic_pad_wrapper 100.00 100.00 100.00 100.00 100.00
prim_generic_pad_wrapper 100.00 100.00
prim_generic_pad_wrapper ( parameter PadType=0,ScanRole=0 ) 100.00 100.00 100.00 100.00
prim_generic_pad_wrapper ( parameter PadType=3,ScanRole=0 ) 100.00 100.00 100.00 100.00
prim_generic_pad_wrapper ( parameter PadType=4,ScanRole=0 ) 100.00 100.00
xbar_peri 100.00 100.00
prim_generic_flop 100.00 100.00 100.00
prim_mubi4_sync 100.00 100.00
prim_generic_clock_buf 100.00 100.00
pinmux_jtag_buf
prim_usb_diff_rx
prim_clock_buf
tlul_data_integ_enc
prim_reg_we_check
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