Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3359	1			T14	1		T16	35		T31	14
all_values[1]	3294	1			T16	24		T31	16		T53	26
all_values[2]	3340	1			T14	2		T16	30		T31	11
all_values[3]	3343	1			T14	1		T16	27		T31	14
all_values[4]	3387	1			T14	1		T16	23		T31	18
all_values[5]	3298	1			T14	1		T16	26		T31	15
all_values[6]	3321	1			T14	1		T16	28		T31	14
all_values[7]	3330	1			T14	3		T16	25		T31	6
all_values[8]	3302	1			T14	5		T16	28		T31	6
all_values[9]	3297	1			T16	36		T31	14		T53	15
all_values[10]	3294	1			T14	1		T16	35		T31	14
all_values[11]	3382	1			T16	25		T31	15		T53	24
all_values[12]	3309	1			T14	1		T16	21		T31	17
all_values[13]	3317	1			T14	1		T16	34		T31	13
all_values[14]	3300	1			T16	33		T31	11		T53	29
all_values[15]	3289	1			T16	23		T31	19		T53	20
all_values[16]	3354	1			T14	3		T16	24		T31	16
all_values[17]	3278	1			T14	3		T16	24		T31	7
all_values[18]	3324	1			T14	4		T16	27		T31	12
all_values[19]	3203	1			T14	2		T16	29		T31	15
all_values[20]	3298	1			T14	2		T16	30		T31	13
all_values[21]	3212	1			T14	2		T16	29		T31	13
all_values[22]	3327	1			T14	2		T16	25		T31	11
all_values[23]	3199	1			T14	1		T16	31		T31	11
all_values[24]	3235	1			T14	4		T16	25		T31	11
all_values[25]	3160	1			T14	4		T16	21		T31	16
all_values[26]	3411	1			T14	1		T16	32		T31	22
all_values[27]	3243	1			T14	2		T16	27		T31	10
all_values[28]	3349	1			T14	3		T16	32		T31	15
all_values[29]	3223	1			T14	5		T16	34		T31	17
all_values[30]	3276	1			T14	3		T16	24		T31	11
all_values[31]	3336	1			T14	1		T16	30		T31	14
all_values[32]	3320	1			T14	3		T16	24		T31	6
all_values[33]	3270	1			T14	4		T16	22		T31	20
all_values[34]	3281	1			T14	4		T16	31		T31	2
all_values[35]	3301	1			T14	4		T16	32		T31	14
all_values[36]	3255	1			T14	1		T16	24		T31	8
all_values[37]	3339	1			T14	3		T16	33		T31	18
all_values[38]	3237	1			T14	2		T16	30		T31	13
all_values[39]	3244	1			T14	4		T16	21		T31	10
all_values[40]	3298	1			T14	4		T16	28		T31	6
all_values[41]	3313	1			T14	2		T16	34		T31	13
all_values[42]	3333	1			T14	4		T16	27		T31	13
all_values[43]	3244	1			T14	3		T16	29		T31	17
all_values[44]	3287	1			T16	21		T31	14		T53	18
all_values[45]	3331	1			T14	3		T16	26		T31	13
all_values[46]	3239	1			T14	2		T16	35		T31	9
all_values[47]	3358	1			T14	1		T16	33		T31	15
all_values[48]	3311	1			T14	3		T16	22		T31	14
all_values[49]	3333	1			T14	1		T16	17		T31	18
all_values[50]	3356	1			T14	3		T16	21		T31	18
all_values[51]	3349	1			T14	7		T16	31		T31	14
all_values[52]	3306	1			T14	3		T16	23		T31	19
all_values[53]	3341	1			T14	6		T16	17		T31	18
all_values[54]	3269	1			T14	5		T16	30		T31	11
all_values[55]	3361	1			T14	2		T16	13		T31	10
all_values[56]	3298	1			T14	4		T16	22		T31	18
all_values[57]	3304	1			T14	3		T16	26		T31	14
all_values[58]	3292	1			T14	4		T16	26		T31	13
all_values[59]	3319	1			T14	2		T16	30		T31	10
all_values[60]	3359	1			T14	4		T16	25		T31	18
all_values[61]	3285	1			T14	2		T16	33		T31	14
all_values[62]	3245	1			T14	4		T16	27		T31	9
all_values[63]	3327	1			T14	3		T16	37		T31	11