Go
back
LINE 18838
EXPRESSION (mio_pad_attr_46_we & mio_pad_attr_regwen_46_qs)
---------1-------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T67,T174,T125 |
LINE 19455
EXPRESSION (dio_pad_attr_0_we & dio_pad_attr_regwen_0_qs)
--------1-------- ------------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T66,T128,T185 |
LINE 19608
EXPRESSION (dio_pad_attr_1_we & dio_pad_attr_regwen_1_qs)
--------1-------- ------------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T14,T66,T186 |
LINE 19761
EXPRESSION (dio_pad_attr_2_we & dio_pad_attr_regwen_2_qs)
--------1-------- ------------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T113,T130,T155 |
LINE 19914
EXPRESSION (dio_pad_attr_3_we & dio_pad_attr_regwen_3_qs)
--------1-------- ------------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T165,T187,T188 |
LINE 20067
EXPRESSION (dio_pad_attr_4_we & dio_pad_attr_regwen_4_qs)
--------1-------- ------------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T60,T109,T189 |
LINE 20220
EXPRESSION (dio_pad_attr_5_we & dio_pad_attr_regwen_5_qs)
--------1-------- ------------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T190,T122,T191 |
LINE 20373
EXPRESSION (dio_pad_attr_6_we & dio_pad_attr_regwen_6_qs)
--------1-------- ------------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T64,T178,T192 |
LINE 20526
EXPRESSION (dio_pad_attr_7_we & dio_pad_attr_regwen_7_qs)
--------1-------- ------------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T64,T133,T193 |
LINE 20679
EXPRESSION (dio_pad_attr_8_we & dio_pad_attr_regwen_8_qs)
--------1-------- ------------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T107,T66,T181 |
LINE 20832
EXPRESSION (dio_pad_attr_9_we & dio_pad_attr_regwen_9_qs)
--------1-------- ------------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T194,T195,T157 |
LINE 20985
EXPRESSION (dio_pad_attr_10_we & dio_pad_attr_regwen_10_qs)
---------1-------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T85,T192,T196 |
LINE 21138
EXPRESSION (dio_pad_attr_11_we & dio_pad_attr_regwen_11_qs)
---------1-------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T163,T197,T198 |
LINE 21291
EXPRESSION (dio_pad_attr_12_we & dio_pad_attr_regwen_12_qs)
---------1-------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T67,T109,T96 |
LINE 21444
EXPRESSION (dio_pad_attr_13_we & dio_pad_attr_regwen_13_qs)
---------1-------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T60,T199,T153 |
LINE 21597
EXPRESSION (dio_pad_attr_14_we & dio_pad_attr_regwen_14_qs)
---------1-------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T65,T139,T134 |
LINE 21750
EXPRESSION (dio_pad_attr_15_we & dio_pad_attr_regwen_15_qs)
---------1-------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T117,T200,T149 |
LINE 24538
EXPRESSION (mio_pad_sleep_en_0_we & mio_pad_sleep_regwen_0_qs)
----------1---------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T19,T21,T33 |
1 | 1 | Covered | T12,T17,T18 |
LINE 24570
EXPRESSION (mio_pad_sleep_en_1_we & mio_pad_sleep_regwen_1_qs)
----------1---------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T17,T18,T39 |
1 | 1 | Covered | T16,T12,T65 |
LINE 24602
EXPRESSION (mio_pad_sleep_en_2_we & mio_pad_sleep_regwen_2_qs)
----------1---------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T12,T17,T21 |
1 | 1 | Covered | T15,T16,T12 |
LINE 24634
EXPRESSION (mio_pad_sleep_en_3_we & mio_pad_sleep_regwen_3_qs)
----------1---------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T12,T17,T39 |
1 | 1 | Covered | T12,T19,T108 |
LINE 24666
EXPRESSION (mio_pad_sleep_en_4_we & mio_pad_sleep_regwen_4_qs)
----------1---------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T12,T21,T56 |
1 | 1 | Covered | T19,T60,T17 |
LINE 24698
EXPRESSION (mio_pad_sleep_en_5_we & mio_pad_sleep_regwen_5_qs)
----------1---------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T17,T30,T47 |
1 | 1 | Covered | T12,T19,T67 |
LINE 24730
EXPRESSION (mio_pad_sleep_en_6_we & mio_pad_sleep_regwen_6_qs)
----------1---------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T21,T33,T39 |
1 | 1 | Covered | T16,T12,T19 |
LINE 24762
EXPRESSION (mio_pad_sleep_en_7_we & mio_pad_sleep_regwen_7_qs)
----------1---------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T33,T39,T56 |
1 | 1 | Covered | T12,T19,T60 |
LINE 24794
EXPRESSION (mio_pad_sleep_en_8_we & mio_pad_sleep_regwen_8_qs)
----------1---------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T33,T39,T30 |
1 | 1 | Covered | T12,T19,T17 |
LINE 24826
EXPRESSION (mio_pad_sleep_en_9_we & mio_pad_sleep_regwen_9_qs)
----------1---------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T12,T19,T33 |
1 | 1 | Covered | T12,T85,T17 |
LINE 24858
EXPRESSION (mio_pad_sleep_en_10_we & mio_pad_sleep_regwen_10_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T19,T17,T39 |
1 | 1 | Covered | T12,T67,T61 |
LINE 24890
EXPRESSION (mio_pad_sleep_en_11_we & mio_pad_sleep_regwen_11_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T19,T21,T28 |
1 | 1 | Covered | T14,T71,T12 |
LINE 24922
EXPRESSION (mio_pad_sleep_en_12_we & mio_pad_sleep_regwen_12_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T19,T21,T39 |
1 | 1 | Covered | T12,T60,T100 |
LINE 24954
EXPRESSION (mio_pad_sleep_en_13_we & mio_pad_sleep_regwen_13_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T12,T19,T17 |
1 | 1 | Covered | T201,T85,T67 |
LINE 24986
EXPRESSION (mio_pad_sleep_en_14_we & mio_pad_sleep_regwen_14_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T12,T39,T30 |
1 | 1 | Covered | T19,T83,T64 |
LINE 25018
EXPRESSION (mio_pad_sleep_en_15_we & mio_pad_sleep_regwen_15_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T12,T19,T18 |
1 | 1 | Covered | T71,T168,T17 |
LINE 25050
EXPRESSION (mio_pad_sleep_en_16_we & mio_pad_sleep_regwen_16_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T17,T18,T39 |
1 | 1 | Covered | T12,T65,T19 |
LINE 25082
EXPRESSION (mio_pad_sleep_en_17_we & mio_pad_sleep_regwen_17_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T12,T33,T39 |
1 | 1 | Covered | T12,T19,T60 |
LINE 25114
EXPRESSION (mio_pad_sleep_en_18_we & mio_pad_sleep_regwen_18_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T12,T33,T39 |
1 | 1 | Covered | T12,T19,T66 |
LINE 25146
EXPRESSION (mio_pad_sleep_en_19_we & mio_pad_sleep_regwen_19_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T12,T39,T30 |
1 | 1 | Covered | T19,T60,T17 |
LINE 25178
EXPRESSION (mio_pad_sleep_en_20_we & mio_pad_sleep_regwen_20_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T33,T28,T30 |
1 | 1 | Covered | T12,T19,T60 |
LINE 25210
EXPRESSION (mio_pad_sleep_en_21_we & mio_pad_sleep_regwen_21_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T17,T21,T33 |
1 | 1 | Covered | T12,T57,T19 |
LINE 25242
EXPRESSION (mio_pad_sleep_en_22_we & mio_pad_sleep_regwen_22_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T12,T17,T18 |
1 | 1 | Covered | T16,T19,T60 |
LINE 25274
EXPRESSION (mio_pad_sleep_en_23_we & mio_pad_sleep_regwen_23_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T19,T21,T30 |
1 | 1 | Covered | T12,T60,T85 |
LINE 25306
EXPRESSION (mio_pad_sleep_en_24_we & mio_pad_sleep_regwen_24_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T12,T19,T17 |
1 | 1 | Covered | T16,T12,T57 |
LINE 25338
EXPRESSION (mio_pad_sleep_en_25_we & mio_pad_sleep_regwen_25_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T12,T33,T56 |
1 | 1 | Covered | T19,T100,T17 |
LINE 25370
EXPRESSION (mio_pad_sleep_en_26_we & mio_pad_sleep_regwen_26_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T30,T45,T34 |
1 | 1 | Covered | T12,T19,T60 |
LINE 25402
EXPRESSION (mio_pad_sleep_en_27_we & mio_pad_sleep_regwen_27_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T18,T30,T47 |
1 | 1 | Covered | T12,T19,T163 |
LINE 25434
EXPRESSION (mio_pad_sleep_en_28_we & mio_pad_sleep_regwen_28_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T19,T17,T18 |
1 | 1 | Covered | T12,T60,T67 |
LINE 25466
EXPRESSION (mio_pad_sleep_en_29_we & mio_pad_sleep_regwen_29_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T12,T19,T39 |
1 | 1 | Covered | T57,T17,T18 |
LINE 25498
EXPRESSION (mio_pad_sleep_en_30_we & mio_pad_sleep_regwen_30_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T12,T33,T30 |
1 | 1 | Covered | T16,T12,T69 |
LINE 25530
EXPRESSION (mio_pad_sleep_en_31_we & mio_pad_sleep_regwen_31_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T17,T18,T21 |
1 | 1 | Covered | T12,T19,T116 |
LINE 25562
EXPRESSION (mio_pad_sleep_en_32_we & mio_pad_sleep_regwen_32_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T12,T17,T56 |
1 | 1 | Covered | T12,T19,T66 |
LINE 25594
EXPRESSION (mio_pad_sleep_en_33_we & mio_pad_sleep_regwen_33_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T12,T17,T33 |
1 | 1 | Covered | T19,T64,T128 |
LINE 25626
EXPRESSION (mio_pad_sleep_en_34_we & mio_pad_sleep_regwen_34_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T39,T56,T47 |
1 | 1 | Covered | T12,T202,T19 |
LINE 25658
EXPRESSION (mio_pad_sleep_en_35_we & mio_pad_sleep_regwen_35_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T12,T21,T39 |
1 | 1 | Covered | T12,T19,T108 |
LINE 25690
EXPRESSION (mio_pad_sleep_en_36_we & mio_pad_sleep_regwen_36_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T12,T18,T33 |
1 | 1 | Covered | T19,T67,T17 |
LINE 25722
EXPRESSION (mio_pad_sleep_en_37_we & mio_pad_sleep_regwen_37_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T19,T18,T21 |
1 | 1 | Covered | T16,T71,T12 |
LINE 25754
EXPRESSION (mio_pad_sleep_en_38_we & mio_pad_sleep_regwen_38_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T12,T33,T39 |
1 | 1 | Covered | T19,T17,T203 |
LINE 25786
EXPRESSION (mio_pad_sleep_en_39_we & mio_pad_sleep_regwen_39_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T12,T19,T17 |
1 | 1 | Covered | T82,T98,T204 |
LINE 25818
EXPRESSION (mio_pad_sleep_en_40_we & mio_pad_sleep_regwen_40_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T12,T18,T33 |
1 | 1 | Covered | T71,T12,T19 |
LINE 25850
EXPRESSION (mio_pad_sleep_en_41_we & mio_pad_sleep_regwen_41_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T12,T19,T17 |
1 | 1 | Covered | T128,T98,T21 |
LINE 25882
EXPRESSION (mio_pad_sleep_en_42_we & mio_pad_sleep_regwen_42_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T12,T17,T18 |
1 | 1 | Covered | T19,T205,T96 |
LINE 25914
EXPRESSION (mio_pad_sleep_en_43_we & mio_pad_sleep_regwen_43_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T33,T39,T47 |
1 | 1 | Covered | T12,T19,T17 |
LINE 25946
EXPRESSION (mio_pad_sleep_en_44_we & mio_pad_sleep_regwen_44_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T19,T17,T56 |
1 | 1 | Covered | T12,T57,T138 |
LINE 25978
EXPRESSION (mio_pad_sleep_en_45_we & mio_pad_sleep_regwen_45_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T17,T18,T21 |
1 | 1 | Covered | T71,T12,T65 |
LINE 26010
EXPRESSION (mio_pad_sleep_en_46_we & mio_pad_sleep_regwen_46_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T12,T33,T39 |
1 | 1 | Covered | T71,T12,T19 |
LINE 26042
EXPRESSION (mio_pad_sleep_mode_0_we & mio_pad_sleep_regwen_0_qs)
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T33,T30,T47 |
1 | 1 | Covered | T54,T12,T69 |
LINE 26074
EXPRESSION (mio_pad_sleep_mode_1_we & mio_pad_sleep_regwen_1_qs)
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T12,T18,T39 |
1 | 1 | Covered | T12,T63,T19 |
LINE 26106
EXPRESSION (mio_pad_sleep_mode_2_we & mio_pad_sleep_regwen_2_qs)
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T12,T17,T18 |
1 | 1 | Covered | T12,T19,T85 |
LINE 26138
EXPRESSION (mio_pad_sleep_mode_3_we & mio_pad_sleep_regwen_3_qs)
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T12,T39,T30 |
1 | 1 | Covered | T12,T65,T19 |
LINE 26170
EXPRESSION (mio_pad_sleep_mode_4_we & mio_pad_sleep_regwen_4_qs)
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T12,T21,T56 |
1 | 1 | Covered | T19,T100,T108 |
LINE 26202
EXPRESSION (mio_pad_sleep_mode_5_we & mio_pad_sleep_regwen_5_qs)
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T33,T30,T47 |
1 | 1 | Covered | T12,T19,T60 |
LINE 26234
EXPRESSION (mio_pad_sleep_mode_6_we & mio_pad_sleep_regwen_6_qs)
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T33,T39,T30 |
1 | 1 | Covered | T12,T19,T60 |
LINE 26266
EXPRESSION (mio_pad_sleep_mode_7_we & mio_pad_sleep_regwen_7_qs)
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T39,T45,T56 |
1 | 1 | Covered | T12,T19,T67 |
LINE 26298
EXPRESSION (mio_pad_sleep_mode_8_we & mio_pad_sleep_regwen_8_qs)
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T12,T39,T30 |
1 | 1 | Covered | T31,T12,T19 |
LINE 26330
EXPRESSION (mio_pad_sleep_mode_9_we & mio_pad_sleep_regwen_9_qs)
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T12,T19,T33 |
1 | 1 | Covered | T12,T60,T103 |
LINE 26362
EXPRESSION (mio_pad_sleep_mode_10_we & mio_pad_sleep_regwen_10_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T19,T17,T39 |
1 | 1 | Covered | T12,T62,T64 |
LINE 26394
EXPRESSION (mio_pad_sleep_mode_11_we & mio_pad_sleep_regwen_11_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T19,T21,T33 |
1 | 1 | Covered | T12,T206,T69 |
LINE 26426
EXPRESSION (mio_pad_sleep_mode_12_we & mio_pad_sleep_regwen_12_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T17,T18,T33 |
1 | 1 | Covered | T12,T19,T85 |
LINE 26458
EXPRESSION (mio_pad_sleep_mode_13_we & mio_pad_sleep_regwen_13_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T12,T19,T33 |
1 | 1 | Covered | T12,T64,T61 |
LINE 26490
EXPRESSION (mio_pad_sleep_mode_14_we & mio_pad_sleep_regwen_14_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T12,T17,T18 |
1 | 1 | Covered | T69,T19,T108 |
LINE 26522
EXPRESSION (mio_pad_sleep_mode_15_we & mio_pad_sleep_regwen_15_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T12,T19,T18 |
1 | 1 | Covered | T12,T62,T64 |
LINE 26554
EXPRESSION (mio_pad_sleep_mode_16_we & mio_pad_sleep_regwen_16_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T18,T33,T39 |
1 | 1 | Covered | T12,T19,T108 |
LINE 26586
EXPRESSION (mio_pad_sleep_mode_17_we & mio_pad_sleep_regwen_17_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T12,T39,T56 |
1 | 1 | Covered | T71,T12,T57 |
LINE 26618
EXPRESSION (mio_pad_sleep_mode_18_we & mio_pad_sleep_regwen_18_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T12,T33,T39 |
1 | 1 | Covered | T12,T19,T85 |
LINE 26650
EXPRESSION (mio_pad_sleep_mode_19_we & mio_pad_sleep_regwen_19_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T12,T18,T39 |
1 | 1 | Covered | T71,T19,T67 |
LINE 26682
EXPRESSION (mio_pad_sleep_mode_20_we & mio_pad_sleep_regwen_20_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T18,T33,T28 |
1 | 1 | Covered | T52,T12,T113 |
LINE 26714
EXPRESSION (mio_pad_sleep_mode_21_we & mio_pad_sleep_regwen_21_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T21,T33,T39 |
1 | 1 | Covered | T71,T12,T19 |
LINE 26746
EXPRESSION (mio_pad_sleep_mode_22_we & mio_pad_sleep_regwen_22_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T12,T17,T33 |
1 | 1 | Covered | T12,T57,T19 |
LINE 26778
EXPRESSION (mio_pad_sleep_mode_23_we & mio_pad_sleep_regwen_23_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T19,T18,T21 |
1 | 1 | Covered | T31,T12,T65 |
LINE 26810
EXPRESSION (mio_pad_sleep_mode_24_we & mio_pad_sleep_regwen_24_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T12,T18,T39 |
1 | 1 | Covered | T31,T12,T19 |
LINE 26842
EXPRESSION (mio_pad_sleep_mode_25_we & mio_pad_sleep_regwen_25_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T12,T18,T33 |
1 | 1 | Covered | T80,T19,T17 |
LINE 26874
EXPRESSION (mio_pad_sleep_mode_26_we & mio_pad_sleep_regwen_26_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T39,T30,T45 |
1 | 1 | Covered | T12,T65,T19 |
LINE 26906
EXPRESSION (mio_pad_sleep_mode_27_we & mio_pad_sleep_regwen_27_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T12,T18,T33 |
1 | 1 | Covered | T12,T19,T60 |
LINE 26938
EXPRESSION (mio_pad_sleep_mode_28_we & mio_pad_sleep_regwen_28_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T19,T17,T18 |
1 | 1 | Covered | T12,T64,T128 |
LINE 26970
EXPRESSION (mio_pad_sleep_mode_29_we & mio_pad_sleep_regwen_29_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T12,T19,T17 |
1 | 1 | Covered | T12,T67,T112 |
LINE 27002
EXPRESSION (mio_pad_sleep_mode_30_we & mio_pad_sleep_regwen_30_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T12,T47,T58 |
1 | 1 | Covered | T12,T65,T19 |
LINE 27034
EXPRESSION (mio_pad_sleep_mode_31_we & mio_pad_sleep_regwen_31_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T18,T39,T28 |
1 | 1 | Covered | T12,T19,T60 |
LINE 27066
EXPRESSION (mio_pad_sleep_mode_32_we & mio_pad_sleep_regwen_32_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T12,T17,T33 |
1 | 1 | Covered | T19,T60,T116 |
LINE 27098
EXPRESSION (mio_pad_sleep_mode_33_we & mio_pad_sleep_regwen_33_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T12,T19,T33 |
1 | 1 | Covered | T103,T67,T66 |
LINE 27130
EXPRESSION (mio_pad_sleep_mode_34_we & mio_pad_sleep_regwen_34_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T19,T39,T56 |
1 | 1 | Covered | T12,T64,T61 |
LINE 27162
EXPRESSION (mio_pad_sleep_mode_35_we & mio_pad_sleep_regwen_35_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T12,T21,T39 |
1 | 1 | Covered | T71,T12,T19 |
LINE 27194
EXPRESSION (mio_pad_sleep_mode_36_we & mio_pad_sleep_regwen_36_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T12,T18,T33 |
1 | 1 | Covered | T29,T19,T62 |
LINE 27226
EXPRESSION (mio_pad_sleep_mode_37_we & mio_pad_sleep_regwen_37_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T19,T18,T21 |
1 | 1 | Covered | T12,T70,T69 |
LINE 27258
EXPRESSION (mio_pad_sleep_mode_38_we & mio_pad_sleep_regwen_38_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T12,T33,T39 |
1 | 1 | Covered | T68,T19,T60 |
LINE 27290
EXPRESSION (mio_pad_sleep_mode_39_we & mio_pad_sleep_regwen_39_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T12,T19,T17 |
1 | 1 | Covered | T69,T62,T141 |
LINE 27322
EXPRESSION (mio_pad_sleep_mode_40_we & mio_pad_sleep_regwen_40_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T19,T17,T18 |
1 | 1 | Covered | T12,T64,T98 |
LINE 27354
EXPRESSION (mio_pad_sleep_mode_41_we & mio_pad_sleep_regwen_41_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T12,T17,T18 |
1 | 1 | Covered | T19,T60,T128 |
LINE 27386
EXPRESSION (mio_pad_sleep_mode_42_we & mio_pad_sleep_regwen_42_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T12,T18,T21 |
1 | 1 | Covered | T19,T109,T115 |
LINE 27418
EXPRESSION (mio_pad_sleep_mode_43_we & mio_pad_sleep_regwen_43_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T18,T39,T47 |
1 | 1 | Covered | T16,T29,T12 |
LINE 27450
EXPRESSION (mio_pad_sleep_mode_44_we & mio_pad_sleep_regwen_44_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T19,T56,T58 |
1 | 1 | Covered | T12,T65,T67 |
LINE 27482
EXPRESSION (mio_pad_sleep_mode_45_we & mio_pad_sleep_regwen_45_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T12,T17,T18 |
1 | 1 | Covered | T12,T57,T19 |
LINE 27514
EXPRESSION (mio_pad_sleep_mode_46_we & mio_pad_sleep_regwen_46_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T12,T18,T39 |
1 | 1 | Covered | T19,T66,T17 |
LINE 28445
EXPRESSION (dio_pad_sleep_en_0_we & dio_pad_sleep_regwen_0_qs)
----------1---------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T12,T18,T33 |
1 | 1 | Covered | T19,T64,T17 |
LINE 28477
EXPRESSION (dio_pad_sleep_en_1_we & dio_pad_sleep_regwen_1_qs)
----------1---------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T12,T17,T21 |
1 | 1 | Covered | T19,T18,T33 |
LINE 28509
EXPRESSION (dio_pad_sleep_en_2_we & dio_pad_sleep_regwen_2_qs)
----------1---------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T12,T21,T39 |
1 | 1 | Covered | T12,T19,T60 |
LINE 28541
EXPRESSION (dio_pad_sleep_en_3_we & dio_pad_sleep_regwen_3_qs)
----------1---------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T17,T33,T39 |
1 | 1 | Covered | T12,T65,T19 |
LINE 28573
EXPRESSION (dio_pad_sleep_en_4_we & dio_pad_sleep_regwen_4_qs)
----------1---------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T19,T18,T39 |
1 | 1 | Covered | T12,T79,T60 |
LINE 28605
EXPRESSION (dio_pad_sleep_en_5_we & dio_pad_sleep_regwen_5_qs)
----------1---------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T19,T18,T33 |
1 | 1 | Covered | T12,T60,T67 |
LINE 28637
EXPRESSION (dio_pad_sleep_en_6_we & dio_pad_sleep_regwen_6_qs)
----------1---------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T12,T17,T33 |
1 | 1 | Covered | T12,T19,T62 |
LINE 28669
EXPRESSION (dio_pad_sleep_en_7_we & dio_pad_sleep_regwen_7_qs)
----------1---------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T18,T33,T58 |
1 | 1 | Covered | T16,T12,T69 |
LINE 28701
EXPRESSION (dio_pad_sleep_en_8_we & dio_pad_sleep_regwen_8_qs)
----------1---------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T18,T21,T39 |
1 | 1 | Covered | T12,T19,T17 |
LINE 28733
EXPRESSION (dio_pad_sleep_en_9_we & dio_pad_sleep_regwen_9_qs)
----------1---------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T12,T18,T21 |
1 | 1 | Covered | T12,T19,T64 |
LINE 28765
EXPRESSION (dio_pad_sleep_en_10_we & dio_pad_sleep_regwen_10_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T12,T17,T39 |
1 | 1 | Covered | T12,T69,T19 |
LINE 28797
EXPRESSION (dio_pad_sleep_en_11_we & dio_pad_sleep_regwen_11_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T18,T33,T30 |
1 | 1 | Covered | T72,T71,T12 |
LINE 28829
EXPRESSION (dio_pad_sleep_en_12_we & dio_pad_sleep_regwen_12_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T12,T17,T21 |
1 | 1 | Covered | T19,T102,T85 |
LINE 28861
EXPRESSION (dio_pad_sleep_en_13_we & dio_pad_sleep_regwen_13_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T19,T33,T30 |
1 | 1 | Covered | T12,T83,T67 |
LINE 28893
EXPRESSION (dio_pad_sleep_en_14_we & dio_pad_sleep_regwen_14_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T12,T18,T47 |
1 | 1 | Covered | T12,T19,T102 |
LINE 28925
EXPRESSION (dio_pad_sleep_en_15_we & dio_pad_sleep_regwen_15_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T12,T17,T18 |
1 | 1 | Covered | T19,T115,T21 |
LINE 28957
EXPRESSION (dio_pad_sleep_mode_0_we & dio_pad_sleep_regwen_0_qs)
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T12,T18,T33 |
1 | 1 | Covered | T12,T57,T19 |
LINE 28989
EXPRESSION (dio_pad_sleep_mode_1_we & dio_pad_sleep_regwen_1_qs)
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T12,T17,T21 |
1 | 1 | Covered | T19,T60,T67 |
LINE 29021
EXPRESSION (dio_pad_sleep_mode_2_we & dio_pad_sleep_regwen_2_qs)
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T12,T21,T39 |
1 | 1 | Covered | T12,T69,T19 |
LINE 29053
EXPRESSION (dio_pad_sleep_mode_3_we & dio_pad_sleep_regwen_3_qs)
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T17,T33,T39 |
1 | 1 | Covered | T12,T19,T141 |
LINE 29085
EXPRESSION (dio_pad_sleep_mode_4_we & dio_pad_sleep_regwen_4_qs)
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T19,T17,T18 |
1 | 1 | Covered | T54,T12,T128 |
LINE 29117
EXPRESSION (dio_pad_sleep_mode_5_we & dio_pad_sleep_regwen_5_qs)
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T19,T18,T33 |
1 | 1 | Covered | T12,T69,T85 |
LINE 29149
EXPRESSION (dio_pad_sleep_mode_6_we & dio_pad_sleep_regwen_6_qs)
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T12,T17,T39 |
1 | 1 | Covered | T12,T19,T203 |
LINE 29181
EXPRESSION (dio_pad_sleep_mode_7_we & dio_pad_sleep_regwen_7_qs)
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T12,T33,T58 |
1 | 1 | Covered | T12,T19,T108 |
LINE 29213
EXPRESSION (dio_pad_sleep_mode_8_we & dio_pad_sleep_regwen_8_qs)
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T18,T39,T30 |
1 | 1 | Covered | T12,T19,T17 |
LINE 29245
EXPRESSION (dio_pad_sleep_mode_9_we & dio_pad_sleep_regwen_9_qs)
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T12,T17,T21 |
1 | 1 | Covered | T12,T69,T19 |
LINE 29277
EXPRESSION (dio_pad_sleep_mode_10_we & dio_pad_sleep_regwen_10_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T12,T17,T33 |
1 | 1 | Covered | T71,T12,T69 |
LINE 29309
EXPRESSION (dio_pad_sleep_mode_11_we & dio_pad_sleep_regwen_11_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T17,T30,T56 |
1 | 1 | Covered | T72,T12,T19 |