Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo	40.00	0.00					80.00
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo	52.50	25.00					80.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo	75.00	50.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	547324184	241965	0	0
DepthKnown_A	547324184	547207846	0	0
RvalidKnown_A	547324184	547207846	0	0
WreadyKnown_A	547324184	547207846	0	0
gen_passthru_fifo.paramCheckPass	11576	11576	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	547324184	241965	0	0
T1	236340	532	0	0
T2	377014	172	0	0
T3	213930	98	0	0
T8	340664	125	0	0
T9	277032	1380	0	0
T10	150742	50	0	0
T14	336402	16089	0	0
T15	249486	6563	0	0
T16	340134	16935	0	0
T17	218936	181	0	0
T18	221204	78	0	0
T19	203356	218	0	0
T20	696904	208	0	0
T24	409306	21544	0	0
T25	305246	8715	0	0
T26	352638	17282	0	0
T27	285676	6896	0	0
T39	380264	150	0	0
T40	1407996	0	0	0
T41	337700	174	0	0
T50	0	100	0	0
T53	108536	14	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	547324184	547207846	0	0
T1	709020	708954	0	0
T2	1131042	1130388	0	0
T3	641790	641112	0	0
T8	1021992	1021290	0	0
T9	831096	831036	0	0
T10	452226	451566	0	0
T14	672804	672116	0	0
T15	498972	498332	0	0
T16	680268	679640	0	0
T17	437872	437828	0	0
T18	442408	442356	0	0
T19	406712	406668	0	0
T20	2090712	2090010	0	0
T24	818612	817900	0	0
T25	610492	609832	0	0
T26	705276	704548	0	0
T27	571352	570640	0	0
T39	1140792	1140048	0	0
T40	4223988	4223268	0	0
T41	1013100	1012398	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	547324184	547207846	0	0
T1	709020	708954	0	0
T2	1131042	1130388	0	0
T3	641790	641112	0	0
T8	1021992	1021290	0	0
T9	831096	831036	0	0
T10	452226	451566	0	0
T14	672804	672116	0	0
T15	498972	498332	0	0
T16	680268	679640	0	0
T17	437872	437828	0	0
T18	442408	442356	0	0
T19	406712	406668	0	0
T20	2090712	2090010	0	0
T24	818612	817900	0	0
T25	610492	609832	0	0
T26	705276	704548	0	0
T27	571352	570640	0	0
T39	1140792	1140048	0	0
T40	4223988	4223268	0	0
T41	1013100	1012398	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	547324184	547207846	0	0
T1	709020	708954	0	0
T2	1131042	1130388	0	0
T3	641790	641112	0	0
T8	1021992	1021290	0	0
T9	831096	831036	0	0
T10	452226	451566	0	0
T14	672804	672116	0	0
T15	498972	498332	0	0
T16	680268	679640	0	0
T17	437872	437828	0	0
T18	442408	442356	0	0
T19	406712	406668	0	0
T20	2090712	2090010	0	0
T24	818612	817900	0	0
T25	610492	609832	0	0
T26	705276	704548	0	0
T27	571352	570640	0	0
T39	1140792	1140048	0	0
T40	4223988	4223268	0	0
T41	1013100	1012398	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	11576	11576	0	0
T4	6	6	0	0
T5	6	6	0	0
T6	6	6	0	0
T7	6	6	0	0
T14	4	4	0	0
T15	4	4	0	0
T16	4	4	0	0
T17	4	4	0	0
T18	4	4	0	0
T19	4	4	0	0
T24	4	4	0	0
T25	4	4	0	0
T26	4	4	0	0
T27	4	4	0	0
T42	6	6	0	0
T46	6	6	0	0
T58	6	6	0	0
T59	6	6	0	0
T60	6	6	0	0
T61	6	6	0	0