Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	0.00					80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	0.00					80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
52.50	25.00					80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
52.50	25.00					80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	0	0.00
CONT_ASSIGN	44	1	0	0.00
CONT_ASSIGN	45	1	0	0.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	0	1
45	0	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	4	80.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	4	80.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	5117576	0	0	0
DepthKnown_A	5117576	5115928	0	0
RvalidKnown_A	5117576	5115928	0	0
WreadyKnown_A	5117576	5115928	0	0
gen_passthru_fifo.paramCheckPass	11	11	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5117576	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5117576	5115928	0	0
T14	168201	168029	0	0
T15	124743	124583	0	0
T16	170067	169910	0	0
T17	109468	109457	0	0
T18	110602	110589	0	0
T19	101678	101667	0	0
T24	204653	204475	0	0
T25	152623	152458	0	0
T26	176319	176137	0	0
T27	142838	142660	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5117576	5115928	0	0
T14	168201	168029	0	0
T15	124743	124583	0	0
T16	170067	169910	0	0
T17	109468	109457	0	0
T18	110602	110589	0	0
T19	101678	101667	0	0
T24	204653	204475	0	0
T25	152623	152458	0	0
T26	176319	176137	0	0
T27	142838	142660	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5117576	5115928	0	0
T14	168201	168029	0	0
T15	124743	124583	0	0
T16	170067	169910	0	0
T17	109468	109457	0	0
T18	110602	110589	0	0
T19	101678	101667	0	0
T24	204653	204475	0	0
T25	152623	152458	0	0
T26	176319	176137	0	0
T27	142838	142660	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	11	11	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0
T26	1	1	0	0
T27	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	1	25.00
CONT_ASSIGN	44	1	0	0.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	0	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	4	80.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	4	80.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	5117576	0	0	0
DepthKnown_A	5117576	5115928	0	0
RvalidKnown_A	5117576	5115928	0	0
WreadyKnown_A	5117576	5115928	0	0
gen_passthru_fifo.paramCheckPass	11	11	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5117576	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5117576	5115928	0	0
T14	168201	168029	0	0
T15	124743	124583	0	0
T16	170067	169910	0	0
T17	109468	109457	0	0
T18	110602	110589	0	0
T19	101678	101667	0	0
T24	204653	204475	0	0
T25	152623	152458	0	0
T26	176319	176137	0	0
T27	142838	142660	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5117576	5115928	0	0
T14	168201	168029	0	0
T15	124743	124583	0	0
T16	170067	169910	0	0
T17	109468	109457	0	0
T18	110602	110589	0	0
T19	101678	101667	0	0
T24	204653	204475	0	0
T25	152623	152458	0	0
T26	176319	176137	0	0
T27	142838	142660	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5117576	5115928	0	0
T14	168201	168029	0	0
T15	124743	124583	0	0
T16	170067	169910	0	0
T17	109468	109457	0	0
T18	110602	110589	0	0
T19	101678	101667	0	0
T24	204653	204475	0	0
T25	152623	152458	0	0
T26	176319	176137	0	0
T27	142838	142660	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	11	11	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0
T26	1	1	0	0
T27	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	5117576	28778	0	0
DepthKnown_A	5117576	5115928	0	0
RvalidKnown_A	5117576	5115928	0	0
WreadyKnown_A	5117576	5115928	0	0
gen_passthru_fifo.paramCheckPass	11	11	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5117576	28778	0	0
T14	168201	3236	0	0
T15	124743	4351	0	0
T16	170067	3577	0	0
T17	109468	39	0	0
T18	110602	39	0	0
T19	101678	39	0	0
T24	204653	4401	0	0
T25	152623	5505	0	0
T26	176319	3466	0	0
T27	142838	4086	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5117576	5115928	0	0
T14	168201	168029	0	0
T15	124743	124583	0	0
T16	170067	169910	0	0
T17	109468	109457	0	0
T18	110602	110589	0	0
T19	101678	101667	0	0
T24	204653	204475	0	0
T25	152623	152458	0	0
T26	176319	176137	0	0
T27	142838	142660	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5117576	5115928	0	0
T14	168201	168029	0	0
T15	124743	124583	0	0
T16	170067	169910	0	0
T17	109468	109457	0	0
T18	110602	110589	0	0
T19	101678	101667	0	0
T24	204653	204475	0	0
T25	152623	152458	0	0
T26	176319	176137	0	0
T27	142838	142660	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5117576	5115928	0	0
T14	168201	168029	0	0
T15	124743	124583	0	0
T16	170067	169910	0	0
T17	109468	109457	0	0
T18	110602	110589	0	0
T19	101678	101667	0	0
T24	204653	204475	0	0
T25	152623	152458	0	0
T26	176319	176137	0	0
T27	142838	142660	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	11	11	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0
T26	1	1	0	0
T27	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	5117576	65959	0	0
DepthKnown_A	5117576	5115928	0	0
RvalidKnown_A	5117576	5115928	0	0
WreadyKnown_A	5117576	5115928	0	0
gen_passthru_fifo.paramCheckPass	11	11	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5117576	65959	0	0
T14	168201	12853	0	0
T15	124743	2212	0	0
T16	170067	13358	0	0
T17	109468	142	0	0
T18	110602	39	0	0
T19	101678	179	0	0
T24	204653	17143	0	0
T25	152623	3210	0	0
T26	176319	13816	0	0
T27	142838	2810	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5117576	5115928	0	0
T14	168201	168029	0	0
T15	124743	124583	0	0
T16	170067	169910	0	0
T17	109468	109457	0	0
T18	110602	110589	0	0
T19	101678	101667	0	0
T24	204653	204475	0	0
T25	152623	152458	0	0
T26	176319	176137	0	0
T27	142838	142660	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5117576	5115928	0	0
T14	168201	168029	0	0
T15	124743	124583	0	0
T16	170067	169910	0	0
T17	109468	109457	0	0
T18	110602	110589	0	0
T19	101678	101667	0	0
T24	204653	204475	0	0
T25	152623	152458	0	0
T26	176319	176137	0	0
T27	142838	142660	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5117576	5115928	0	0
T14	168201	168029	0	0
T15	124743	124583	0	0
T16	170067	169910	0	0
T17	109468	109457	0	0
T18	110602	110589	0	0
T19	101678	101667	0	0
T24	204653	204475	0	0
T25	152623	152458	0	0
T26	176319	176137	0	0
T27	142838	142660	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	11	11	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0
T26	1	1	0	0
T27	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	87808980	34281	0	0
DepthKnown_A	87808980	87790689	0	0
RvalidKnown_A	87808980	87790689	0	0
WreadyKnown_A	87808980	87790689	0	0
gen_passthru_fifo.paramCheckPass	1922	1922	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87808980	34281	0	0
T1	118170	266	0	0
T2	188507	86	0	0
T3	106965	49	0	0
T8	170332	53	0	0
T9	138516	530	0	0
T10	75371	25	0	0
T20	348452	104	0	0
T39	190132	75	0	0
T40	703998	0	0	0
T41	168850	87	0	0
T50	0	50	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87808980	87790689	0	0
T1	118170	118159	0	0
T2	188507	188398	0	0
T3	106965	106852	0	0
T8	170332	170215	0	0
T9	138516	138506	0	0
T10	75371	75261	0	0
T20	348452	348335	0	0
T39	190132	190008	0	0
T40	703998	703878	0	0
T41	168850	168733	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87808980	87790689	0	0
T1	118170	118159	0	0
T2	188507	188398	0	0
T3	106965	106852	0	0
T8	170332	170215	0	0
T9	138516	138506	0	0
T10	75371	75261	0	0
T20	348452	348335	0	0
T39	190132	190008	0	0
T40	703998	703878	0	0
T41	168850	168733	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87808980	87790689	0	0
T1	118170	118159	0	0
T2	188507	188398	0	0
T3	106965	106852	0	0
T8	170332	170215	0	0
T9	138516	138506	0	0
T10	75371	75261	0	0
T20	348452	348335	0	0
T39	190132	190008	0	0
T40	703998	703878	0	0
T41	168850	168733	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1922	1922	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T42	1	1	0	0
T46	1	1	0	0
T58	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	87808980	39333	0	0
DepthKnown_A	87808980	87790689	0	0
RvalidKnown_A	87808980	87790689	0	0
WreadyKnown_A	87808980	87790689	0	0
gen_passthru_fifo.paramCheckPass	1922	1922	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87808980	39333	0	0
T1	118170	266	0	0
T2	188507	86	0	0
T3	106965	49	0	0
T8	170332	72	0	0
T9	138516	850	0	0
T10	75371	25	0	0
T20	348452	104	0	0
T39	190132	75	0	0
T40	703998	0	0	0
T41	168850	87	0	0
T50	0	50	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87808980	87790689	0	0
T1	118170	118159	0	0
T2	188507	188398	0	0
T3	106965	106852	0	0
T8	170332	170215	0	0
T9	138516	138506	0	0
T10	75371	75261	0	0
T20	348452	348335	0	0
T39	190132	190008	0	0
T40	703998	703878	0	0
T41	168850	168733	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87808980	87790689	0	0
T1	118170	118159	0	0
T2	188507	188398	0	0
T3	106965	106852	0	0
T8	170332	170215	0	0
T9	138516	138506	0	0
T10	75371	75261	0	0
T20	348452	348335	0	0
T39	190132	190008	0	0
T40	703998	703878	0	0
T41	168850	168733	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87808980	87790689	0	0
T1	118170	118159	0	0
T2	188507	188398	0	0
T3	106965	106852	0	0
T8	170332	170215	0	0
T9	138516	138506	0	0
T10	75371	75261	0	0
T20	348452	348335	0	0
T39	190132	190008	0	0
T40	703998	703878	0	0
T41	168850	168733	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1922	1922	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T42	1	1	0	0
T46	1	1	0	0
T58	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	87808980	28	0	0
DepthKnown_A	87808980	87790689	0	0
RvalidKnown_A	87808980	87790689	0	0
WreadyKnown_A	87808980	87790689	0	0
gen_passthru_fifo.paramCheckPass	1922	1922	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87808980	28	0	0
T51	115036	0	0	0
T53	108536	14	0	0
T80	176393	2	0	0
T81	168437	2	0	0
T282	169401	10	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87808980	87790689	0	0
T1	118170	118159	0	0
T2	188507	188398	0	0
T3	106965	106852	0	0
T8	170332	170215	0	0
T9	138516	138506	0	0
T10	75371	75261	0	0
T20	348452	348335	0	0
T39	190132	190008	0	0
T40	703998	703878	0	0
T41	168850	168733	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87808980	87790689	0	0
T1	118170	118159	0	0
T2	188507	188398	0	0
T3	106965	106852	0	0
T8	170332	170215	0	0
T9	138516	138506	0	0
T10	75371	75261	0	0
T20	348452	348335	0	0
T39	190132	190008	0	0
T40	703998	703878	0	0
T41	168850	168733	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87808980	87790689	0	0
T1	118170	118159	0	0
T2	188507	188398	0	0
T3	106965	106852	0	0
T8	170332	170215	0	0
T9	138516	138506	0	0
T10	75371	75261	0	0
T20	348452	348335	0	0
T39	190132	190008	0	0
T40	703998	703878	0	0
T41	168850	168733	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1922	1922	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T42	1	1	0	0
T46	1	1	0	0
T58	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	87808980	28	0	0
DepthKnown_A	87808980	87790689	0	0
RvalidKnown_A	87808980	87790689	0	0
WreadyKnown_A	87808980	87790689	0	0
gen_passthru_fifo.paramCheckPass	1922	1922	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87808980	28	0	0
T51	115036	0	0	0
T53	108536	14	0	0
T80	176393	2	0	0
T81	168437	2	0	0
T282	169401	10	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87808980	87790689	0	0
T1	118170	118159	0	0
T2	188507	188398	0	0
T3	106965	106852	0	0
T8	170332	170215	0	0
T9	138516	138506	0	0
T10	75371	75261	0	0
T20	348452	348335	0	0
T39	190132	190008	0	0
T40	703998	703878	0	0
T41	168850	168733	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87808980	87790689	0	0
T1	118170	118159	0	0
T2	188507	188398	0	0
T3	106965	106852	0	0
T8	170332	170215	0	0
T9	138516	138506	0	0
T10	75371	75261	0	0
T20	348452	348335	0	0
T39	190132	190008	0	0
T40	703998	703878	0	0
T41	168850	168733	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87808980	87790689	0	0
T1	118170	118159	0	0
T2	188507	188398	0	0
T3	106965	106852	0	0
T8	170332	170215	0	0
T9	138516	138506	0	0
T10	75371	75261	0	0
T20	348452	348335	0	0
T39	190132	190008	0	0
T40	703998	703878	0	0
T41	168850	168733	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1922	1922	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T42	1	1	0	0
T46	1	1	0	0
T58	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	87808980	34253	0	0
DepthKnown_A	87808980	87790689	0	0
RvalidKnown_A	87808980	87790689	0	0
WreadyKnown_A	87808980	87790689	0	0
gen_passthru_fifo.paramCheckPass	1922	1922	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87808980	34253	0	0
T1	118170	266	0	0
T2	188507	86	0	0
T3	106965	49	0	0
T8	170332	53	0	0
T9	138516	530	0	0
T10	75371	25	0	0
T20	348452	104	0	0
T39	190132	75	0	0
T40	703998	0	0	0
T41	168850	87	0	0
T50	0	50	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87808980	87790689	0	0
T1	118170	118159	0	0
T2	188507	188398	0	0
T3	106965	106852	0	0
T8	170332	170215	0	0
T9	138516	138506	0	0
T10	75371	75261	0	0
T20	348452	348335	0	0
T39	190132	190008	0	0
T40	703998	703878	0	0
T41	168850	168733	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87808980	87790689	0	0
T1	118170	118159	0	0
T2	188507	188398	0	0
T3	106965	106852	0	0
T8	170332	170215	0	0
T9	138516	138506	0	0
T10	75371	75261	0	0
T20	348452	348335	0	0
T39	190132	190008	0	0
T40	703998	703878	0	0
T41	168850	168733	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87808980	87790689	0	0
T1	118170	118159	0	0
T2	188507	188398	0	0
T3	106965	106852	0	0
T8	170332	170215	0	0
T9	138516	138506	0	0
T10	75371	75261	0	0
T20	348452	348335	0	0
T39	190132	190008	0	0
T40	703998	703878	0	0
T41	168850	168733	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1922	1922	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T42	1	1	0	0
T46	1	1	0	0
T58	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	87808980	39305	0	0
DepthKnown_A	87808980	87790689	0	0
RvalidKnown_A	87808980	87790689	0	0
WreadyKnown_A	87808980	87790689	0	0
gen_passthru_fifo.paramCheckPass	1922	1922	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87808980	39305	0	0
T1	118170	266	0	0
T2	188507	86	0	0
T3	106965	49	0	0
T8	170332	72	0	0
T9	138516	850	0	0
T10	75371	25	0	0
T20	348452	104	0	0
T39	190132	75	0	0
T40	703998	0	0	0
T41	168850	87	0	0
T50	0	50	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87808980	87790689	0	0
T1	118170	118159	0	0
T2	188507	188398	0	0
T3	106965	106852	0	0
T8	170332	170215	0	0
T9	138516	138506	0	0
T10	75371	75261	0	0
T20	348452	348335	0	0
T39	190132	190008	0	0
T40	703998	703878	0	0
T41	168850	168733	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87808980	87790689	0	0
T1	118170	118159	0	0
T2	188507	188398	0	0
T3	106965	106852	0	0
T8	170332	170215	0	0
T9	138516	138506	0	0
T10	75371	75261	0	0
T20	348452	348335	0	0
T39	190132	190008	0	0
T40	703998	703878	0	0
T41	168850	168733	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87808980	87790689	0	0
T1	118170	118159	0	0
T2	188507	188398	0	0
T3	106965	106852	0	0
T8	170332	170215	0	0
T9	138516	138506	0	0
T10	75371	75261	0	0
T20	348452	348335	0	0
T39	190132	190008	0	0
T40	703998	703878	0	0
T41	168850	168733	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1922	1922	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T42	1	1	0	0
T46	1	1	0	0
T58	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0