Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo	40.00	0.00					80.00
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo	52.50	25.00					80.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo	75.00	50.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	593916470	287883	0	0
DepthKnown_A	593916470	593796364	0	0
RvalidKnown_A	593916470	593796364	0	0
WreadyKnown_A	593916470	593796364	0	0
gen_passthru_fifo.paramCheckPass	11626	11626	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	593916470	287883	0	0
T1	312118	8865	0	0
T2	308140	13601	0	0
T3	339488	9506	0	0
T4	289276	6913	0	0
T5	318958	14229	0	0
T6	353590	10039	0	0
T7	436976	23854	0	0
T8	246646	7080	0	0
T9	387754	19701	0	0
T10	329754	9031	0	0
T11	407972	108	0	0
T12	345374	100	0	0
T13	408172	100	0	0
T19	237358	574	0	0
T20	246388	105	0	0
T31	247458	1153	0	0
T32	713614	206	0	0
T39	288786	92	0	0
T47	169280	62	0	0
T51	167307	1	0	0
T62	247078	130	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	593916470	593796364	0	0
T1	624236	623608	0	0
T2	616280	615568	0	0
T3	678976	678292	0	0
T4	578552	577896	0	0
T5	637916	637260	0	0
T6	707180	706452	0	0
T7	873952	873312	0	0
T8	493292	492648	0	0
T9	775508	774808	0	0
T10	659508	658880	0	0
T11	1223916	1223196	0	0
T12	1036122	1035420	0	0
T13	1224516	1223814	0	0
T19	712074	712008	0	0
T20	739164	738444	0	0
T31	742374	742308	0	0
T32	2140842	2140164	0	0
T39	866358	865680	0	0
T47	507840	507096	0	0
T62	741234	740532	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	593916470	593796364	0	0
T1	624236	623608	0	0
T2	616280	615568	0	0
T3	678976	678292	0	0
T4	578552	577896	0	0
T5	637916	637260	0	0
T6	707180	706452	0	0
T7	873952	873312	0	0
T8	493292	492648	0	0
T9	775508	774808	0	0
T10	659508	658880	0	0
T11	1223916	1223196	0	0
T12	1036122	1035420	0	0
T13	1224516	1223814	0	0
T19	712074	712008	0	0
T20	739164	738444	0	0
T31	742374	742308	0	0
T32	2140842	2140164	0	0
T39	866358	865680	0	0
T47	507840	507096	0	0
T62	741234	740532	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	593916470	593796364	0	0
T1	624236	623608	0	0
T2	616280	615568	0	0
T3	678976	678292	0	0
T4	578552	577896	0	0
T5	637916	637260	0	0
T6	707180	706452	0	0
T7	873952	873312	0	0
T8	493292	492648	0	0
T9	775508	774808	0	0
T10	659508	658880	0	0
T11	1223916	1223196	0	0
T12	1036122	1035420	0	0
T13	1224516	1223814	0	0
T19	712074	712008	0	0
T20	739164	738444	0	0
T31	742374	742308	0	0
T32	2140842	2140164	0	0
T39	866358	865680	0	0
T47	507840	507096	0	0
T62	741234	740532	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	11626	11626	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T6	4	4	0	0
T7	4	4	0	0
T8	4	4	0	0
T9	4	4	0	0
T10	4	4	0	0
T11	6	6	0	0
T14	6	6	0	0
T15	6	6	0	0
T16	6	6	0	0
T17	6	6	0	0
T18	6	6	0	0
T34	6	6	0	0
T49	6	6	0	0
T55	6	6	0	0
T56	6	6	0	0