Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	0.00					80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	0.00					80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
52.50	25.00					80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
52.50	25.00					80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	0	0.00
CONT_ASSIGN	44	1	0	0.00
CONT_ASSIGN	45	1	0	0.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	0	1
45	0	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	4	80.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	4	80.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	9343157	0	0	0
DepthKnown_A	9343157	9340780	0	0
RvalidKnown_A	9343157	9340780	0	0
WreadyKnown_A	9343157	9340780	0	0
gen_passthru_fifo.paramCheckPass	16	16	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9343157	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9343157	9340780	0	0
T1	156059	155902	0	0
T2	154070	153892	0	0
T3	169744	169573	0	0
T4	144638	144474	0	0
T5	159479	159315	0	0
T6	176795	176613	0	0
T7	218488	218328	0	0
T8	123323	123162	0	0
T9	193877	193702	0	0
T10	164877	164720	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9343157	9340780	0	0
T1	156059	155902	0	0
T2	154070	153892	0	0
T3	169744	169573	0	0
T4	144638	144474	0	0
T5	159479	159315	0	0
T6	176795	176613	0	0
T7	218488	218328	0	0
T8	123323	123162	0	0
T9	193877	193702	0	0
T10	164877	164720	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9343157	9340780	0	0
T1	156059	155902	0	0
T2	154070	153892	0	0
T3	169744	169573	0	0
T4	144638	144474	0	0
T5	159479	159315	0	0
T6	176795	176613	0	0
T7	218488	218328	0	0
T8	123323	123162	0	0
T9	193877	193702	0	0
T10	164877	164720	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	16	16	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	1	25.00
CONT_ASSIGN	44	1	0	0.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	0	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	4	80.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	4	80.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	9343157	0	0	0
DepthKnown_A	9343157	9340780	0	0
RvalidKnown_A	9343157	9340780	0	0
WreadyKnown_A	9343157	9340780	0	0
gen_passthru_fifo.paramCheckPass	16	16	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9343157	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9343157	9340780	0	0
T1	156059	155902	0	0
T2	154070	153892	0	0
T3	169744	169573	0	0
T4	144638	144474	0	0
T5	159479	159315	0	0
T6	176795	176613	0	0
T7	218488	218328	0	0
T8	123323	123162	0	0
T9	193877	193702	0	0
T10	164877	164720	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9343157	9340780	0	0
T1	156059	155902	0	0
T2	154070	153892	0	0
T3	169744	169573	0	0
T4	144638	144474	0	0
T5	159479	159315	0	0
T6	176795	176613	0	0
T7	218488	218328	0	0
T8	123323	123162	0	0
T9	193877	193702	0	0
T10	164877	164720	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9343157	9340780	0	0
T1	156059	155902	0	0
T2	154070	153892	0	0
T3	169744	169573	0	0
T4	144638	144474	0	0
T5	159479	159315	0	0
T6	176795	176613	0	0
T7	218488	218328	0	0
T8	123323	123162	0	0
T9	193877	193702	0	0
T10	164877	164720	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	16	16	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	9343157	46334	0	0
DepthKnown_A	9343157	9340780	0	0
RvalidKnown_A	9343157	9340780	0	0
WreadyKnown_A	9343157	9340780	0	0
gen_passthru_fifo.paramCheckPass	16	16	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9343157	46334	0	0
T1	156059	5495	0	0
T2	154070	2901	0	0
T3	169744	5724	0	0
T4	144638	4015	0	0
T5	159479	2744	0	0
T6	176795	5981	0	0
T7	218488	5063	0	0
T8	123323	4920	0	0
T9	193877	3930	0	0
T10	164877	5327	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9343157	9340780	0	0
T1	156059	155902	0	0
T2	154070	153892	0	0
T3	169744	169573	0	0
T4	144638	144474	0	0
T5	159479	159315	0	0
T6	176795	176613	0	0
T7	218488	218328	0	0
T8	123323	123162	0	0
T9	193877	193702	0	0
T10	164877	164720	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9343157	9340780	0	0
T1	156059	155902	0	0
T2	154070	153892	0	0
T3	169744	169573	0	0
T4	144638	144474	0	0
T5	159479	159315	0	0
T6	176795	176613	0	0
T7	218488	218328	0	0
T8	123323	123162	0	0
T9	193877	193702	0	0
T10	164877	164720	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9343157	9340780	0	0
T1	156059	155902	0	0
T2	154070	153892	0	0
T3	169744	169573	0	0
T4	144638	144474	0	0
T5	159479	159315	0	0
T6	176795	176613	0	0
T7	218488	218328	0	0
T8	123323	123162	0	0
T9	193877	193702	0	0
T10	164877	164720	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	16	16	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	9343157	77697	0	0
DepthKnown_A	9343157	9340780	0	0
RvalidKnown_A	9343157	9340780	0	0
WreadyKnown_A	9343157	9340780	0	0
gen_passthru_fifo.paramCheckPass	16	16	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9343157	77697	0	0
T1	156059	3370	0	0
T2	154070	10700	0	0
T3	169744	3782	0	0
T4	144638	2898	0	0
T5	159479	11485	0	0
T6	176795	4058	0	0
T7	218488	18791	0	0
T8	123323	2160	0	0
T9	193877	15771	0	0
T10	164877	3704	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9343157	9340780	0	0
T1	156059	155902	0	0
T2	154070	153892	0	0
T3	169744	169573	0	0
T4	144638	144474	0	0
T5	159479	159315	0	0
T6	176795	176613	0	0
T7	218488	218328	0	0
T8	123323	123162	0	0
T9	193877	193702	0	0
T10	164877	164720	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9343157	9340780	0	0
T1	156059	155902	0	0
T2	154070	153892	0	0
T3	169744	169573	0	0
T4	144638	144474	0	0
T5	159479	159315	0	0
T6	176795	176613	0	0
T7	218488	218328	0	0
T8	123323	123162	0	0
T9	193877	193702	0	0
T10	164877	164720	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9343157	9340780	0	0
T1	156059	155902	0	0
T2	154070	153892	0	0
T3	169744	169573	0	0
T4	144638	144474	0	0
T5	159479	159315	0	0
T6	176795	176613	0	0
T7	218488	218328	0	0
T8	123323	123162	0	0
T9	193877	193702	0	0
T10	164877	164720	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	16	16	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	92757307	39150	0	0
DepthKnown_A	92757307	92738874	0	0
RvalidKnown_A	92757307	92738874	0	0
WreadyKnown_A	92757307	92738874	0	0
gen_passthru_fifo.paramCheckPass	1927	1927	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92757307	39150	0	0
T11	203986	54	0	0
T12	172687	50	0	0
T13	204086	50	0	0
T19	118679	287	0	0
T20	123194	50	0	0
T31	123729	428	0	0
T32	356807	100	0	0
T39	144393	46	0	0
T47	84640	31	0	0
T62	123539	65	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92757307	92738874	0	0
T11	203986	203866	0	0
T12	172687	172570	0	0
T13	204086	203969	0	0
T19	118679	118668	0	0
T20	123194	123074	0	0
T31	123729	123718	0	0
T32	356807	356694	0	0
T39	144393	144280	0	0
T47	84640	84516	0	0
T62	123539	123422	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92757307	92738874	0	0
T11	203986	203866	0	0
T12	172687	172570	0	0
T13	204086	203969	0	0
T19	118679	118668	0	0
T20	123194	123074	0	0
T31	123729	123718	0	0
T32	356807	356694	0	0
T39	144393	144280	0	0
T47	84640	84516	0	0
T62	123539	123422	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92757307	92738874	0	0
T11	203986	203866	0	0
T12	172687	172570	0	0
T13	204086	203969	0	0
T19	118679	118668	0	0
T20	123194	123074	0	0
T31	123729	123718	0	0
T32	356807	356694	0	0
T39	144393	144280	0	0
T47	84640	84516	0	0
T62	123539	123422	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1927	1927	0	0
T11	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T34	1	1	0	0
T49	1	1	0	0
T55	1	1	0	0
T56	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	92757307	42776	0	0
DepthKnown_A	92757307	92738874	0	0
RvalidKnown_A	92757307	92738874	0	0
WreadyKnown_A	92757307	92738874	0	0
gen_passthru_fifo.paramCheckPass	1927	1927	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92757307	42776	0	0
T11	203986	54	0	0
T12	172687	50	0	0
T13	204086	50	0	0
T19	118679	287	0	0
T20	123194	55	0	0
T31	123729	725	0	0
T32	356807	106	0	0
T39	144393	46	0	0
T47	84640	31	0	0
T62	123539	65	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92757307	92738874	0	0
T11	203986	203866	0	0
T12	172687	172570	0	0
T13	204086	203969	0	0
T19	118679	118668	0	0
T20	123194	123074	0	0
T31	123729	123718	0	0
T32	356807	356694	0	0
T39	144393	144280	0	0
T47	84640	84516	0	0
T62	123539	123422	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92757307	92738874	0	0
T11	203986	203866	0	0
T12	172687	172570	0	0
T13	204086	203969	0	0
T19	118679	118668	0	0
T20	123194	123074	0	0
T31	123729	123718	0	0
T32	356807	356694	0	0
T39	144393	144280	0	0
T47	84640	84516	0	0
T62	123539	123422	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92757307	92738874	0	0
T11	203986	203866	0	0
T12	172687	172570	0	0
T13	204086	203969	0	0
T19	118679	118668	0	0
T20	123194	123074	0	0
T31	123729	123718	0	0
T32	356807	356694	0	0
T39	144393	144280	0	0
T47	84640	84516	0	0
T62	123539	123422	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1927	1927	0	0
T11	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T34	1	1	0	0
T49	1	1	0	0
T55	1	1	0	0
T56	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	92757307	9	0	0
DepthKnown_A	92757307	92738874	0	0
RvalidKnown_A	92757307	92738874	0	0
WreadyKnown_A	92757307	92738874	0	0
gen_passthru_fifo.paramCheckPass	1927	1927	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92757307	9	0	0
T51	167307	1	0	0
T64	102766	2	0	0
T65	170021	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92757307	92738874	0	0
T11	203986	203866	0	0
T12	172687	172570	0	0
T13	204086	203969	0	0
T19	118679	118668	0	0
T20	123194	123074	0	0
T31	123729	123718	0	0
T32	356807	356694	0	0
T39	144393	144280	0	0
T47	84640	84516	0	0
T62	123539	123422	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92757307	92738874	0	0
T11	203986	203866	0	0
T12	172687	172570	0	0
T13	204086	203969	0	0
T19	118679	118668	0	0
T20	123194	123074	0	0
T31	123729	123718	0	0
T32	356807	356694	0	0
T39	144393	144280	0	0
T47	84640	84516	0	0
T62	123539	123422	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92757307	92738874	0	0
T11	203986	203866	0	0
T12	172687	172570	0	0
T13	204086	203969	0	0
T19	118679	118668	0	0
T20	123194	123074	0	0
T31	123729	123718	0	0
T32	356807	356694	0	0
T39	144393	144280	0	0
T47	84640	84516	0	0
T62	123539	123422	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1927	1927	0	0
T11	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T34	1	1	0	0
T49	1	1	0	0
T55	1	1	0	0
T56	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	92757307	9	0	0
DepthKnown_A	92757307	92738874	0	0
RvalidKnown_A	92757307	92738874	0	0
WreadyKnown_A	92757307	92738874	0	0
gen_passthru_fifo.paramCheckPass	1927	1927	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92757307	9	0	0
T51	167307	1	0	0
T64	102766	2	0	0
T65	170021	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92757307	92738874	0	0
T11	203986	203866	0	0
T12	172687	172570	0	0
T13	204086	203969	0	0
T19	118679	118668	0	0
T20	123194	123074	0	0
T31	123729	123718	0	0
T32	356807	356694	0	0
T39	144393	144280	0	0
T47	84640	84516	0	0
T62	123539	123422	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92757307	92738874	0	0
T11	203986	203866	0	0
T12	172687	172570	0	0
T13	204086	203969	0	0
T19	118679	118668	0	0
T20	123194	123074	0	0
T31	123729	123718	0	0
T32	356807	356694	0	0
T39	144393	144280	0	0
T47	84640	84516	0	0
T62	123539	123422	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92757307	92738874	0	0
T11	203986	203866	0	0
T12	172687	172570	0	0
T13	204086	203969	0	0
T19	118679	118668	0	0
T20	123194	123074	0	0
T31	123729	123718	0	0
T32	356807	356694	0	0
T39	144393	144280	0	0
T47	84640	84516	0	0
T62	123539	123422	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1927	1927	0	0
T11	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T34	1	1	0	0
T49	1	1	0	0
T55	1	1	0	0
T56	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	92757307	39141	0	0
DepthKnown_A	92757307	92738874	0	0
RvalidKnown_A	92757307	92738874	0	0
WreadyKnown_A	92757307	92738874	0	0
gen_passthru_fifo.paramCheckPass	1927	1927	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92757307	39141	0	0
T11	203986	54	0	0
T12	172687	50	0	0
T13	204086	50	0	0
T19	118679	287	0	0
T20	123194	50	0	0
T31	123729	428	0	0
T32	356807	100	0	0
T39	144393	46	0	0
T47	84640	31	0	0
T62	123539	65	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92757307	92738874	0	0
T11	203986	203866	0	0
T12	172687	172570	0	0
T13	204086	203969	0	0
T19	118679	118668	0	0
T20	123194	123074	0	0
T31	123729	123718	0	0
T32	356807	356694	0	0
T39	144393	144280	0	0
T47	84640	84516	0	0
T62	123539	123422	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92757307	92738874	0	0
T11	203986	203866	0	0
T12	172687	172570	0	0
T13	204086	203969	0	0
T19	118679	118668	0	0
T20	123194	123074	0	0
T31	123729	123718	0	0
T32	356807	356694	0	0
T39	144393	144280	0	0
T47	84640	84516	0	0
T62	123539	123422	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92757307	92738874	0	0
T11	203986	203866	0	0
T12	172687	172570	0	0
T13	204086	203969	0	0
T19	118679	118668	0	0
T20	123194	123074	0	0
T31	123729	123718	0	0
T32	356807	356694	0	0
T39	144393	144280	0	0
T47	84640	84516	0	0
T62	123539	123422	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1927	1927	0	0
T11	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T34	1	1	0	0
T49	1	1	0	0
T55	1	1	0	0
T56	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	92757307	42767	0	0
DepthKnown_A	92757307	92738874	0	0
RvalidKnown_A	92757307	92738874	0	0
WreadyKnown_A	92757307	92738874	0	0
gen_passthru_fifo.paramCheckPass	1927	1927	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92757307	42767	0	0
T11	203986	54	0	0
T12	172687	50	0	0
T13	204086	50	0	0
T19	118679	287	0	0
T20	123194	55	0	0
T31	123729	725	0	0
T32	356807	106	0	0
T39	144393	46	0	0
T47	84640	31	0	0
T62	123539	65	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92757307	92738874	0	0
T11	203986	203866	0	0
T12	172687	172570	0	0
T13	204086	203969	0	0
T19	118679	118668	0	0
T20	123194	123074	0	0
T31	123729	123718	0	0
T32	356807	356694	0	0
T39	144393	144280	0	0
T47	84640	84516	0	0
T62	123539	123422	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92757307	92738874	0	0
T11	203986	203866	0	0
T12	172687	172570	0	0
T13	204086	203969	0	0
T19	118679	118668	0	0
T20	123194	123074	0	0
T31	123729	123718	0	0
T32	356807	356694	0	0
T39	144393	144280	0	0
T47	84640	84516	0	0
T62	123539	123422	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92757307	92738874	0	0
T11	203986	203866	0	0
T12	172687	172570	0	0
T13	204086	203969	0	0
T19	118679	118668	0	0
T20	123194	123074	0	0
T31	123729	123718	0	0
T32	356807	356694	0	0
T39	144393	144280	0	0
T47	84640	84516	0	0
T62	123539	123422	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1927	1927	0	0
T11	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T34	1	1	0	0
T49	1	1	0	0
T55	1	1	0	0
T56	1	1	0	0