Unified Coverage Report :: Group :: tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	3581827	1			T32	726		T33	13374		T34	84
values[2]	739048	1			T32	55		T33	2874		T34	28
values[3]	112656	1			T32	2		T33	433		T34	4
values[4]	58430	1			T33	216		T100	10		T101	104
values[5]	38003	1			T33	114		T100	10		T101	75
values[6]	28382	1			T33	53		T100	10		T101	45
values[7]	22806	1			T33	50		T100	11		T101	22
values[8]	18751	1			T33	20		T100	10		T101	26
values[9]	16635	1			T33	20		T100	10		T101	20
values[10]	15185	1			T33	15		T100	10		T101	21
values[11]	13835	1			T33	15		T100	11		T101	24
values[12]	12905	1			T33	11		T100	10		T101	29
values[13]	12172	1			T33	10		T100	10		T101	26
values[14]	11469	1			T33	7		T100	10		T101	29
values[15]	11045	1			T33	8		T100	10		T101	57
values[16]	10626	1			T33	17		T100	10		T101	49
values[17]	10390	1			T33	7		T100	10		T101	38
values[18]	10152	1			T33	11		T100	10		T101	25
values[19]	9846	1			T33	5		T100	10		T101	18
values[20]	9404	1			T33	4		T100	10		T101	16
values[21]	9060	1			T33	12		T100	10		T101	19
values[22]	8661	1			T33	7		T100	10		T101	19
values[23]	8386	1			T33	6		T100	10		T101	17
values[24]	8010	1			T33	4		T100	10		T101	18
values[25]	7731	1			T33	6		T100	10		T101	16
values[26]	7701	1			T33	7		T100	10		T101	19
values[27]	7257	1			T33	2		T100	10		T101	16
values[28]	6908	1			T33	4		T100	10		T101	29
values[29]	6601	1			T33	2		T100	11		T101	28
values[30]	6237	1			T33	3		T100	10		T101	37
values[31]	5938	1			T33	5		T100	10		T101	32
values[32]	5513	1			T33	5		T100	10		T101	32
values[33]	5148	1			T33	4		T100	10		T101	15
values[34]	4796	1			T33	7		T100	10		T101	17
values[35]	4443	1			T33	6		T100	11		T101	21
values[36]	4243	1			T33	5		T100	10		T101	20
values[37]	3999	1			T33	3		T100	10		T101	12
values[38]	3797	1			T33	5		T100	11		T101	13
values[39]	3763	1			T33	3		T100	10		T101	16
values[40]	3722	1			T33	1		T100	10		T101	21
values[41]	3623	1			T33	1		T100	10		T101	27
values[42]	3425	1			T33	1		T100	11		T101	20
values[43]	3425	1			T33	1		T100	11		T101	21
values[44]	3241	1			T33	1		T100	10		T101	24
values[45]	3262	1			T33	1		T100	10		T101	19
values[46]	3168	1			T33	1		T100	10		T101	28
values[47]	3104	1			T33	2		T100	10		T101	26
values[48]	3097	1			T33	1		T100	10		T101	14
values[49]	3063	1			T33	3		T100	10		T101	7
values[50]	3012	1			T33	2		T100	10		T101	6
values[51]	2945	1			T33	1		T100	11		T101	11
values[52]	2900	1			T33	6		T100	12		T101	11
values[53]	2832	1			T33	1		T100	10		T101	7
values[54]	2820	1			T33	1		T100	10		T101	5
values[55]	2847	1			T33	1		T100	11		T101	11
values[56]	2758	1			T33	1		T100	11		T101	11
values[57]	2597	1			T33	2		T100	10		T101	9
values[58]	2625	1			T33	1		T100	10		T101	6
values[59]	2691	1			T33	1		T100	10		T101	10
values[60]	2693	1			T33	5		T100	10		T101	5
values[61]	3045	1			T33	10		T100	10		T101	7
values[62]	4990	1			T33	13		T100	10		T101	8
values[63]	18537	1			T33	11		T100	11		T101	18
values[64]	230131	1			T33	27		T100	1899		T101	81

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	4651825	1			T32	815		T33	14438		T34	117
values[2]	772733	1			T32	50		T33	2213		T34	28
values[3]	77347	1			T32	5		T33	333		T34	4
values[4]	14149	1			T33	50		T100	37		T101	57
values[5]	5779	1			T33	20		T100	4		T101	22
values[6]	3607	1			T33	28		T100	2		T101	6
values[7]	2695	1			T33	19		T100	1		T101	10
values[8]	2166	1			T33	26		T100	1		T101	17
values[9]	1884	1			T33	21		T100	1		T101	4
values[10]	1769	1			T33	17		T100	1		T231	1
values[11]	1576	1			T33	5		T100	1		T231	1
values[12]	1371	1			T100	1		T231	1		T782	1
values[13]	1358	1			T100	1		T231	1		T782	1
values[14]	1196	1			T100	1		T231	1		T782	1
values[15]	1096	1			T100	1		T231	1		T782	1
values[16]	1090	1			T100	1		T231	1		T782	1
values[17]	1018	1			T100	1		T231	1		T782	1
values[18]	986	1			T100	1		T231	1		T782	1
values[19]	928	1			T100	1		T231	1		T782	1
values[20]	872	1			T100	1		T231	1		T782	1
values[21]	843	1			T100	1		T231	1		T782	1
values[22]	879	1			T100	1		T231	1		T782	1
values[23]	841	1			T100	1		T231	1		T782	1
values[24]	805	1			T100	1		T231	1		T782	1
values[25]	709	1			T100	1		T231	1		T782	1
values[26]	687	1			T100	1		T231	1		T782	1
values[27]	658	1			T100	1		T231	1		T782	1
values[28]	678	1			T100	1		T231	1		T782	1
values[29]	666	1			T100	1		T231	1		T782	1
values[30]	610	1			T100	1		T231	1		T782	1
values[31]	594	1			T100	1		T231	1		T782	1
values[32]	591	1			T100	1		T231	1		T782	1
values[33]	562	1			T100	1		T231	2		T782	1
values[34]	538	1			T100	1		T231	1		T782	1
values[35]	560	1			T100	1		T231	1		T782	1
values[36]	547	1			T100	1		T231	1		T782	1
values[37]	518	1			T100	1		T231	1		T782	1
values[38]	491	1			T100	1		T231	1		T782	1
values[39]	527	1			T100	1		T231	1		T782	1
values[40]	522	1			T100	1		T231	1		T782	1
values[41]	544	1			T100	1		T231	1		T782	1
values[42]	498	1			T100	1		T231	1		T782	1
values[43]	463	1			T100	1		T231	1		T782	1
values[44]	473	1			T100	1		T231	1		T782	1
values[45]	460	1			T100	1		T231	1		T782	1
values[46]	433	1			T100	1		T231	1		T782	1
values[47]	415	1			T100	1		T231	1		T782	1
values[48]	392	1			T100	1		T231	1		T782	1
values[49]	416	1			T100	1		T231	1		T782	1
values[50]	391	1			T100	1		T231	1		T782	1
values[51]	415	1			T100	1		T231	1		T782	1
values[52]	404	1			T100	1		T231	1		T782	1
values[53]	382	1			T100	1		T231	1		T782	1
values[54]	381	1			T100	1		T231	1		T782	1
values[55]	404	1			T100	1		T231	1		T782	1
values[56]	393	1			T100	1		T231	1		T782	1
values[57]	390	1			T100	1		T231	1		T782	1
values[58]	390	1			T100	1		T231	1		T782	1
values[59]	379	1			T100	1		T231	1		T782	1
values[60]	396	1			T100	1		T231	1		T782	1
values[61]	423	1			T100	1		T231	1		T782	1
values[62]	758	1			T100	1		T231	1		T782	1
values[63]	3676	1			T100	1		T231	1		T782	17
values[64]	24552	1			T100	167		T231	214		T782	181

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	648528	1			T32	229		T33	243		T34	2
values[2]	2428403	1			T32	436		T33	5357		T34	84
values[3]	1134157	1			T32	58		T33	9060		T34	43
values[4]	161209	1			T32	1		T33	522		T34	2
values[5]	83570	1			T33	310		T100	10		T101	231
values[6]	54071	1			T33	223		T100	10		T101	125
values[7]	38499	1			T33	212		T100	10		T101	100
values[8]	30252	1			T33	124		T100	10		T101	86
values[9]	25197	1			T33	80		T100	10		T101	88
values[10]	22063	1			T33	64		T100	10		T101	90
values[11]	19417	1			T33	37		T100	10		T101	43
values[12]	17427	1			T33	33		T100	10		T101	30
values[13]	16089	1			T33	33		T100	10		T101	42
values[14]	14822	1			T33	45		T100	10		T101	38
values[15]	13954	1			T33	34		T100	10		T101	42
values[16]	13419	1			T33	17		T100	11		T101	40
values[17]	12922	1			T33	12		T100	10		T101	43
values[18]	12493	1			T33	10		T100	10		T101	38
values[19]	11561	1			T33	17		T100	10		T101	35
values[20]	11331	1			T33	19		T100	10		T101	35
values[21]	10872	1			T33	9		T100	10		T101	50
values[22]	10657	1			T33	10		T100	10		T101	42
values[23]	10430	1			T33	6		T100	10		T101	29
values[24]	9962	1			T33	9		T100	10		T101	27
values[25]	9560	1			T33	13		T100	10		T101	19
values[26]	9080	1			T33	13		T100	10		T101	19
values[27]	8421	1			T33	6		T100	10		T101	26
values[28]	7781	1			T33	6		T100	11		T101	21
values[29]	7535	1			T33	4		T100	10		T101	19
values[30]	7063	1			T33	9		T100	10		T101	17
values[31]	6446	1			T33	6		T100	11		T101	15
values[32]	6116	1			T33	5		T100	10		T101	17
values[33]	5565	1			T33	4		T100	10		T101	14
values[34]	5130	1			T33	5		T100	10		T101	12
values[35]	4898	1			T33	11		T100	10		T101	18
values[36]	4568	1			T33	5		T100	10		T101	29
values[37]	4478	1			T33	7		T100	10		T101	29
values[38]	4182	1			T33	10		T100	10		T101	22
values[39]	4119	1			T33	4		T100	12		T101	21
values[40]	3971	1			T33	9		T100	10		T101	22
values[41]	3876	1			T33	7		T100	10		T101	17
values[42]	3905	1			T33	3		T100	10		T101	19
values[43]	3799	1			T33	4		T100	10		T101	16
values[44]	3678	1			T33	4		T100	10		T101	20
values[45]	3704	1			T33	4		T100	10		T101	26
values[46]	3613	1			T33	2		T100	10		T101	27
values[47]	3522	1			T33	2		T100	10		T101	42
values[48]	3484	1			T33	3		T100	10		T101	17
values[49]	3465	1			T33	4		T100	10		T101	17
values[50]	3446	1			T33	7		T100	10		T101	17
values[51]	3396	1			T33	9		T100	10		T101	25
values[52]	3301	1			T33	9		T100	10		T101	14
values[53]	3305	1			T33	6		T100	10		T101	10
values[54]	3146	1			T33	5		T100	10		T101	11
values[55]	3147	1			T33	4		T100	10		T101	21
values[56]	3000	1			T33	5		T100	10		T101	11
values[57]	2985	1			T33	5		T100	10		T101	16
values[58]	3027	1			T33	7		T100	11		T101	25
values[59]	2912	1			T33	3		T100	10		T101	19
values[60]	2960	1			T33	5		T100	10		T101	13
values[61]	3077	1			T33	5		T100	10		T101	14
values[62]	4485	1			T33	6		T100	10		T101	11
values[63]	19302	1			T33	18		T100	189		T101	13
values[64]	219554	1			T33	85		T100	1723		T101	87