Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2644201	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

28265994

1

T29

1277

T30

2411

T31

1237

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	20202448	1			T29	2346		T30	4676		T31	2332
values[0x0]	8728072	1			T29	70		T30	41		T31	38
values[0x1]	1979675	1			T29	67		T30	30		T31	29

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	726204	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

30183991

1

T29

1687

T30

3183

T31

1612

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	14238012	1			T29	37		T30	55		T31	43
valid_sources[0x01]	14236855	1			T29	56		T30	41		T31	45
valid_sources[0x02]	38980	1			T29	45		T30	54		T31	30
valid_sources[0x03]	39218	1			T29	26		T30	42		T31	30
valid_sources[0x04]	39870	1			T29	32		T30	88		T31	34
valid_sources[0x05]	40003	1			T29	35		T30	83		T31	38
valid_sources[0x06]	39593	1			T29	32		T30	77		T31	30
valid_sources[0x07]	38851	1			T29	42		T30	121		T31	36
valid_sources[0x08]	39435	1			T29	38		T30	52		T31	26
valid_sources[0x09]	39494	1			T29	40		T30	44		T31	43
valid_sources[0x0a]	38957	1			T29	43		T30	89		T31	41
valid_sources[0x0b]	38668	1			T29	48		T30	119		T31	37
valid_sources[0x0c]	39109	1			T29	43		T30	28		T31	36
valid_sources[0x0d]	39685	1			T29	31		T30	71		T31	41
valid_sources[0x0e]	39275	1			T29	35		T30	61		T31	42
valid_sources[0x0f]	39033	1			T29	32		T30	93		T31	41
valid_sources[0x10]	39383	1			T29	41		T30	85		T31	47
valid_sources[0x11]	38863	1			T29	32		T30	72		T31	32
valid_sources[0x12]	38504	1			T29	32		T30	95		T31	27
valid_sources[0x13]	39558	1			T29	44		T30	55		T31	32
valid_sources[0x14]	38974	1			T29	42		T30	84		T31	29
valid_sources[0x15]	39180	1			T29	35		T30	102		T31	33
valid_sources[0x16]	39146	1			T29	33		T30	118		T31	39
valid_sources[0x17]	40160	1			T29	40		T30	75		T31	35
valid_sources[0x18]	40060	1			T29	39		T30	94		T31	28
valid_sources[0x19]	39429	1			T29	41		T30	63		T31	35
valid_sources[0x1a]	40154	1			T29	40		T30	58		T31	32
valid_sources[0x1b]	40375	1			T29	39		T30	60		T31	28
valid_sources[0x1c]	39883	1			T29	53		T30	73		T31	36
valid_sources[0x1d]	39105	1			T29	36		T30	79		T31	46
valid_sources[0x1e]	38742	1			T29	36		T30	47		T31	43
valid_sources[0x1f]	39867	1			T29	34		T30	60		T31	45
valid_sources[0x20]	39624	1			T29	38		T30	57		T31	37

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

19374094

1

T29

1146

T30

2341

T31

1170

values[0x0]

all_enables

biggest_size

8681057

1

T29

69

T30

41

T31

38

values[0x1]

all_enables

biggest_size

210843

1

T29

62

T30

29

T31

29

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2691949	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

424900

1

T32

2

T33

2392

T34

11

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1056100	1			T32	22		T33	5853		T34	40
values[0x0]	1003351	1			T32	4		T33	5723		T34	37
values[0x1]	1057398	1			T32	15		T33	5880		T34	39

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2083709	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1033140

1

T32

17

T33

5791

T34

32

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	48882	1			T33	288		T34	1		T100	42
valid_sources[0x01]	49542	1			T33	322		T100	37		T101	213
valid_sources[0x02]	49531	1			T33	242		T100	36		T58	1
valid_sources[0x03]	47888	1			T33	303		T100	38		T58	7
valid_sources[0x04]	47824	1			T33	287		T34	2		T100	38
valid_sources[0x05]	49399	1			T32	1		T33	265		T34	3
valid_sources[0x06]	48045	1			T32	1		T33	255		T100	47
valid_sources[0x07]	49370	1			T32	3		T33	246		T34	1
valid_sources[0x08]	48275	1			T32	1		T33	326		T34	3
valid_sources[0x09]	48617	1			T33	284		T100	38		T101	207
valid_sources[0x0a]	49378	1			T33	303		T100	37		T58	3
valid_sources[0x0b]	49452	1			T33	271		T100	44		T101	98
valid_sources[0x0c]	49490	1			T33	257		T34	5		T100	48
valid_sources[0x0d]	47355	1			T33	276		T100	48		T58	4
valid_sources[0x0e]	49757	1			T32	1		T33	259		T34	9
valid_sources[0x0f]	49144	1			T33	269		T100	38		T101	188
valid_sources[0x10]	48203	1			T33	284		T100	37		T101	226
valid_sources[0x11]	48701	1			T32	2		T33	226		T100	46
valid_sources[0x12]	46634	1			T33	282		T100	44		T101	198
valid_sources[0x13]	49194	1			T33	286		T100	51		T58	2
valid_sources[0x14]	49409	1			T32	2		T33	270		T100	29
valid_sources[0x15]	47882	1			T32	1		T33	242		T100	37
valid_sources[0x16]	48413	1			T32	3		T33	252		T34	7
valid_sources[0x17]	48354	1			T32	2		T33	283		T34	7
valid_sources[0x18]	48564	1			T33	302		T100	46		T101	156
valid_sources[0x19]	48546	1			T33	277		T100	42		T58	18
valid_sources[0x1a]	49343	1			T32	1		T33	256		T34	3
valid_sources[0x1b]	48777	1			T33	273		T34	7		T100	40
valid_sources[0x1c]	48468	1			T33	295		T100	35		T58	4
valid_sources[0x1d]	48282	1			T33	256		T100	41		T58	2
valid_sources[0x1e]	49364	1			T33	272		T100	42		T58	3
valid_sources[0x1f]	49088	1			T32	4		T33	256		T34	4
valid_sources[0x20]	49102	1			T32	1		T33	282		T100	47

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

44788

1

T32

1

T33

250

T100

44

values[0x0]

all_enables

biggest_size

335491

1

T32

1

T33

1922

T34

10

values[0x1]

all_enables

biggest_size

44621

1

T33

220

T34

1

T100

30

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2864690	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

466323

1

T32

4

T33

2390

T34

21

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1143519	1			T32	18		T33	5948		T34	55
values[0x0]	1047040	1			T32	4		T33	5457		T34	42
values[0x1]	1140454	1			T32	17		T33	5765		T34	52

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2197648	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1133365

1

T32

17

T33

5854

T34

58

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	52473	1			T33	249		T34	4		T100	53
valid_sources[0x01]	52200	1			T33	276		T100	25		T58	3
valid_sources[0x02]	53062	1			T32	2		T33	258		T34	4
valid_sources[0x03]	51873	1			T33	260		T100	40		T58	5
valid_sources[0x04]	51011	1			T33	254		T34	1		T100	22
valid_sources[0x05]	51380	1			T32	1		T33	270		T100	26
valid_sources[0x06]	52330	1			T32	1		T33	270		T34	2
valid_sources[0x07]	52810	1			T32	1		T33	259		T34	5
valid_sources[0x08]	52175	1			T33	266		T100	33		T101	231
valid_sources[0x09]	52728	1			T33	285		T34	1		T100	41
valid_sources[0x0a]	52771	1			T33	289		T34	3		T100	40
valid_sources[0x0b]	51904	1			T32	1		T33	290		T34	1
valid_sources[0x0c]	53353	1			T32	2		T33	288		T34	3
valid_sources[0x0d]	51323	1			T33	267		T34	3		T100	47
valid_sources[0x0e]	51710	1			T32	3		T33	237		T34	7
valid_sources[0x0f]	52586	1			T33	292		T34	7		T100	30
valid_sources[0x10]	52223	1			T33	257		T34	1		T100	39
valid_sources[0x11]	52479	1			T33	248		T34	2		T100	33
valid_sources[0x12]	52364	1			T33	282		T100	56		T58	3
valid_sources[0x13]	51655	1			T33	243		T34	4		T100	46
valid_sources[0x14]	51453	1			T32	1		T33	263		T34	2
valid_sources[0x15]	51398	1			T33	261		T34	6		T100	61
valid_sources[0x16]	51335	1			T33	261		T34	2		T100	32
valid_sources[0x17]	51661	1			T32	1		T33	284		T34	3
valid_sources[0x18]	51351	1			T32	1		T33	298		T34	2
valid_sources[0x19]	51850	1			T32	2		T33	272		T100	40
valid_sources[0x1a]	52386	1			T33	270		T34	2		T100	32
valid_sources[0x1b]	52337	1			T33	233		T34	1		T100	43
valid_sources[0x1c]	52330	1			T33	262		T34	1		T100	41
valid_sources[0x1d]	51963	1			T33	257		T34	2		T100	53
valid_sources[0x1e]	51608	1			T32	1		T33	290		T34	2
valid_sources[0x1f]	52424	1			T32	2		T33	235		T34	5
valid_sources[0x20]	52424	1			T32	1		T33	259		T34	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

49264

1

T33

258

T34

3

T100

49

values[0x0]

all_enables

biggest_size

367881

1

T32

2

T33

1919

T34

17

values[0x1]

all_enables

biggest_size

49178

1

T32

2

T33

213

T34

1

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2710005	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

427621

1

T32

3

T33

2289

T34

19

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1063081	1			T32	17		T33	5751		T34	47
values[0x0]	1010294	1			T32	4		T33	5513		T34	36
values[0x1]	1064251	1			T32	16		T33	5551		T34	48

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2097883	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1039743

1

T32

10

T33

5622

T34

45

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	49476	1			T32	1		T33	253		T100	41
valid_sources[0x01]	48805	1			T32	1		T33	304		T34	2
valid_sources[0x02]	48762	1			T33	293		T100	38		T101	118
valid_sources[0x03]	48680	1			T33	281		T100	35		T101	162
valid_sources[0x04]	49111	1			T33	280		T34	2		T100	49
valid_sources[0x05]	49042	1			T33	308		T34	2		T100	34
valid_sources[0x06]	49026	1			T33	324		T34	4		T100	37
valid_sources[0x07]	49001	1			T33	257		T100	41		T58	5
valid_sources[0x08]	48384	1			T33	265		T34	10		T100	35
valid_sources[0x09]	49722	1			T33	241		T34	3		T100	37
valid_sources[0x0a]	49614	1			T32	2		T33	218		T100	53
valid_sources[0x0b]	49530	1			T32	1		T33	252		T34	1
valid_sources[0x0c]	48991	1			T32	1		T33	285		T34	9
valid_sources[0x0d]	48150	1			T32	1		T33	232		T34	6
valid_sources[0x0e]	49010	1			T32	1		T33	299		T34	1
valid_sources[0x0f]	49743	1			T32	2		T33	262		T100	37
valid_sources[0x10]	49554	1			T32	1		T33	274		T100	31
valid_sources[0x11]	48343	1			T32	2		T33	249		T100	38
valid_sources[0x12]	48768	1			T33	229		T100	36		T101	212
valid_sources[0x13]	48883	1			T32	3		T33	266		T100	49
valid_sources[0x14]	48842	1			T33	236		T100	38		T101	156
valid_sources[0x15]	48664	1			T32	2		T33	215		T100	33
valid_sources[0x16]	48620	1			T33	307		T34	1		T100	45
valid_sources[0x17]	49345	1			T33	276		T100	45		T58	2
valid_sources[0x18]	49460	1			T32	1		T33	240		T34	11
valid_sources[0x19]	49328	1			T32	1		T33	320		T34	1
valid_sources[0x1a]	49004	1			T32	1		T33	285		T100	38
valid_sources[0x1b]	49126	1			T32	2		T33	256		T100	33
valid_sources[0x1c]	49358	1			T33	293		T34	1		T100	39
valid_sources[0x1d]	49204	1			T33	210		T34	5		T100	37
valid_sources[0x1e]	48679	1			T33	268		T100	31		T58	1
valid_sources[0x1f]	49204	1			T33	223		T34	9		T100	41
valid_sources[0x20]	48956	1			T33	237		T34	2		T100	42

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

45290

1

T32

1

T33

257

T34

4

values[0x0]

all_enables

biggest_size

337454

1

T33

1810

T34

11

T100

294

values[0x1]

all_enables

biggest_size

44877

1

T32

2

T33

222

T34

4