Go back

 LINE       17595
 EXPRESSION (addr_hit[192] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T59,T56,T57
1	0	1	Covered	T29,T30,T31
1	1	0	Covered	T321,T411,T433
1	1	1	Covered	T59,T56,T57

 LINE       17660
 EXPRESSION (addr_hit[193] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T59,T56,T57
1	0	1	Covered	T29,T30,T31
1	1	0	Covered	T403,T411,T427
1	1	1	Covered	T59,T56,T57

 LINE       17725
 EXPRESSION (addr_hit[194] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T59,T56,T57
1	0	1	Covered	T29,T30,T31
1	1	0	Covered	T495,T653,T654
1	1	1	Covered	T59,T56,T57

 LINE       17790
 EXPRESSION (addr_hit[195] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T59,T56,T57
1	0	1	Covered	T29,T30,T31
1	1	0	Covered	T403,T433,T434
1	1	1	Covered	T59,T56,T57

 LINE       17855
 EXPRESSION (addr_hit[196] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T59,T56,T57
1	0	1	Covered	T29,T30,T31
1	1	0	Covered	T321,T403,T401
1	1	1	Covered	T59,T56,T57

 LINE       17906
 EXPRESSION (addr_hit[197] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T59,T56,T57
1	0	1	Covered	T29,T30,T31
1	1	0	Covered	T403,T433,T404
1	1	1	Covered	T59,T56,T57

 LINE       17909
 EXPRESSION (addr_hit[198] & reg_re & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T29,T30,T31
1	0	1	Covered	T59,T56,T57
1	1	0	Not Covered
1	1	1	Covered	T29,T30,T31

 LINE       17910
 EXPRESSION (addr_hit[198] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T59,T56,T57
1	0	1	Covered	T29,T30,T31
1	1	0	Covered	T411,T404,T434
1	1	1	Covered	T59,T56,T57

 LINE       17913
 EXPRESSION (addr_hit[199] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T59,T56,T57
1	0	1	Covered	T29,T30,T31
1	1	0	Covered	T321,T401,T411
1	1	1	Covered	T59,T56,T57

 LINE       17916
 EXPRESSION (addr_hit[200] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T59,T56,T57
1	0	1	Covered	T29,T30,T31
1	1	0	Covered	T321,T403,T401
1	1	1	Covered	T59,T56,T57