Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : rv_plic_reg_top
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.98 100.00 99.90 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_rv_plic_0/rtl/rv_plic_reg_top.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_rv_plic.u_reg 99.98 100.00 99.90 100.00 100.00

Line Coverage for Module : rv_plic_reg_top
Line No.TotalCoveredPercent
TOTAL15521552100.00
ALWAYS7144100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN12111100.00
CONT_ASSIGN12211100.00
CONT_ASSIGN1649411100.00
CONT_ASSIGN1650811100.00
CONT_ASSIGN1654211100.00
CONT_ASSIGN1655611100.00
ALWAYS16562202202100.00
CONT_ASSIGN1676611100.00
ALWAYS1677011100.00
CONT_ASSIGN1697511100.00
CONT_ASSIGN1697711100.00
CONT_ASSIGN1697811100.00
CONT_ASSIGN1698011100.00
CONT_ASSIGN1698111100.00
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CONT_ASSIGN1698711100.00
CONT_ASSIGN1698911100.00
CONT_ASSIGN1699011100.00
CONT_ASSIGN1699211100.00
CONT_ASSIGN1699311100.00
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CONT_ASSIGN1700811100.00
CONT_ASSIGN1701011100.00
CONT_ASSIGN1701111100.00
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CONT_ASSIGN1702211100.00
CONT_ASSIGN1702311100.00
CONT_ASSIGN1702511100.00
CONT_ASSIGN1702611100.00
CONT_ASSIGN1702811100.00
CONT_ASSIGN1702911100.00
CONT_ASSIGN1703111100.00
CONT_ASSIGN1703211100.00
CONT_ASSIGN1703411100.00
CONT_ASSIGN1703511100.00
CONT_ASSIGN1703711100.00
CONT_ASSIGN1703811100.00
CONT_ASSIGN1704011100.00
CONT_ASSIGN1704111100.00
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CONT_ASSIGN1713011100.00
CONT_ASSIGN1713111100.00
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CONT_ASSIGN1728911100.00
CONT_ASSIGN1729011100.00
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CONT_ASSIGN1730811100.00
CONT_ASSIGN1731011100.00
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CONT_ASSIGN1731311100.00
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CONT_ASSIGN1731711100.00
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CONT_ASSIGN1732011100.00
CONT_ASSIGN1732211100.00
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CONT_ASSIGN1732511100.00
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CONT_ASSIGN1733511100.00
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CONT_ASSIGN1733811100.00
CONT_ASSIGN1734011100.00
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CONT_ASSIGN1742711100.00
CONT_ASSIGN1742811100.00
CONT_ASSIGN1743011100.00
CONT_ASSIGN1743111100.00
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CONT_ASSIGN1743711100.00
CONT_ASSIGN1743911100.00
CONT_ASSIGN1744011100.00
CONT_ASSIGN1744211100.00
CONT_ASSIGN1744311100.00
CONT_ASSIGN1744511100.00
CONT_ASSIGN1744611100.00
CONT_ASSIGN1744811100.00
CONT_ASSIGN1744911100.00
CONT_ASSIGN1745111100.00
CONT_ASSIGN1745211100.00
CONT_ASSIGN1745411100.00
CONT_ASSIGN1745511100.00
CONT_ASSIGN1745711100.00
CONT_ASSIGN1745811100.00
CONT_ASSIGN1746011100.00
CONT_ASSIGN1746111100.00
CONT_ASSIGN1746311100.00
CONT_ASSIGN1746411100.00
CONT_ASSIGN1746611100.00
CONT_ASSIGN1746711100.00
CONT_ASSIGN1746911100.00
CONT_ASSIGN1747011100.00
CONT_ASSIGN1747211100.00
CONT_ASSIGN1747311100.00
CONT_ASSIGN1747511100.00
CONT_ASSIGN1747611100.00
CONT_ASSIGN1747811100.00
CONT_ASSIGN1747911100.00
CONT_ASSIGN1748111100.00
CONT_ASSIGN1748211100.00
CONT_ASSIGN1748411100.00
CONT_ASSIGN1748511100.00
CONT_ASSIGN1748711100.00
CONT_ASSIGN1748811100.00
CONT_ASSIGN1749011100.00
CONT_ASSIGN1749111100.00
CONT_ASSIGN1749311100.00
CONT_ASSIGN1749411100.00
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CONT_ASSIGN1749711100.00
CONT_ASSIGN1749911100.00
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CONT_ASSIGN1750211100.00
CONT_ASSIGN1750311100.00
CONT_ASSIGN1750511100.00
CONT_ASSIGN1750611100.00
CONT_ASSIGN1750811100.00
CONT_ASSIGN1750911100.00
CONT_ASSIGN1751111100.00
CONT_ASSIGN1751211100.00
CONT_ASSIGN1751411100.00
CONT_ASSIGN1751511100.00
CONT_ASSIGN1751711100.00
CONT_ASSIGN1751811100.00
CONT_ASSIGN1752011100.00
CONT_ASSIGN1752111100.00
CONT_ASSIGN1752311100.00
CONT_ASSIGN1752411100.00
CONT_ASSIGN1752611100.00
CONT_ASSIGN1752711100.00
CONT_ASSIGN1752911100.00
CONT_ASSIGN1753011100.00
CONT_ASSIGN1753211100.00
CONT_ASSIGN1753411100.00
CONT_ASSIGN1753611100.00
CONT_ASSIGN1753811100.00
CONT_ASSIGN1754011100.00
CONT_ASSIGN1754211100.00
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CONT_ASSIGN1755011100.00
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CONT_ASSIGN1756011100.00
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CONT_ASSIGN1757011100.00
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CONT_ASSIGN1757611100.00
CONT_ASSIGN1757811100.00
CONT_ASSIGN1758011100.00
CONT_ASSIGN1758211100.00
CONT_ASSIGN1758411100.00
CONT_ASSIGN1758611100.00
CONT_ASSIGN1758811100.00
CONT_ASSIGN1759011100.00
CONT_ASSIGN1759211100.00
CONT_ASSIGN1759411100.00
CONT_ASSIGN1759511100.00
CONT_ASSIGN1759711100.00
CONT_ASSIGN1759911100.00
CONT_ASSIGN1760111100.00
CONT_ASSIGN1760311100.00
CONT_ASSIGN1760511100.00
CONT_ASSIGN1760711100.00
CONT_ASSIGN1760911100.00
CONT_ASSIGN1761111100.00
CONT_ASSIGN1761311100.00
CONT_ASSIGN1761511100.00
CONT_ASSIGN1761711100.00
CONT_ASSIGN1761911100.00
CONT_ASSIGN1762111100.00
CONT_ASSIGN1762311100.00
CONT_ASSIGN1762511100.00
CONT_ASSIGN1762711100.00
CONT_ASSIGN1762911100.00
CONT_ASSIGN1763111100.00
CONT_ASSIGN1763311100.00
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CONT_ASSIGN1763711100.00
CONT_ASSIGN1763911100.00
CONT_ASSIGN1764111100.00
CONT_ASSIGN1764311100.00
CONT_ASSIGN1764511100.00
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CONT_ASSIGN1764911100.00
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CONT_ASSIGN1778711100.00
CONT_ASSIGN1778911100.00
CONT_ASSIGN1779011100.00
CONT_ASSIGN1779211100.00
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CONT_ASSIGN1779611100.00
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CONT_ASSIGN1780011100.00
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CONT_ASSIGN1780611100.00
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CONT_ASSIGN1787111100.00
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CONT_ASSIGN1787911100.00
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CONT_ASSIGN1788511100.00
CONT_ASSIGN1788711100.00
CONT_ASSIGN1788911100.00
CONT_ASSIGN1789111100.00
CONT_ASSIGN1789311100.00
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CONT_ASSIGN1791211100.00
CONT_ASSIGN1791311100.00
CONT_ASSIGN1791511100.00
CONT_ASSIGN1791611100.00
CONT_ASSIGN1791811100.00
ALWAYS17922202202100.00
ALWAYS18128561561100.00
CONT_ASSIGN1930300
CONT_ASSIGN1931111100.00
CONT_ASSIGN1931211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_rv_plic_0/rtl/rv_plic_reg_top.sv' or '../src/lowrisc_opentitan_top_earlgrey_rv_plic_0/rtl/rv_plic_reg_top.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
71 1 1
72 1 1
73 1 1
74 1 1
MISSING_ELSE
80 1 1
92 1 1
93 1 1
121 1 1
122 1 1
16494 1 1
16508 1 1
16542 1 1
16556 1 1
16562 1 1
16563 1 1
16564 1 1
16565 1 1
16566 1 1
16567 1 1
16568 1 1
16569 1 1
16570 1 1
16571 1 1
16572 1 1
16573 1 1
16574 1 1
16575 1 1
16576 1 1
16577 1 1
16578 1 1
16579 1 1
16580 1 1
16581 1 1
16582 1 1
16583 1 1
16584 1 1
16585 1 1
16586 1 1
16587 1 1
16588 1 1
16589 1 1
16590 1 1
16591 1 1
16592 1 1
16593 1 1
16594 1 1
16595 1 1
16596 1 1
16597 1 1
16598 1 1
16599 1 1
16600 1 1
16601 1 1
16602 1 1
16603 1 1
16604 1 1
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16608 1 1
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16610 1 1
16611 1 1
16612 1 1
16613 1 1
16614 1 1
16615 1 1
16616 1 1
16617 1 1
16618 1 1
16619 1 1
16620 1 1
16621 1 1
16622 1 1
16623 1 1
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16625 1 1
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16660 1 1
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16680 1 1
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16685 1 1
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19228 1 1
19229 1 1
19230 1 1
19231 1 1
19232 1 1
19233 1 1
19234 1 1
19235 1 1
19236 1 1
19237 1 1
19238 1 1
19239 1 1
19240 1 1
19241 1 1
19242 1 1
19243 1 1
19244 1 1
19245 1 1
19249 1 1
19250 1 1
19251 1 1
19252 1 1
19253 1 1
19254 1 1
19255 1 1
19256 1 1
19257 1 1
19258 1 1
19259 1 1
19260 1 1
19261 1 1
19262 1 1
19263 1 1
19264 1 1
19265 1 1
19266 1 1
19267 1 1
19268 1 1
19269 1 1
19270 1 1
19271 1 1
19272 1 1
19273 1 1
19277 1 1
19281 1 1
19285 1 1
19289 1 1
19303 unreachable
19311 1 1
19312 1 1


Cond Coverage for Module : rv_plic_reg_top
TotalCoveredPercent
Conditions2015201399.90
Logical2015201399.90
Non-Logical00
Event00

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.
Line numbersPercent
61-1674199.73
16742-16770100.00
16770100.00
16770-17215100.00
17218-17530100.00
17595-1791697.50

Branch Coverage for Module : rv_plic_reg_top
Line No.TotalCoveredPercent
Branches 207 207 100.00
TERNARY 16766 2 2 100.00
IF 71 3 3 100.00
CASE 18129 202 202 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_rv_plic_0/rtl/rv_plic_reg_top.sv' or '../src/lowrisc_opentitan_top_earlgrey_rv_plic_0/rtl/rv_plic_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 16766 ((reg_re || reg_we)) ?

Branches:
-1-StatusTests
1 Covered T32,T33,T58
0 Covered T32,T33,T34


LineNo. Expression -1-: 71 if ((!rst_ni)) -2-: 73 if ((intg_err || reg_we_err))

Branches:
-1--2-StatusTests
1 - Covered T29,T30,T31
0 1 Covered T638,T639,T640
0 0 Covered T29,T30,T31


LineNo. Expression -1-: 18129 case (1'b1)

Branches:
-1-StatusTests
addr_hit[0] Covered T32,T33,T34
addr_hit[1] Covered T29,T30,T31
addr_hit[2] Covered T29,T30,T31
addr_hit[3] Covered T29,T30,T31
addr_hit[4] Covered T29,T30,T31
addr_hit[5] Covered T29,T30,T31
addr_hit[6] Covered T29,T30,T31
addr_hit[7] Covered T29,T30,T31
addr_hit[8] Covered T29,T30,T31
addr_hit[9] Covered T29,T30,T31
addr_hit[10] Covered T29,T30,T31
addr_hit[11] Covered T29,T30,T31
addr_hit[12] Covered T29,T30,T31
addr_hit[13] Covered T29,T30,T31
addr_hit[14] Covered T29,T30,T31
addr_hit[15] Covered T29,T30,T31
addr_hit[16] Covered T29,T30,T31
addr_hit[17] Covered T29,T30,T31
addr_hit[18] Covered T29,T30,T31
addr_hit[19] Covered T29,T30,T31
addr_hit[20] Covered T29,T30,T31
addr_hit[21] Covered T29,T30,T31
addr_hit[22] Covered T29,T30,T31
addr_hit[23] Covered T29,T30,T31
addr_hit[24] Covered T29,T30,T31
addr_hit[25] Covered T29,T30,T31
addr_hit[26] Covered T29,T30,T31
addr_hit[27] Covered T29,T30,T31
addr_hit[28] Covered T29,T30,T31
addr_hit[29] Covered T29,T30,T31
addr_hit[30] Covered T29,T30,T31
addr_hit[31] Covered T29,T30,T31
addr_hit[32] Covered T29,T30,T31
addr_hit[33] Covered T29,T30,T31
addr_hit[34] Covered T29,T30,T31
addr_hit[35] Covered T29,T30,T31
addr_hit[36] Covered T29,T30,T31
addr_hit[37] Covered T29,T30,T31
addr_hit[38] Covered T29,T30,T31
addr_hit[39] Covered T29,T30,T31
addr_hit[40] Covered T29,T30,T31
addr_hit[41] Covered T29,T30,T31
addr_hit[42] Covered T29,T30,T31
addr_hit[43] Covered T29,T30,T31
addr_hit[44] Covered T29,T30,T31
addr_hit[45] Covered T29,T30,T31
addr_hit[46] Covered T29,T30,T31
addr_hit[47] Covered T29,T30,T31
addr_hit[48] Covered T29,T30,T31
addr_hit[49] Covered T29,T30,T31
addr_hit[50] Covered T29,T30,T31
addr_hit[51] Covered T29,T30,T31
addr_hit[52] Covered T29,T30,T31
addr_hit[53] Covered T29,T30,T31
addr_hit[54] Covered T29,T30,T31
addr_hit[55] Covered T29,T30,T31
addr_hit[56] Covered T29,T30,T31
addr_hit[57] Covered T29,T30,T31
addr_hit[58] Covered T29,T30,T31
addr_hit[59] Covered T29,T30,T31
addr_hit[60] Covered T29,T30,T31
addr_hit[61] Covered T29,T30,T31
addr_hit[62] Covered T29,T30,T31
addr_hit[63] Covered T29,T30,T31
addr_hit[64] Covered T29,T30,T31
addr_hit[65] Covered T29,T30,T31
addr_hit[66] Covered T29,T30,T31
addr_hit[67] Covered T29,T30,T31
addr_hit[68] Covered T29,T30,T31
addr_hit[69] Covered T29,T30,T31
addr_hit[70] Covered T29,T30,T31
addr_hit[71] Covered T29,T30,T31
addr_hit[72] Covered T29,T30,T31
addr_hit[73] Covered T29,T30,T31
addr_hit[74] Covered T29,T30,T31
addr_hit[75] Covered T29,T30,T31
addr_hit[76] Covered T29,T30,T31
addr_hit[77] Covered T29,T30,T31
addr_hit[78] Covered T29,T30,T31
addr_hit[79] Covered T29,T30,T31
addr_hit[80] Covered T29,T30,T31
addr_hit[81] Covered T29,T30,T31
addr_hit[82] Covered T29,T30,T31
addr_hit[83] Covered T29,T30,T31
addr_hit[84] Covered T29,T30,T31
addr_hit[85] Covered T29,T30,T31
addr_hit[86] Covered T29,T30,T31
addr_hit[87] Covered T29,T30,T31
addr_hit[88] Covered T29,T30,T31
addr_hit[89] Covered T29,T30,T31
addr_hit[90] Covered T29,T30,T31
addr_hit[91] Covered T29,T30,T31
addr_hit[92] Covered T29,T30,T31
addr_hit[93] Covered T29,T30,T31
addr_hit[94] Covered T29,T30,T31
addr_hit[95] Covered T29,T30,T31
addr_hit[96] Covered T29,T30,T31
addr_hit[97] Covered T29,T30,T31
addr_hit[98] Covered T29,T30,T31
addr_hit[99] Covered T29,T30,T31
addr_hit[100] Covered T29,T30,T31
addr_hit[101] Covered T29,T30,T31
addr_hit[102] Covered T29,T30,T31
addr_hit[103] Covered T29,T30,T31
addr_hit[104] Covered T29,T30,T31
addr_hit[105] Covered T29,T30,T31
addr_hit[106] Covered T29,T30,T31
addr_hit[107] Covered T29,T30,T31
addr_hit[108] Covered T29,T30,T31
addr_hit[109] Covered T29,T30,T31
addr_hit[110] Covered T29,T30,T31
addr_hit[111] Covered T29,T30,T31
addr_hit[112] Covered T29,T30,T31
addr_hit[113] Covered T29,T30,T31
addr_hit[114] Covered T29,T30,T31
addr_hit[115] Covered T29,T30,T31
addr_hit[116] Covered T29,T30,T31
addr_hit[117] Covered T29,T30,T31
addr_hit[118] Covered T29,T30,T31
addr_hit[119] Covered T29,T30,T31
addr_hit[120] Covered T29,T30,T31
addr_hit[121] Covered T29,T30,T31
addr_hit[122] Covered T29,T30,T31
addr_hit[123] Covered T29,T30,T31
addr_hit[124] Covered T29,T30,T31
addr_hit[125] Covered T29,T30,T31
addr_hit[126] Covered T29,T30,T31
addr_hit[127] Covered T29,T30,T31
addr_hit[128] Covered T29,T30,T31
addr_hit[129] Covered T29,T30,T31
addr_hit[130] Covered T29,T30,T31
addr_hit[131] Covered T29,T30,T31
addr_hit[132] Covered T29,T30,T31
addr_hit[133] Covered T29,T30,T31
addr_hit[134] Covered T29,T30,T31
addr_hit[135] Covered T29,T30,T31
addr_hit[136] Covered T29,T30,T31
addr_hit[137] Covered T29,T30,T31
addr_hit[138] Covered T29,T30,T31
addr_hit[139] Covered T29,T30,T31
addr_hit[140] Covered T29,T30,T31
addr_hit[141] Covered T29,T30,T31
addr_hit[142] Covered T29,T30,T31
addr_hit[143] Covered T29,T30,T31
addr_hit[144] Covered T29,T30,T31
addr_hit[145] Covered T29,T30,T31
addr_hit[146] Covered T29,T30,T31
addr_hit[147] Covered T29,T30,T31
addr_hit[148] Covered T29,T30,T31
addr_hit[149] Covered T29,T30,T31
addr_hit[150] Covered T29,T30,T31
addr_hit[151] Covered T29,T30,T31
addr_hit[152] Covered T29,T30,T31
addr_hit[153] Covered T29,T30,T31
addr_hit[154] Covered T29,T30,T31
addr_hit[155] Covered T29,T30,T31
addr_hit[156] Covered T29,T30,T31
addr_hit[157] Covered T29,T30,T31
addr_hit[158] Covered T29,T30,T31
addr_hit[159] Covered T29,T30,T31
addr_hit[160] Covered T29,T30,T31
addr_hit[161] Covered T29,T30,T31
addr_hit[162] Covered T29,T30,T31
addr_hit[163] Covered T29,T30,T31
addr_hit[164] Covered T29,T30,T31
addr_hit[165] Covered T29,T30,T31
addr_hit[166] Covered T29,T30,T31
addr_hit[167] Covered T29,T30,T31
addr_hit[168] Covered T29,T30,T31
addr_hit[169] Covered T29,T30,T31
addr_hit[170] Covered T29,T30,T31
addr_hit[171] Covered T29,T30,T31
addr_hit[172] Covered T29,T30,T31
addr_hit[173] Covered T29,T30,T31
addr_hit[174] Covered T29,T30,T31
addr_hit[175] Covered T29,T30,T31
addr_hit[176] Covered T29,T30,T31
addr_hit[177] Covered T29,T30,T31
addr_hit[178] Covered T29,T30,T31
addr_hit[179] Covered T29,T30,T31
addr_hit[180] Covered T29,T30,T31
addr_hit[181] Covered T29,T30,T31
addr_hit[182] Covered T29,T30,T31
addr_hit[183] Covered T29,T30,T31
addr_hit[184] Covered T29,T30,T31
addr_hit[185] Covered T29,T30,T31
addr_hit[186] Covered T29,T30,T31
addr_hit[187] Covered T29,T30,T31
addr_hit[188] Covered T29,T30,T31
addr_hit[189] Covered T29,T30,T31
addr_hit[190] Covered T29,T30,T31
addr_hit[191] Covered T29,T30,T31
addr_hit[192] Covered T29,T30,T31
addr_hit[193] Covered T29,T30,T31
addr_hit[194] Covered T29,T30,T31
addr_hit[195] Covered T29,T30,T31
addr_hit[196] Covered T29,T30,T31
addr_hit[197] Covered T29,T30,T31
addr_hit[198] Covered T29,T30,T31
addr_hit[199] Covered T29,T30,T31
addr_hit[200] Covered T29,T30,T31
default Covered T32,T33,T34


Assert Coverage for Module : rv_plic_reg_top
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
en2addrHit 473364705 265274 0 0
reAfterRv 473364705 265274 0 0
rePulse 473364705 180299 0 0
wePulse 473364705 84975 0 0


en2addrHit
NameAttemptsReal SuccessesFailuresIncomplete
Total 473364705 265274 0 0
T20 697375 45 0 0
T21 198182 15 0 0
T22 211682 47 0 0
T29 106680 201 0 0
T30 180500 402 0 0
T31 111128 201 0 0
T56 262952 4353 0 0
T57 271238 4014 0 0
T59 366991 1000 0 0
T136 213239 47 0 0

reAfterRv
NameAttemptsReal SuccessesFailuresIncomplete
Total 473364705 265274 0 0
T20 697375 45 0 0
T21 198182 15 0 0
T22 211682 47 0 0
T29 106680 201 0 0
T30 180500 402 0 0
T31 111128 201 0 0
T56 262952 4353 0 0
T57 271238 4014 0 0
T59 366991 1000 0 0
T136 213239 47 0 0

rePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 473364705 180299 0 0
T20 697375 18 0 0
T21 198182 5 0 0
T22 211682 19 0 0
T29 106680 201 0 0
T30 180500 402 0 0
T31 111128 201 0 0
T56 262952 2140 0 0
T57 271238 1945 0 0
T59 366991 598 0 0
T136 213239 19 0 0

wePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 473364705 84975 0 0
T7 0 4 0 0
T20 697375 27 0 0
T21 198182 10 0 0
T22 211682 28 0 0
T38 0 30 0 0
T56 262952 2213 0 0
T57 271238 2069 0 0
T59 366991 402 0 0
T90 454672 0 0 0
T104 250774 0 0 0
T136 213239 28 0 0
T137 75221 0 0 0
T172 0 28 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%