Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : sensor_ctrl
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.37 90.41 83.05 93.39 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_systems_sensor_ctrl_0.1/rtl/sensor_ctrl.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_sensor_ctrl_aon 93.37 90.41 83.05 93.39 100.00 100.00



Module Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.37 90.41 83.05 93.39 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.73 92.23 89.39 93.39 93.65 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.41 90.68 92.56 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_alert_sync_assign[0].u_alert_in_buf 100.00 100.00
gen_alert_sync_assign[10].u_alert_in_buf 100.00 100.00
gen_alert_sync_assign[1].u_alert_in_buf 100.00 100.00
gen_alert_sync_assign[2].u_alert_in_buf 100.00 100.00
gen_alert_sync_assign[3].u_alert_in_buf 100.00 100.00
gen_alert_sync_assign[4].u_alert_in_buf 100.00 100.00
gen_alert_sync_assign[5].u_alert_in_buf 100.00 100.00
gen_alert_sync_assign[6].u_alert_in_buf 100.00 100.00
gen_alert_sync_assign[7].u_alert_in_buf 100.00 100.00
gen_alert_sync_assign[8].u_alert_in_buf 100.00 100.00
gen_alert_sync_assign[9].u_alert_in_buf 100.00 100.00
u_alert_n_sync 100.00 100.00 100.00
u_alert_p_sync 100.00 100.00 100.00
u_init_chg 100.00 100.00 100.00 100.00
u_init_intr 100.00 100.00 100.00 100.00 100.00
u_io_intr 100.00 100.00 100.00 100.00 100.00
u_io_status_chg 100.00 100.00 100.00
u_reg 93.69 91.57 90.12 93.06 100.00
u_wake_sync 100.00 100.00 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : sensor_ctrl
Line No.TotalCoveredPercent
TOTAL736690.41
ALWAYS18000
ALWAYS18022100.00
CONT_ASSIGN19411100.00
CONT_ASSIGN19411100.00
CONT_ASSIGN19411100.00
CONT_ASSIGN19411100.00
CONT_ASSIGN19411100.00
CONT_ASSIGN19411100.00
CONT_ASSIGN19411100.00
CONT_ASSIGN19411100.00
CONT_ASSIGN19411100.00
CONT_ASSIGN19411100.00
CONT_ASSIGN19411100.00
CONT_ASSIGN19511100.00
CONT_ASSIGN19511100.00
CONT_ASSIGN19511100.00
CONT_ASSIGN19511100.00
CONT_ASSIGN19511100.00
CONT_ASSIGN19511100.00
CONT_ASSIGN19511100.00
CONT_ASSIGN19511100.00
CONT_ASSIGN19511100.00
CONT_ASSIGN19511100.00
CONT_ASSIGN19511100.00
CONT_ASSIGN19811100.00
CONT_ASSIGN19811100.00
CONT_ASSIGN19811100.00
CONT_ASSIGN19811100.00
CONT_ASSIGN19811100.00
CONT_ASSIGN19811100.00
CONT_ASSIGN19811100.00
CONT_ASSIGN19811100.00
CONT_ASSIGN19811100.00
CONT_ASSIGN19811100.00
CONT_ASSIGN19811100.00
CONT_ASSIGN20111100.00
CONT_ASSIGN201100.00
CONT_ASSIGN20111100.00
CONT_ASSIGN201100.00
CONT_ASSIGN20111100.00
CONT_ASSIGN201100.00
CONT_ASSIGN20111100.00
CONT_ASSIGN201100.00
CONT_ASSIGN201100.00
CONT_ASSIGN201100.00
CONT_ASSIGN201100.00
CONT_ASSIGN20411100.00
CONT_ASSIGN20411100.00
CONT_ASSIGN20411100.00
CONT_ASSIGN20411100.00
CONT_ASSIGN20411100.00
CONT_ASSIGN20411100.00
CONT_ASSIGN20411100.00
CONT_ASSIGN20411100.00
CONT_ASSIGN20411100.00
CONT_ASSIGN20411100.00
CONT_ASSIGN20411100.00
CONT_ASSIGN21111100.00
ALWAYS22100
ALWAYS22133100.00
ALWAYS22900
ALWAYS22933100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24011100.00
CONT_ASSIGN29111100.00
ALWAYS30733100.00
ALWAYS31833100.00
CONT_ASSIGN32900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_systems_sensor_ctrl_0.1/rtl/sensor_ctrl.sv' or '../src/lowrisc_systems_sensor_ctrl_0.1/rtl/sensor_ctrl.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
180 1 1
181 1 1
194 11 11
195 11 11
198 11 11
201 4 11
204 11 11
211 1 1
221 1 1
222 1 1
223 1 1
229 1 1
230 1 1
231 1 1
238 1 1
240 1 1
291 1 1
307 1 1
308 1 1
310 1 1
318 1 1
319 1 1
321 1 1
329 unreachable


Cond Coverage for Module : sensor_ctrl
TotalCoveredPercent
Conditions1189883.05
Logical1189883.05
Non-Logical00
Event00

 LINE       181
 EXPRESSION (alert_event_p[i] | ((~alert_event_n[i])))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT104,T87,T10
01Not Covered
10Not Covered

 LINE       194
 EXPRESSION (event_vld[0] & ((~reg2hw.fatal_alert_en[0])))
             ------1-----   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT109,T110,T298
11CoveredT10,T109,T110

 LINE       194
 EXPRESSION (event_vld[1] & ((~reg2hw.fatal_alert_en[1])))
             ------1-----   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT111,T112,T113

 LINE       194
 EXPRESSION (event_vld[2] & ((~reg2hw.fatal_alert_en[2])))
             ------1-----   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT104,T109,T110
11CoveredT104,T109,T110

 LINE       194
 EXPRESSION (event_vld[3] & ((~reg2hw.fatal_alert_en[3])))
             ------1-----   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT111,T112,T113

 LINE       194
 EXPRESSION (event_vld[4] & ((~reg2hw.fatal_alert_en[4])))
             ------1-----   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT109,T110,T298
11CoveredT109,T110,T111

 LINE       194
 EXPRESSION (event_vld[5] & ((~reg2hw.fatal_alert_en[5])))
             ------1-----   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT111,T112,T113

 LINE       194
 EXPRESSION (event_vld[6] & ((~reg2hw.fatal_alert_en[6])))
             ------1-----   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT104
11CoveredT104,T111,T112

 LINE       194
 EXPRESSION (event_vld[7] & ((~reg2hw.fatal_alert_en[7])))
             ------1-----   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT87,T89,T111

 LINE       194
 EXPRESSION (event_vld[8] & ((~reg2hw.fatal_alert_en[8])))
             ------1-----   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT87,T89,T111

 LINE       194
 EXPRESSION (event_vld[9] & ((~reg2hw.fatal_alert_en[9])))
             ------1-----   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT111,T112,T113

 LINE       194
 EXPRESSION (event_vld[10] & ((~reg2hw.fatal_alert_en[10])))
             ------1------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT111,T112,T113

 LINE       195
 EXPRESSION (event_vld[0] & reg2hw.fatal_alert_en[0])
             ------1-----   ------------2-----------
-1--2-StatusTests
01CoveredT109,T110,T298
10CoveredT10,T109,T110
11CoveredT109,T110,T298

 LINE       195
 EXPRESSION (event_vld[1] & reg2hw.fatal_alert_en[1])
             ------1-----   ------------2-----------
-1--2-StatusTests
01CoveredT228,T13
10CoveredT111,T112,T113
11Not Covered

 LINE       195
 EXPRESSION (event_vld[2] & reg2hw.fatal_alert_en[2])
             ------1-----   ------------2-----------
-1--2-StatusTests
01CoveredT104,T109,T110
10CoveredT104,T109,T110
11CoveredT104,T109,T110

 LINE       195
 EXPRESSION (event_vld[3] & reg2hw.fatal_alert_en[3])
             ------1-----   ------------2-----------
-1--2-StatusTests
01CoveredT13
10CoveredT111,T112,T113
11Not Covered

 LINE       195
 EXPRESSION (event_vld[4] & reg2hw.fatal_alert_en[4])
             ------1-----   ------------2-----------
-1--2-StatusTests
01CoveredT109,T110,T298
10CoveredT109,T110,T111
11CoveredT109,T110,T298

 LINE       195
 EXPRESSION (event_vld[5] & reg2hw.fatal_alert_en[5])
             ------1-----   ------------2-----------
-1--2-StatusTests
01CoveredT13
10CoveredT111,T112,T113
11Not Covered

 LINE       195
 EXPRESSION (event_vld[6] & reg2hw.fatal_alert_en[6])
             ------1-----   ------------2-----------
-1--2-StatusTests
01CoveredT104
10CoveredT104,T111,T112
11CoveredT104

 LINE       195
 EXPRESSION (event_vld[7] & reg2hw.fatal_alert_en[7])
             ------1-----   ------------2-----------
-1--2-StatusTests
01CoveredT13
10CoveredT87,T89,T111
11Not Covered

 LINE       195
 EXPRESSION (event_vld[8] & reg2hw.fatal_alert_en[8])
             ------1-----   ------------2-----------
-1--2-StatusTests
01CoveredT13
10CoveredT87,T89,T111
11Not Covered

 LINE       195
 EXPRESSION (event_vld[9] & reg2hw.fatal_alert_en[9])
             ------1-----   ------------2-----------
-1--2-StatusTests
01CoveredT13
10CoveredT111,T112,T113
11Not Covered

 LINE       195
 EXPRESSION (event_vld[10] & reg2hw.fatal_alert_en[10])
             ------1------   ------------2------------
-1--2-StatusTests
01CoveredT228,T13
10CoveredT111,T112,T113
11Not Covered

 LINE       204
 EXPRESSION (recov_event[0] & reg2hw.recov_alert[0].q)
             -------1------   -----------2-----------
-1--2-StatusTests
01CoveredT10,T109,T110
10CoveredT10,T109,T110
11CoveredT10,T109,T110

 LINE       204
 EXPRESSION (recov_event[1] & reg2hw.recov_alert[1].q)
             -------1------   -----------2-----------
-1--2-StatusTests
01CoveredT111,T112,T113
10CoveredT111,T112,T113
11CoveredT111,T112,T113

 LINE       204
 EXPRESSION (recov_event[2] & reg2hw.recov_alert[2].q)
             -------1------   -----------2-----------
-1--2-StatusTests
01CoveredT104,T109,T110
10CoveredT104,T109,T110
11CoveredT104,T109,T110

 LINE       204
 EXPRESSION (recov_event[3] & reg2hw.recov_alert[3].q)
             -------1------   -----------2-----------
-1--2-StatusTests
01CoveredT111,T112,T113
10CoveredT111,T112,T113
11CoveredT111,T112,T113

 LINE       204
 EXPRESSION (recov_event[4] & reg2hw.recov_alert[4].q)
             -------1------   -----------2-----------
-1--2-StatusTests
01CoveredT109,T110,T111
10CoveredT109,T110,T111
11CoveredT109,T110,T111

 LINE       204
 EXPRESSION (recov_event[5] & reg2hw.recov_alert[5].q)
             -------1------   -----------2-----------
-1--2-StatusTests
01CoveredT111,T112,T113
10CoveredT111,T112,T113
11CoveredT111,T112,T113

 LINE       204
 EXPRESSION (recov_event[6] & reg2hw.recov_alert[6].q)
             -------1------   -----------2-----------
-1--2-StatusTests
01CoveredT104,T111,T112
10CoveredT104,T111,T112
11CoveredT104,T111,T112

 LINE       204
 EXPRESSION (recov_event[7] & reg2hw.recov_alert[7].q)
             -------1------   -----------2-----------
-1--2-StatusTests
01CoveredT87,T89,T111
10CoveredT87,T89,T111
11CoveredT87,T89,T111

 LINE       204
 EXPRESSION (recov_event[8] & reg2hw.recov_alert[8].q)
             -------1------   -----------2-----------
-1--2-StatusTests
01CoveredT87,T89,T111
10CoveredT87,T89,T111
11CoveredT87,T89,T111

 LINE       204
 EXPRESSION (recov_event[9] & reg2hw.recov_alert[9].q)
             -------1------   -----------2-----------
-1--2-StatusTests
01CoveredT111,T112,T113
10CoveredT111,T112,T113
11CoveredT111,T112,T113

 LINE       204
 EXPRESSION (recov_event[10] & reg2hw.recov_alert[10].q)
             -------1-------   ------------2-----------
-1--2-StatusTests
01CoveredT111,T112,T113
10CoveredT111,T112,T113
11CoveredT111,T112,T113

 LINE       222
 EXPRESSION (alert_event_p[i] & event_clr[i])
             --------1-------   ------2-----
-1--2-StatusTests
01Not Covered
10CoveredT104,T87,T10
11CoveredT104,T87,T10

 LINE       223
 SUB-EXPRESSION (((~alert_event_n[i])) & event_clr[i])
                 ----------1----------   ------2-----
-1--2-StatusTests
01Not Covered
10CoveredT104,T87,T10
11CoveredT104,T87,T10

 LINE       238
 EXPRESSION (reg2hw.alert_test.recov_alert.qe & reg2hw.alert_test.recov_alert.q)
             ----------------1---------------   ---------------2---------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT23,T24,T25
11CoveredT23,T24,T228

 LINE       240
 EXPRESSION (reg2hw.alert_test.fatal_alert.qe & reg2hw.alert_test.fatal_alert.q)
             ----------------1---------------   ---------------2---------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT23,T24,T228
11CoveredT23,T24,T25

 LINE       291
 EXPRESSION (((|async_alert_event_p)) | ((~&async_alert_event_n)) | ((|reg2hw.recov_alert)))
             ------------1-----------   ------------2------------   -----------3-----------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT104,T87,T10
010Not Covered
100Not Covered

Toggle Coverage for Module : sensor_ctrl
TotalCoveredPercent
Totals 108 100 92.59
Total Bits 454 424 93.39
Total Bits 0->1 227 212 93.39
Total Bits 1->0 227 212 93.39

Ports 108 100 92.59
Port Bits 454 424 93.39
Port Bits 0->1 227 212 93.39
Port Bits 1->0 227 212 93.39

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
clk_aon_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_aon_ni Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T19,T20,T21 Yes T19,T20,T21 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[2:1] No No No INPUT
tl_i.a_user.instr_type[3] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T19,T20,T21 Yes T19,T20,T21 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[1:0] No No No INPUT
tl_i.a_address[5:2] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[15:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[16] Yes Yes *T19,*T20,*T21 Yes T19,T20,T21 INPUT
tl_i.a_address[18:17] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[19] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[21:20] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[22] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[29:23] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T45,*T46,*T47 Yes T45,T46,T47 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_opcode[1] No No No INPUT
tl_i.a_opcode[2] Yes Yes T19,T20,T21 Yes T19,T20,T21 INPUT
tl_i.a_valid Yes Yes T19,T20,T21 Yes T19,T20,T21 INPUT
tl_o.a_ready Yes Yes T19,T20,T21 Yes T19,T20,T21 OUTPUT
tl_o.d_error No No No OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T104,T129,T87 Yes T104,T129,T87 OUTPUT
tl_o.d_user.rsp_intg[1:0] Yes Yes T104,T129,T87 Yes T104,T129,T87 OUTPUT
tl_o.d_user.rsp_intg[3:2] No No No OUTPUT
tl_o.d_user.rsp_intg[5:4] Yes Yes T19,T20,T104 Yes T19,T20,T21 OUTPUT
tl_o.d_user.rsp_intg[6] No No No OUTPUT
tl_o.d_data[31:0] Yes Yes T19,T20,T104 Yes T19,T20,T21 OUTPUT
tl_o.d_sink No No No OUTPUT
tl_o.d_source[1:0] Yes Yes *T228,*T13,*T19 Yes T228,T13,T19 OUTPUT
tl_o.d_source[5:2] No No No OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[0] No No No OUTPUT
tl_o.d_size[1] Yes Yes T19,T20,T104 Yes T19,T20,T21 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T19,*T20,*T104 Yes T19,T20,T21 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T19,T20,T21 Yes T19,T20,T21 OUTPUT
ast_alert_i.alerts[0].n Yes Yes T10,T109,T110 Yes T10,T109,T110 INPUT
ast_alert_i.alerts[0].p Yes Yes T10,T109,T110 Yes T10,T109,T110 INPUT
ast_alert_i.alerts[1].n Yes Yes T111,T112,T113 Yes T111,T112,T113 INPUT
ast_alert_i.alerts[1].p Yes Yes T111,T112,T113 Yes T111,T112,T113 INPUT
ast_alert_i.alerts[2].n Yes Yes T104,T109,T110 Yes T104,T109,T110 INPUT
ast_alert_i.alerts[2].p Yes Yes T104,T109,T110 Yes T104,T109,T110 INPUT
ast_alert_i.alerts[3].n Yes Yes T111,T112,T113 Yes T111,T112,T113 INPUT
ast_alert_i.alerts[3].p Yes Yes T111,T112,T113 Yes T111,T112,T113 INPUT
ast_alert_i.alerts[4].n Yes Yes T109,T110,T111 Yes T109,T110,T111 INPUT
ast_alert_i.alerts[4].p Yes Yes T109,T110,T111 Yes T109,T110,T111 INPUT
ast_alert_i.alerts[5].n Yes Yes T111,T112,T113 Yes T111,T112,T113 INPUT
ast_alert_i.alerts[5].p Yes Yes T111,T112,T113 Yes T111,T112,T113 INPUT
ast_alert_i.alerts[6].n Yes Yes T104,T111,T112 Yes T104,T111,T112 INPUT
ast_alert_i.alerts[6].p Yes Yes T104,T111,T112 Yes T104,T111,T112 INPUT
ast_alert_i.alerts[7].n Yes Yes T87,T89,T111 Yes T87,T89,T111 INPUT
ast_alert_i.alerts[7].p Yes Yes T87,T89,T111 Yes T87,T89,T111 INPUT
ast_alert_i.alerts[8].n Yes Yes T87,T89,T111 Yes T87,T89,T111 INPUT
ast_alert_i.alerts[8].p Yes Yes T87,T89,T111 Yes T87,T89,T111 INPUT
ast_alert_i.alerts[9].n Yes Yes T111,T112,T113 Yes T111,T112,T113 INPUT
ast_alert_i.alerts[9].p Yes Yes T111,T112,T113 Yes T111,T112,T113 INPUT
ast_alert_i.alerts[10].n Yes Yes T111,T112,T113 Yes T111,T112,T113 INPUT
ast_alert_i.alerts[10].p Yes Yes T111,T112,T113 Yes T111,T112,T113 INPUT
ast_alert_o.alerts_trig[0].n Yes Yes T10,T109,T110 Yes T10,T109,T110 OUTPUT
ast_alert_o.alerts_trig[0].p Yes Yes T10,T109,T110 Yes T10,T109,T110 OUTPUT
ast_alert_o.alerts_trig[1].n Yes Yes T111,T112,T113 Yes T111,T112,T113 OUTPUT
ast_alert_o.alerts_trig[1].p Yes Yes T111,T112,T113 Yes T111,T112,T113 OUTPUT
ast_alert_o.alerts_trig[2].n Yes Yes T104,T109,T110 Yes T104,T109,T110 OUTPUT
ast_alert_o.alerts_trig[2].p Yes Yes T104,T109,T110 Yes T104,T109,T110 OUTPUT
ast_alert_o.alerts_trig[3].n Yes Yes T111,T112,T113 Yes T111,T112,T113 OUTPUT
ast_alert_o.alerts_trig[3].p Yes Yes T111,T112,T113 Yes T111,T112,T113 OUTPUT
ast_alert_o.alerts_trig[4].n Yes Yes T109,T110,T111 Yes T109,T110,T111 OUTPUT
ast_alert_o.alerts_trig[4].p Yes Yes T109,T110,T111 Yes T109,T110,T111 OUTPUT
ast_alert_o.alerts_trig[5].n Yes Yes T111,T112,T113 Yes T111,T112,T113 OUTPUT
ast_alert_o.alerts_trig[5].p Yes Yes T111,T112,T113 Yes T111,T112,T113 OUTPUT
ast_alert_o.alerts_trig[6].n Yes Yes T104,T111,T112 Yes T104,T111,T112 OUTPUT
ast_alert_o.alerts_trig[6].p Yes Yes T104,T111,T112 Yes T104,T111,T112 OUTPUT
ast_alert_o.alerts_trig[7].n Yes Yes T87,T89,T111 Yes T87,T89,T111 OUTPUT
ast_alert_o.alerts_trig[7].p Yes Yes T87,T89,T111 Yes T87,T89,T111 OUTPUT
ast_alert_o.alerts_trig[8].n Yes Yes T87,T89,T111 Yes T87,T89,T111 OUTPUT
ast_alert_o.alerts_trig[8].p Yes Yes T87,T89,T111 Yes T87,T89,T111 OUTPUT
ast_alert_o.alerts_trig[9].n Yes Yes T111,T112,T113 Yes T111,T112,T113 OUTPUT
ast_alert_o.alerts_trig[9].p Yes Yes T111,T112,T113 Yes T111,T112,T113 OUTPUT
ast_alert_o.alerts_trig[10].n Yes Yes T111,T112,T113 Yes T111,T112,T113 OUTPUT
ast_alert_o.alerts_trig[10].p Yes Yes T111,T112,T113 Yes T111,T112,T113 OUTPUT
ast_alert_o.alerts_ack[0].n Yes Yes T10,T109,T110 Yes T10,T109,T110 OUTPUT
ast_alert_o.alerts_ack[0].p Yes Yes T10,T109,T110 Yes T10,T109,T110 OUTPUT
ast_alert_o.alerts_ack[1].n Yes Yes T111,T112,T113 Yes T111,T112,T113 OUTPUT
ast_alert_o.alerts_ack[1].p Yes Yes T111,T112,T113 Yes T111,T112,T113 OUTPUT
ast_alert_o.alerts_ack[2].n Yes Yes T104,T109,T110 Yes T104,T109,T110 OUTPUT
ast_alert_o.alerts_ack[2].p Yes Yes T104,T109,T110 Yes T104,T109,T110 OUTPUT
ast_alert_o.alerts_ack[3].n Yes Yes T111,T112,T113 Yes T111,T112,T113 OUTPUT
ast_alert_o.alerts_ack[3].p Yes Yes T111,T112,T113 Yes T111,T112,T113 OUTPUT
ast_alert_o.alerts_ack[4].n Yes Yes T109,T110,T111 Yes T109,T110,T111 OUTPUT
ast_alert_o.alerts_ack[4].p Yes Yes T109,T110,T111 Yes T109,T110,T111 OUTPUT
ast_alert_o.alerts_ack[5].n Yes Yes T111,T112,T113 Yes T111,T112,T113 OUTPUT
ast_alert_o.alerts_ack[5].p Yes Yes T111,T112,T113 Yes T111,T112,T113 OUTPUT
ast_alert_o.alerts_ack[6].n Yes Yes T104,T111,T112 Yes T104,T111,T112 OUTPUT
ast_alert_o.alerts_ack[6].p Yes Yes T104,T111,T112 Yes T104,T111,T112 OUTPUT
ast_alert_o.alerts_ack[7].n Yes Yes T87,T89,T111 Yes T87,T89,T111 OUTPUT
ast_alert_o.alerts_ack[7].p Yes Yes T87,T89,T111 Yes T87,T89,T111 OUTPUT
ast_alert_o.alerts_ack[8].n Yes Yes T87,T89,T111 Yes T87,T89,T111 OUTPUT
ast_alert_o.alerts_ack[8].p Yes Yes T87,T89,T111 Yes T87,T89,T111 OUTPUT
ast_alert_o.alerts_ack[9].n Yes Yes T111,T112,T113 Yes T111,T112,T113 OUTPUT
ast_alert_o.alerts_ack[9].p Yes Yes T111,T112,T113 Yes T111,T112,T113 OUTPUT
ast_alert_o.alerts_ack[10].n Yes Yes T111,T112,T113 Yes T111,T112,T113 OUTPUT
ast_alert_o.alerts_ack[10].p Yes Yes T111,T112,T113 Yes T111,T112,T113 OUTPUT
ast_status_i.io_pok[1:0] Yes Yes T108,T114,T115 Yes T1,T2,T3 INPUT
ast2pinmux_i[8:0] Unreachable Unreachable Unreachable INPUT
ast_init_done_i[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
cio_ast_debug_out_o[8:0] Unreachable Unreachable Unreachable OUTPUT
cio_ast_debug_out_en_o[8:0] Unreachable Unreachable Unreachable OUTPUT
intr_io_status_change_o Yes Yes T129,T115,T131 Yes T129,T115,T131 OUTPUT
intr_init_status_change_o Yes Yes T129,T131,T228 Yes T129,T131,T228 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T104,T87,T10 Yes T104,T87,T10 INPUT
alert_rx_i[0].ping_n Yes Yes T60,T62,T143 Yes T60,T62,T143 INPUT
alert_rx_i[0].ping_p Yes Yes T60,T62,T143 Yes T60,T62,T143 INPUT
alert_rx_i[1].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[1].ack_p Yes Yes T104,T109,T110 Yes T104,T109,T110 INPUT
alert_rx_i[1].ping_n Yes Yes T60,T62,T143 Yes T60,T62,T143 INPUT
alert_rx_i[1].ping_p Yes Yes T60,T62,T143 Yes T60,T62,T143 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T104,T87,T10 Yes T104,T87,T10 OUTPUT
alert_tx_o[1].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[1].alert_p Yes Yes T104,T109,T110 Yes T104,T109,T110 OUTPUT
wkup_req_o Yes Yes T104,T87,T10 Yes T104,T87,T10 OUTPUT

*Tests covering at least one bit in the range

Branch Coverage for Module : sensor_ctrl
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 307 2 2 100.00
IF 318 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_systems_sensor_ctrl_0.1/rtl/sensor_ctrl.sv' or '../src/lowrisc_systems_sensor_ctrl_0.1/rtl/sensor_ctrl.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 307 if ((!rst_aon_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 318 if ((!rst_aon_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : sensor_ctrl
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
FpvSecCmRegWeOnehotCheck_A 99909715 2 0 0
NumAlertsMatch_A 962 962 0 0


FpvSecCmRegWeOnehotCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 99909715 2 0 0
T223 64351 0 0 0
T299 35936 1 0 0
T300 0 1 0 0
T301 64158 0 0 0
T302 169080 0 0 0
T303 32907 0 0 0
T304 115537 0 0 0
T305 56249 0 0 0
T306 209066 0 0 0
T307 284570 0 0 0
T308 45299 0 0 0

NumAlertsMatch_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 962 962 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T63 1 1 0 0
T64 1 1 0 0
T65 1 1 0 0
T66 1 1 0 0
T67 1 1 0 0
T68 1 1 0 0
T69 1 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%