Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.88 100.00 86.67 100.00 92.86


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.88 100.00 86.67 100.00 92.86


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_ibus_trans


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.55 100.00 93.33 100.00 92.86


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.55 100.00 93.33 100.00 92.86


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_dbus_trans


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_arbiter_fixed
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN8911100.00
ALWAYS10566100.00
CONT_ASSIGN12111100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN12911100.00
CONT_ASSIGN13211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
85 2 2
87 2 2
89 2 2
105 1 1
107 1 1
109 1 1
110 1 1
112 1 1
113 1 1
121 1 1
128 1 1
129 1 1
132 1 1


Cond Coverage for Module : prim_arbiter_fixed
TotalCoveredPercent
Conditions151493.33
Logical151493.33
Non-Logical00
Event00

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT235,T236,T13
01CoveredT235,T236,T238
10CoveredT13

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT235,T236,T13
1CoveredT235,T236,T13

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT235,T236,T13
1CoveredT235,T236,T13

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01Not Covered
10CoveredT235,T236,T238
11CoveredT235,T236,T13

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01CoveredT235,T236,T13
10CoveredT235,T236,T13
11CoveredT235,T236,T238

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11CoveredT235,T236,T13

Branch Coverage for Module : prim_arbiter_fixed
Line No.TotalCoveredPercent
Branches 4 4 100.00
TERNARY 109 2 2 100.00
TERNARY 110 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 109 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T235,T236,T13
0 Covered T235,T236,T13


LineNo. Expression -1-: 110 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T235,T236,T13
0 Covered T235,T236,T13


Assert Coverage for Module : prim_arbiter_fixed
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 14 14 100.00 13 92.86
Cover properties 0 0 0
Cover sequences 0 0 0
Total 14 14 100.00 13 92.86




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckHotOne_A 803803682 786596090 0 0
CheckNGreaterZero_A 1924 1924 0 0
GntImpliesReady_A 803803682 5339 0 0
GntImpliesValid_A 803803682 5339 0 0
GrantKnown_A 803803682 786596090 0 0
IdxKnown_A 803803682 786596090 0 0
IndexIsCorrect_A 803803682 5339 0 0
NoReadyValidNoGrant_A 803803682 0 0 0
Priority_A 803803682 5339 0 0
ReadyAndValidImplyGrant_A 803803682 5339 0 0
ReqAndReadyImplyGrant_A 803803682 5339 0 0
ReqImpliesValid_A 803803682 5339 0 0
ValidKnown_A 803803682 786596090 0 0
gen_data_port_assertion.DataFlow_A 803803682 5339 0 0


CheckHotOne_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 803803682 786596090 0 0
T19 733742 733180 0 0
T20 1394750 1394728 0 0
T21 396364 396248 0 0
T22 423364 423354 0 0
T38 499656 499436 0 0
T90 909344 909112 0 0
T104 501548 501242 0 0
T106 467724 467614 0 0
T136 426478 426466 0 0
T137 150442 150318 0 0

CheckNGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1924 1924 0 0
T1 2 2 0 0
T2 2 2 0 0
T3 2 2 0 0
T63 2 2 0 0
T64 2 2 0 0
T65 2 2 0 0
T66 2 2 0 0
T67 2 2 0 0
T68 2 2 0 0
T69 2 2 0 0

GntImpliesReady_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 803803682 5339 0 0
T148 561216 0 0 0
T235 180276 1777 0 0
T236 0 1786 0 0
T238 0 1776 0 0
T244 574164 0 0 0
T310 1996392 0 0 0
T322 730986 0 0 0
T323 435356 0 0 0
T324 271410 0 0 0
T325 175252 0 0 0
T326 154070 0 0 0
T327 1206176 0 0 0

GntImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 803803682 5339 0 0
T148 561216 0 0 0
T235 180276 1777 0 0
T236 0 1786 0 0
T238 0 1776 0 0
T244 574164 0 0 0
T310 1996392 0 0 0
T322 730986 0 0 0
T323 435356 0 0 0
T324 271410 0 0 0
T325 175252 0 0 0
T326 154070 0 0 0
T327 1206176 0 0 0

GrantKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 803803682 786596090 0 0
T19 733742 733180 0 0
T20 1394750 1394728 0 0
T21 396364 396248 0 0
T22 423364 423354 0 0
T38 499656 499436 0 0
T90 909344 909112 0 0
T104 501548 501242 0 0
T106 467724 467614 0 0
T136 426478 426466 0 0
T137 150442 150318 0 0

IdxKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 803803682 786596090 0 0
T19 733742 733180 0 0
T20 1394750 1394728 0 0
T21 396364 396248 0 0
T22 423364 423354 0 0
T38 499656 499436 0 0
T90 909344 909112 0 0
T104 501548 501242 0 0
T106 467724 467614 0 0
T136 426478 426466 0 0
T137 150442 150318 0 0

IndexIsCorrect_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 803803682 5339 0 0
T148 561216 0 0 0
T235 180276 1777 0 0
T236 0 1786 0 0
T238 0 1776 0 0
T244 574164 0 0 0
T310 1996392 0 0 0
T322 730986 0 0 0
T323 435356 0 0 0
T324 271410 0 0 0
T325 175252 0 0 0
T326 154070 0 0 0
T327 1206176 0 0 0

NoReadyValidNoGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 803803682 0 0 0

Priority_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 803803682 5339 0 0
T148 561216 0 0 0
T235 180276 1777 0 0
T236 0 1786 0 0
T238 0 1776 0 0
T244 574164 0 0 0
T310 1996392 0 0 0
T322 730986 0 0 0
T323 435356 0 0 0
T324 271410 0 0 0
T325 175252 0 0 0
T326 154070 0 0 0
T327 1206176 0 0 0

ReadyAndValidImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 803803682 5339 0 0
T148 561216 0 0 0
T235 180276 1777 0 0
T236 0 1786 0 0
T238 0 1776 0 0
T244 574164 0 0 0
T310 1996392 0 0 0
T322 730986 0 0 0
T323 435356 0 0 0
T324 271410 0 0 0
T325 175252 0 0 0
T326 154070 0 0 0
T327 1206176 0 0 0

ReqAndReadyImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 803803682 5339 0 0
T148 561216 0 0 0
T235 180276 1777 0 0
T236 0 1786 0 0
T238 0 1776 0 0
T244 574164 0 0 0
T310 1996392 0 0 0
T322 730986 0 0 0
T323 435356 0 0 0
T324 271410 0 0 0
T325 175252 0 0 0
T326 154070 0 0 0
T327 1206176 0 0 0

ReqImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 803803682 5339 0 0
T148 561216 0 0 0
T235 180276 1777 0 0
T236 0 1786 0 0
T238 0 1776 0 0
T244 574164 0 0 0
T310 1996392 0 0 0
T322 730986 0 0 0
T323 435356 0 0 0
T324 271410 0 0 0
T325 175252 0 0 0
T326 154070 0 0 0
T327 1206176 0 0 0

ValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 803803682 786596090 0 0
T19 733742 733180 0 0
T20 1394750 1394728 0 0
T21 396364 396248 0 0
T22 423364 423354 0 0
T38 499656 499436 0 0
T90 909344 909112 0 0
T104 501548 501242 0 0
T106 467724 467614 0 0
T136 426478 426466 0 0
T137 150442 150318 0 0

gen_data_port_assertion.DataFlow_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 803803682 5339 0 0
T148 561216 0 0 0
T235 180276 1777 0 0
T236 0 1786 0 0
T238 0 1776 0 0
T244 574164 0 0 0
T310 1996392 0 0 0
T322 730986 0 0 0
T323 435356 0 0 0
T324 271410 0 0 0
T325 175252 0 0 0
T326 154070 0 0 0
T327 1206176 0 0 0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN8911100.00
ALWAYS10566100.00
CONT_ASSIGN12111100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN12911100.00
CONT_ASSIGN13211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
85 2 2
87 2 2
89 2 2
105 1 1
107 1 1
109 1 1
110 1 1
112 1 1
113 1 1
121 1 1
128 1 1
129 1 1
132 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region
TotalCoveredPercent
Conditions151386.67
Logical151386.67
Non-Logical00
Event00

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT235,T236,T13
01CoveredT235,T236,T238
10Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT235,T236,T238
1CoveredT235,T236,T13

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT235,T236,T238
1CoveredT235,T236,T13

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01Not Covered
10CoveredT235,T236,T238
11CoveredT235,T236,T238

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01CoveredT235,T236,T13
10CoveredT235,T236,T238
11CoveredT235,T236,T238

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11CoveredT235,T236,T238

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region
Line No.TotalCoveredPercent
Branches 4 4 100.00
TERNARY 109 2 2 100.00
TERNARY 110 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 109 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T235,T236,T13
0 Covered T235,T236,T238


LineNo. Expression -1-: 110 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T235,T236,T13
0 Covered T235,T236,T238


Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 14 14 100.00 13 92.86
Cover properties 0 0 0
Cover sequences 0 0 0
Total 14 14 100.00 13 92.86




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckHotOne_A 401901841 393298045 0 0
CheckNGreaterZero_A 962 962 0 0
GntImpliesReady_A 401901841 4307 0 0
GntImpliesValid_A 401901841 4307 0 0
GrantKnown_A 401901841 393298045 0 0
IdxKnown_A 401901841 393298045 0 0
IndexIsCorrect_A 401901841 4307 0 0
NoReadyValidNoGrant_A 401901841 0 0 0
Priority_A 401901841 4307 0 0
ReadyAndValidImplyGrant_A 401901841 4307 0 0
ReqAndReadyImplyGrant_A 401901841 4307 0 0
ReqImpliesValid_A 401901841 4307 0 0
ValidKnown_A 401901841 393298045 0 0
gen_data_port_assertion.DataFlow_A 401901841 4307 0 0


CheckHotOne_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 401901841 393298045 0 0
T19 366871 366590 0 0
T20 697375 697364 0 0
T21 198182 198124 0 0
T22 211682 211677 0 0
T38 249828 249718 0 0
T90 454672 454556 0 0
T104 250774 250621 0 0
T106 233862 233807 0 0
T136 213239 213233 0 0
T137 75221 75159 0 0

CheckNGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 962 962 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T63 1 1 0 0
T64 1 1 0 0
T65 1 1 0 0
T66 1 1 0 0
T67 1 1 0 0
T68 1 1 0 0
T69 1 1 0 0

GntImpliesReady_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 401901841 4307 0 0
T148 280608 0 0 0
T235 90138 1433 0 0
T236 0 1442 0 0
T238 0 1432 0 0
T244 287082 0 0 0
T310 998196 0 0 0
T322 365493 0 0 0
T323 217678 0 0 0
T324 135705 0 0 0
T325 87626 0 0 0
T326 77035 0 0 0
T327 603088 0 0 0

GntImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 401901841 4307 0 0
T148 280608 0 0 0
T235 90138 1433 0 0
T236 0 1442 0 0
T238 0 1432 0 0
T244 287082 0 0 0
T310 998196 0 0 0
T322 365493 0 0 0
T323 217678 0 0 0
T324 135705 0 0 0
T325 87626 0 0 0
T326 77035 0 0 0
T327 603088 0 0 0

GrantKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 401901841 393298045 0 0
T19 366871 366590 0 0
T20 697375 697364 0 0
T21 198182 198124 0 0
T22 211682 211677 0 0
T38 249828 249718 0 0
T90 454672 454556 0 0
T104 250774 250621 0 0
T106 233862 233807 0 0
T136 213239 213233 0 0
T137 75221 75159 0 0

IdxKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 401901841 393298045 0 0
T19 366871 366590 0 0
T20 697375 697364 0 0
T21 198182 198124 0 0
T22 211682 211677 0 0
T38 249828 249718 0 0
T90 454672 454556 0 0
T104 250774 250621 0 0
T106 233862 233807 0 0
T136 213239 213233 0 0
T137 75221 75159 0 0

IndexIsCorrect_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 401901841 4307 0 0
T148 280608 0 0 0
T235 90138 1433 0 0
T236 0 1442 0 0
T238 0 1432 0 0
T244 287082 0 0 0
T310 998196 0 0 0
T322 365493 0 0 0
T323 217678 0 0 0
T324 135705 0 0 0
T325 87626 0 0 0
T326 77035 0 0 0
T327 603088 0 0 0

NoReadyValidNoGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 401901841 0 0 0

Priority_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 401901841 4307 0 0
T148 280608 0 0 0
T235 90138 1433 0 0
T236 0 1442 0 0
T238 0 1432 0 0
T244 287082 0 0 0
T310 998196 0 0 0
T322 365493 0 0 0
T323 217678 0 0 0
T324 135705 0 0 0
T325 87626 0 0 0
T326 77035 0 0 0
T327 603088 0 0 0

ReadyAndValidImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 401901841 4307 0 0
T148 280608 0 0 0
T235 90138 1433 0 0
T236 0 1442 0 0
T238 0 1432 0 0
T244 287082 0 0 0
T310 998196 0 0 0
T322 365493 0 0 0
T323 217678 0 0 0
T324 135705 0 0 0
T325 87626 0 0 0
T326 77035 0 0 0
T327 603088 0 0 0

ReqAndReadyImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 401901841 4307 0 0
T148 280608 0 0 0
T235 90138 1433 0 0
T236 0 1442 0 0
T238 0 1432 0 0
T244 287082 0 0 0
T310 998196 0 0 0
T322 365493 0 0 0
T323 217678 0 0 0
T324 135705 0 0 0
T325 87626 0 0 0
T326 77035 0 0 0
T327 603088 0 0 0

ReqImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 401901841 4307 0 0
T148 280608 0 0 0
T235 90138 1433 0 0
T236 0 1442 0 0
T238 0 1432 0 0
T244 287082 0 0 0
T310 998196 0 0 0
T322 365493 0 0 0
T323 217678 0 0 0
T324 135705 0 0 0
T325 87626 0 0 0
T326 77035 0 0 0
T327 603088 0 0 0

ValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 401901841 393298045 0 0
T19 366871 366590 0 0
T20 697375 697364 0 0
T21 198182 198124 0 0
T22 211682 211677 0 0
T38 249828 249718 0 0
T90 454672 454556 0 0
T104 250774 250621 0 0
T106 233862 233807 0 0
T136 213239 213233 0 0
T137 75221 75159 0 0

gen_data_port_assertion.DataFlow_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 401901841 4307 0 0
T148 280608 0 0 0
T235 90138 1433 0 0
T236 0 1442 0 0
T238 0 1432 0 0
T244 287082 0 0 0
T310 998196 0 0 0
T322 365493 0 0 0
T323 217678 0 0 0
T324 135705 0 0 0
T325 87626 0 0 0
T326 77035 0 0 0
T327 603088 0 0 0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN8911100.00
ALWAYS10566100.00
CONT_ASSIGN12111100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN12911100.00
CONT_ASSIGN13211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
85 2 2
87 2 2
89 2 2
105 1 1
107 1 1
109 1 1
110 1 1
112 1 1
113 1 1
121 1 1
128 1 1
129 1 1
132 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region
TotalCoveredPercent
Conditions151493.33
Logical151493.33
Non-Logical00
Event00

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT235,T236,T13
01CoveredT235,T236,T238
10CoveredT13

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT235,T236,T13
1CoveredT235,T236,T13

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT235,T236,T13
1CoveredT235,T236,T13

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01Not Covered
10CoveredT235,T236,T238
11CoveredT235,T236,T13

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01CoveredT235,T236,T13
10CoveredT235,T236,T13
11CoveredT235,T236,T238

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11CoveredT235,T236,T13

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region
Line No.TotalCoveredPercent
Branches 4 4 100.00
TERNARY 109 2 2 100.00
TERNARY 110 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 109 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T235,T236,T13
0 Covered T235,T236,T13


LineNo. Expression -1-: 110 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T235,T236,T13
0 Covered T235,T236,T13


Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 14 14 100.00 13 92.86
Cover properties 0 0 0
Cover sequences 0 0 0
Total 14 14 100.00 13 92.86




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckHotOne_A 401901841 393298045 0 0
CheckNGreaterZero_A 962 962 0 0
GntImpliesReady_A 401901841 1032 0 0
GntImpliesValid_A 401901841 1032 0 0
GrantKnown_A 401901841 393298045 0 0
IdxKnown_A 401901841 393298045 0 0
IndexIsCorrect_A 401901841 1032 0 0
NoReadyValidNoGrant_A 401901841 0 0 0
Priority_A 401901841 1032 0 0
ReadyAndValidImplyGrant_A 401901841 1032 0 0
ReqAndReadyImplyGrant_A 401901841 1032 0 0
ReqImpliesValid_A 401901841 1032 0 0
ValidKnown_A 401901841 393298045 0 0
gen_data_port_assertion.DataFlow_A 401901841 1032 0 0


CheckHotOne_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 401901841 393298045 0 0
T19 366871 366590 0 0
T20 697375 697364 0 0
T21 198182 198124 0 0
T22 211682 211677 0 0
T38 249828 249718 0 0
T90 454672 454556 0 0
T104 250774 250621 0 0
T106 233862 233807 0 0
T136 213239 213233 0 0
T137 75221 75159 0 0

CheckNGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 962 962 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T63 1 1 0 0
T64 1 1 0 0
T65 1 1 0 0
T66 1 1 0 0
T67 1 1 0 0
T68 1 1 0 0
T69 1 1 0 0

GntImpliesReady_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 401901841 1032 0 0
T148 280608 0 0 0
T235 90138 344 0 0
T236 0 344 0 0
T238 0 344 0 0
T244 287082 0 0 0
T310 998196 0 0 0
T322 365493 0 0 0
T323 217678 0 0 0
T324 135705 0 0 0
T325 87626 0 0 0
T326 77035 0 0 0
T327 603088 0 0 0

GntImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 401901841 1032 0 0
T148 280608 0 0 0
T235 90138 344 0 0
T236 0 344 0 0
T238 0 344 0 0
T244 287082 0 0 0
T310 998196 0 0 0
T322 365493 0 0 0
T323 217678 0 0 0
T324 135705 0 0 0
T325 87626 0 0 0
T326 77035 0 0 0
T327 603088 0 0 0

GrantKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 401901841 393298045 0 0
T19 366871 366590 0 0
T20 697375 697364 0 0
T21 198182 198124 0 0
T22 211682 211677 0 0
T38 249828 249718 0 0
T90 454672 454556 0 0
T104 250774 250621 0 0
T106 233862 233807 0 0
T136 213239 213233 0 0
T137 75221 75159 0 0

IdxKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 401901841 393298045 0 0
T19 366871 366590 0 0
T20 697375 697364 0 0
T21 198182 198124 0 0
T22 211682 211677 0 0
T38 249828 249718 0 0
T90 454672 454556 0 0
T104 250774 250621 0 0
T106 233862 233807 0 0
T136 213239 213233 0 0
T137 75221 75159 0 0

IndexIsCorrect_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 401901841 1032 0 0
T148 280608 0 0 0
T235 90138 344 0 0
T236 0 344 0 0
T238 0 344 0 0
T244 287082 0 0 0
T310 998196 0 0 0
T322 365493 0 0 0
T323 217678 0 0 0
T324 135705 0 0 0
T325 87626 0 0 0
T326 77035 0 0 0
T327 603088 0 0 0

NoReadyValidNoGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 401901841 0 0 0

Priority_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 401901841 1032 0 0
T148 280608 0 0 0
T235 90138 344 0 0
T236 0 344 0 0
T238 0 344 0 0
T244 287082 0 0 0
T310 998196 0 0 0
T322 365493 0 0 0
T323 217678 0 0 0
T324 135705 0 0 0
T325 87626 0 0 0
T326 77035 0 0 0
T327 603088 0 0 0

ReadyAndValidImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 401901841 1032 0 0
T148 280608 0 0 0
T235 90138 344 0 0
T236 0 344 0 0
T238 0 344 0 0
T244 287082 0 0 0
T310 998196 0 0 0
T322 365493 0 0 0
T323 217678 0 0 0
T324 135705 0 0 0
T325 87626 0 0 0
T326 77035 0 0 0
T327 603088 0 0 0

ReqAndReadyImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 401901841 1032 0 0
T148 280608 0 0 0
T235 90138 344 0 0
T236 0 344 0 0
T238 0 344 0 0
T244 287082 0 0 0
T310 998196 0 0 0
T322 365493 0 0 0
T323 217678 0 0 0
T324 135705 0 0 0
T325 87626 0 0 0
T326 77035 0 0 0
T327 603088 0 0 0

ReqImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 401901841 1032 0 0
T148 280608 0 0 0
T235 90138 344 0 0
T236 0 344 0 0
T238 0 344 0 0
T244 287082 0 0 0
T310 998196 0 0 0
T322 365493 0 0 0
T323 217678 0 0 0
T324 135705 0 0 0
T325 87626 0 0 0
T326 77035 0 0 0
T327 603088 0 0 0

ValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 401901841 393298045 0 0
T19 366871 366590 0 0
T20 697375 697364 0 0
T21 198182 198124 0 0
T22 211682 211677 0 0
T38 249828 249718 0 0
T90 454672 454556 0 0
T104 250774 250621 0 0
T106 233862 233807 0 0
T136 213239 213233 0 0
T137 75221 75159 0 0

gen_data_port_assertion.DataFlow_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 401901841 1032 0 0
T148 280608 0 0 0
T235 90138 344 0 0
T236 0 344 0 0
T238 0 344 0 0
T244 287082 0 0 0
T310 998196 0 0 0
T322 365493 0 0 0
T323 217678 0 0 0
T324 135705 0 0 0
T325 87626 0 0 0
T326 77035 0 0 0
T327 603088 0 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%