Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1708036	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

26754465

1

T1

9727

T2

8176

T3

16685

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	18374769	1			T1	4621		T2	3865		T3	8195
values[0x0]	8378770	1			T1	5106		T2	4311		T3	8490
values[0x1]	1708962	1			T1	387		T2	464		T3	637

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	9487	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

28453014

1

T1

10114

T2

8640

T3

17322

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	14216695	1			T1	5057		T2	4320		T3	8661
valid_sources[0x01]	14215931	1			T1	5057		T2	4320		T3	8661
valid_sources[0x02]	346	1			T10	32		T12	69		T19	42
valid_sources[0x03]	281	1			T12	33		T19	48		T20	38
valid_sources[0x04]	328	1			T12	59		T19	53		T20	54
valid_sources[0x05]	296	1			T12	52		T19	46		T20	54
valid_sources[0x06]	290	1			T12	55		T19	38		T20	58
valid_sources[0x07]	332	1			T12	57		T19	41		T20	77
valid_sources[0x08]	3053	1			T12	70		T19	33		T20	59
valid_sources[0x09]	324	1			T12	27		T19	90		T20	52
valid_sources[0x0a]	285	1			T12	48		T19	45		T20	63
valid_sources[0x0b]	314	1			T12	44		T19	51		T20	53
valid_sources[0x0c]	372	1			T10	94		T12	46		T19	40
valid_sources[0x0d]	304	1			T10	16		T12	69		T19	37
valid_sources[0x0e]	351	1			T12	71		T19	54		T20	78
valid_sources[0x0f]	390	1			T11	16		T12	43		T19	51
valid_sources[0x10]	268	1			T12	64		T19	40		T20	54
valid_sources[0x11]	535	1			T10	275		T12	31		T19	45
valid_sources[0x12]	307	1			T11	16		T12	65		T19	37
valid_sources[0x13]	313	1			T10	16		T11	16		T12	79
valid_sources[0x14]	288	1			T12	36		T19	40		T20	72
valid_sources[0x15]	310	1			T10	16		T12	36		T19	56
valid_sources[0x16]	341	1			T12	54		T19	52		T20	68
valid_sources[0x17]	247	1			T12	35		T19	45		T20	44
valid_sources[0x18]	612	1			T12	67		T19	43		T20	68
valid_sources[0x19]	346	1			T10	16		T12	48		T19	51
valid_sources[0x1a]	299	1			T12	69		T19	56		T20	53
valid_sources[0x1b]	261	1			T12	39		T19	48		T20	45
valid_sources[0x1c]	386	1			T10	94		T12	62		T19	44
valid_sources[0x1d]	389	1			T12	47		T19	51		T20	42
valid_sources[0x1e]	332	1			T12	88		T19	48		T20	47
valid_sources[0x1f]	301	1			T12	50		T19	52		T20	57
valid_sources[0x20]	322	1			T10	16		T12	70		T19	61

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

18374769

1

T1

4621

T2

3865

T3

8195

values[0x0]

all_enables

biggest_size

8374070

1

T1

5106

T2

4311

T3

8490

values[0x1]

all_enables

biggest_size

5626

1

T10

787

T11

606

T12

652